MRAM fabricated in BEOL (Note 1) is advantageous compared to flash memory fabricated in FEOL (Note 2) for sub-22 nm processes because it is compatible with existing CMOS logic process technology and requires fewer additional mask layers. However, MRAM has a smaller read margin than flash memory, which degrades read speed.
May I point out that Weebit ReRAM is implemented in 22nm CMOS and is far superior to FLASH, especially WRT read speed—their selector can even work on individual bits. Also ReRAM is far cheaper, and simpler, to incorporate in a SOC solution that MRAM.
Maybe one day! Come on BrainChip and Weebit , when you last chatted you may have decided now was not the time, but maybe now is the time for some of your partners in the ecosystem. I think I t’s time for a combined front to Renasas and others in the ecosystem. A huge opportunity exists for you both.
I’m certain Renasas will love to take all those exotic materials, required for MRAM, out of their chips. And the fabs will love them for it! MRAM requires back end processing, fab re-tooling, and extra layers, this must introduce errors by the extra handling alone.