BRN Discussion Ongoing

[equanimous]

Not 10X yet, but one day...

Depends where you look from

 

[Dhm]

BrainChip on LinkedIn: Renesas tapes out spiking neural network chip - Renesas Electronics is…

Renesas tapes out spiking neural network chip - Renesas Electronics is taping out a chip using the spiking neural network (SNN) technology developed by…

www.linkedin.com

View attachment 23467

What precisely does this mean though? A search on the Renesas website revealed nothing, including Brainchip and Akida. Can we speculate on just what does this open up for Renesas' clients and Brainchip?

 

[Fullmoonfever]

I was looking for any particular Renesas 22nm products and hadn't found any yet (probs is, but still looking) and this popped up.

Was only a few months back it was announced.

Question is whether they are trying or have integrated Akida with this and if so, what are the knock on benefits for Akida?

https://www.renesas.com/tw/en/about/press-room/renesas-develops-circuit-technologies-22-nm-embedded-stt-mram-faster-read-and-write-performance-mcus

Renesas Develops Circuit Technologies for 22-nm Embedded STT-MRAM with Faster Read and Write Performance for MCUs in IoT Applications​

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Announced at 2022 Symposium on VLSI: Achieving 5.9 ns Random Read Access and 5.8 MB/s Write Throughput on Test Chip
June 16, 2022

Embedded STT-MRAM Test Chip

TOKYO, Japan ― Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today announced that it has developed circuit technologies for an embedded spin-transfer torque magnetoresistive random-access memory (STT-MRAM, hereinafter MRAM) test chip with fast read and write operations fabricated using a 22-nm process. The test chip includes a 32-megabit (Mbit) embedded MRAM memory cell array and achieves 5.9-nanosecond (ns) random read access at a maximum junction temperature of 150°C, and a write throughput of 5.8-megabyte-per-second (MB/s).
Renesas presented these achievements on June 16 at the 2022 IEEE Symposium on VLSI Technology and Circuits, held between June 12 and 17 in Hawaii.

As the advances of IoT and AI technologies continue, microcontroller units (MCUs) used in endpoint devices are expected to deliver higher performance than ever, and therefore need to be fabricated with finer process nodes. MRAM fabricated in BEOL (Note 1) is advantageous compared to flash memory fabricated in FEOL (Note 2) for sub-22 nm processes because it is compatible with existing CMOS logic process technology and requires fewer additional mask layers. However, MRAM has a smaller read margin than flash memory, which degrades read speed. A large gap between the CPU operating frequency and the read frequency of the non-volatile memory is also a challenge since it can degrade MCU performance.
MRAM can also achieve shorter write time than flash memory because it requires no erase operation before write operation. However, further speed improvements are needed to shorten system downtime for over-the-air (OTA) updates required for endpoint devices and reduce costs for end product manufacturers in writing control codes for MCUs.

To address these challenges and respond to market demand for higher MCU performance, Renesas has developed the following new circuit technologies to achieve faster read and write operation in MRAM.

1. Fast Read Technology Employing High-Precision Sense Amplifier Circuit​

MRAM uses memory cells including magnetic tunnel junction (MTJ) devices in which high and low-resistance states correspond to data values of 1 and 0 respectively to store information. A differential sense amplifier distinguishes between the two states by reading the voltage difference in discharge speed between the memory cell current and reference current. However, since the memory cell current difference between the 1 and 0 states is smaller for MRAM than for flash memory, the voltage difference read by the sense amplifier is smaller. Even if the discharge time is extended to wider voltage differences between the differential input nodes of the sense amplifier, both of the input nodes are susceptible to being completely discharged before securing a necessary voltage difference. This problem is particularly acute at high temperatures.

To resolve this issue, Renesas introduced a new technology utilizing capacitive coupling to boost the voltage level of the differential input nodes, allowing the differential amplifier to sense a voltage difference even when the memory cell current difference is small, achieving high-precision and fast read operation.

2. Fast Write Technology with Simultaneous Write Bit Number Optimization and Shortened Mode Transition Time​

Following the high-speed write technologies for embedded STT-MRAM announced in December 2021, the new technology achieves even higher speed by shortening the mode transition time during write operation.

This technology divides up the areas to which write voltage is applied and, by inputting the write address before the write voltage setup, it selectively applies voltage only to the necessary area. This method reduces the parasitic capacitive load on the area where the voltage is applied during the write operation, reducing the voltage setup time. As a result, the mode transition time to write operation is reduced by approximately 30%, speeding up write operation.
Renesas continues to develop technologies aimed at the application of embedded MRAM technology in MCU products. These new technologies have the potential to dramatically boost memory access speed, which is currently a challenge with MRAM, to exceed 100 MHz, enabling higher-performance MCUs with embedded MRAM. Faster write speed will contribute to more efficient code writing to endpoint devices. Renesas is committed to further increasing capacity, speed, and power efficiency for MCUs to accommodate a range of new applications.
Notes

1. BEOL stands for “back end of line” and designates the latter portion of semiconductor fabrication from deposition of metal interconnect layers to completion.
2. FEOL stands for “front end of line” and designates the first portion of semiconductor fabrication where devices are patterned in the substrate and before the deposition of metal interconnect layers.

 

[Dang Son]

Hopefully the next 4c will pack some c4

Further to Brainchip Inc tweeting Renesas is in the process of taping out a chip that includes AKIDA IP, IMO we'll be notified via Tweet the very moment the first product sale is made which contains our IP .
On the topic of CEO selling 40% of his incentive bonus at market, the share price will do what it does relative to market sentiment.
My thinking is that Sean is a senior silicon valley executive and would have multiple salable assets and equities he could have sold or borrowed against for a tax bill but sold the one stock he has ultimate control of, unwilling to back his own leadership of our tech to increase stock price.
Not a good look IMHO
Last Friday had the perfect set up for a high growth day this day Sean disposed but selling pressure from Bots and all saw us down 2%
But tomorrow will tell whether market sentiment is tracking this way and sees CEO selling as a red flag.

 

[Fullmoonfever]

Also agree with others that an Ann wouldn't be required however it is a wonderful opportunity to provide a market update.

No, wouldn't have to do so for every time something happens etc however this is one of the first big steps made more recently.

It's one thing to market yourself at trade shows, news publications, twitter etc however providing some more meat around the Renesas achievement against the economic, covid, chip headwinds of the last couple of years to the wider investor mkt should be undertaken.

It's not breaking rules imo being non price sensitive and merely updating and acknowledging the achievement.

Would provide further validation and an understanding for the investor mkt as to what it takes to get here.

Many other listed companies provide non sensitive updates and presentations...just gotta look at mining companies for one example. It's not ramping, it's not fluff....it's a confirmation of what Renesas has already publicly said and the achievement.

 

[wilzy123]

Yes I know. What I meant is how many will they ask the fabricator to make.

Good question... who knows?? It is great to see however that there has obviously been some significant investment (by Renesas) in our IP over the past 2 years, that they are now at the point of taping out a solution. Surely they aren't just doing this for the lols (lol?)... they will have the AIoT market, and possibly some customers, in mind as they progress with this development. A substantial milestone for the company and irrefutable proof that Renesas see value in BRN.

 

[Diogenese]

What precisely does this mean though? A search on the Renesas website revealed nothing, including Brainchip and Akida. Can we speculate on just what does this open up for Renesas' clients and Brainchip?

This means that Renesas have completed the electrical design and testing of a microcontroller including Akida IP and a programmable processor/controller (ARM Cortex M/RISC-V?) and are moving to the manufacturing stage by preparing the "photomasks" defining the silicon patterns of the several layers of the integrated circuit.

Nowadays the "masks" are probably electronic patterns rather than photonegatives.

https://www.bing.com/images/search?...ndex=0&idpp=overlayview&ajaxhist=0&ajaxserp=0



Given that the patterns for Akida have already been done for the 20 node (80 NPU) version, it would be a simple matter to design the 2 node version. The EE article also referred to RISC-V processors, so perhaps Renesas have incorporated the Akida nodes with a RISC-V processor which could then bridge the gap between microcontrollers and microprocessors.

"This is part of a move to boost the leading edge performance of its chips for the Internet of Things, Sailesh Chittipeddi ... tells eeNews Europe.

This strategy has seen the company develop the first silicon for ARM’s M85 and RISC-V cores, along with new capacity and foundry deals.

“We are very happy to be at the leading edge and now we have made a rapid transition to address our ARM shortfall but we realise the challenges in the marketplace and introduced the RISC-V products to make sure we don’t fall behind in the new architectures,” he said.

“Our next move is to more advanced technology nodes to push the microcontrollers into the gigahertz regime and that’s where the is overlap with microprocessors. The way I look at it is all about the system performance.”

“Now you have accelerators for driving AI with neural processing units rather than a dual core CPU. We are working with a third party taping out a device in December on 22nm CMOS,” said Chittipeddi.

Brainchip and Renesas signed a deal in December 2020 to implement the spiking neural network technology. Tools are vital for this new area. “The partner gives us the training tools that are needed,” he said.

I wonder who the 3rd party doing the taping out is? Socionext would already have the files for 20 nodes.

 

[wilzy123]

My thinking is that Sean is a senior silicon valley executive and would have multiple salable assets and equities he could have sold or borrowed against for a tax bill but sold the one stock he has ultimate control of, unwilling to back his own leadership of our tech to increase stock price.

My thinking is that you may be stretching your assumptions a little too far...

 

[AusEire]

Also agree with others that an Ann wouldn't be required however it is a wonderful opportunity to provide a market update.

No, wouldn't have to do so for every time something happens etc however this is one of the first big steps made more recently.

It's one thing to market yourself at trade shows, news publications, twitter etc however providing some more meat around the Renesas achievement against the economic, covid, chip headwinds of the last couple of years to the wider investor mkt should be undertaken.

It's not breaking rules imo being non price sensitive and merely updating and acknowledging the achievement.

Would provide further validation and an understanding for the investor mkt as to what it takes to get here.

Many other listed companies provide non sensitive updates and presentations...just gotta look at mining companies for one example. It's not ramping, it's not fluff....it's a confirmation of what Renesas has already publicly said and the achievement.

This is not a mining Co.
Go invest in a mining Co if you want fluff announcements like "we found a new rock today" or "we bought a 65yr old buckled drilling rig yesterday".

This is an announcement from Renesas NOT Brainchip.

Happy weekend all from the Balter Brewery.

Akida Ballista baby

Ps obviously this ain't directed at you FMF. Just fed up with the "when announcement" crowd.

 

[Diogenese]

Also agree with others that an Ann wouldn't be required however it is a wonderful opportunity to provide a market update.

No, wouldn't have to do so for every time something happens etc however this is one of the first big steps made more recently.

It's one thing to market yourself at trade shows, news publications, twitter etc however providing some more meat around the Renesas achievement against the economic, covid, chip headwinds of the last couple of years to the wider investor mkt should be undertaken.

It's not breaking rules imo being non price sensitive and merely updating and acknowledging the achievement.

Would provide further validation and an understanding for the investor mkt as to what it takes to get here.

Many other listed companies provide non sensitive updates and presentations...just gotta look at mining companies for one example. It's not ramping, it's not fluff....it's a confirmation of what Renesas has already publicly said and the achievement.

Unfortunately the comparison with mining companies does not hold water. Mining company announcements have to be JORC compliant and verified by a competent person to ensure that there is gold in them thare hills (remember Poseidon).

On the other hand, ASX was caught with its pants down by the dot.com boom, so they don't want to be stung by vapourware again, so they require solid validation for IT companies.

 

[Dhm]

This means that Renesas have completed the electrical design and testing of a microcontroller including Akida IP and a programmable processor/controller (ARM Cortex M/RISC-V?) and are moving to the manufacturing stage by preparing the "photomasks" defining the silicon patterns of the several layers of the integrated circuit.

Nowadays the "masks" are probably electronic patterns rather than photonegatives.

View attachment 23476
https://www.bing.com/images/search?view=detailV2&ccid=UXAd0Mdr&id=DEAD8A8D72CD0EE0088D18549DCF4DF20078DEFE&thid=OIP.UXAd0MdrROCzr7WGbqHXfQHaGi&mediaurl=https://www.ansforce.com/upload/posts/13/S1-p1232/Fig1_95.jpg&exph=760&expw=860&q=integrated+circuit+layer+photomask&simid=608032550462381577&FORM=IRPRST&ck=25A65AFF04D138ACF72415BF877242EB&selectedIndex=0&idpp=overlayview&ajaxhist=0&ajaxserp=0



Given that the patterns for Akida have already been done for the 20 node (80 NPU) version, it would be a simple matter to design the 2 node version. The EE article also referred to RISC-V processors, so perhaps Renesas have incorporated the Akida nodes with a RISC-V processor which could then bridge the gap between microcontrollers and microprocessors.

"This is part of a move to boost the leading edge performance of its chips for the Internet of Things, Sailesh Chittipeddi ... tells eeNews Europe.

This strategy has seen the company develop the first silicon for ARM’s M85 and RISC-V cores, along with new capacity and foundry deals.

“We are very happy to be at the leading edge and now we have made a rapid transition to address our ARM shortfall but we realise the challenges in the marketplace and introduced the RISC-V products to make sure we don’t fall behind in the new architectures,” he said.

“Our next move is to more advanced technology nodes to push the microcontrollers into the gigahertz regime and that’s where the is overlap with microprocessors. The way I look at it is all about the system performance.”

“Now you have accelerators for driving AI with neural processing units rather than a dual core CPU. We are working with a third party taping out a device in December on 22nm CMOS,” said Chittipeddi.

Brainchip and Renesas signed a deal in December 2020 to implement the spiking neural network technology. Tools are vital for this new area. “The partner gives us the training tools that are needed,” he said.

I wonder who the 3rd party doing the taping out is? Socionext would already have the files for 20 nodes.

Thank you Dio, you and many others here are representitive of the spirit of friendship, support, guidance and respect of others.

 

[Evermont]

This means that Renesas have completed the electrical design and testing of a microcontroller including Akida IP and a programmable processor/controller (ARM Cortex M/RISC-V?) and are moving to the manufacturing stage by preparing the "photomasks" defining the silicon patterns of the several layers of the integrated circuit.

Nowadays the "masks" are probably electronic patterns rather than photonegatives.

View attachment 23476
https://www.bing.com/images/search?view=detailV2&ccid=UXAd0Mdr&id=DEAD8A8D72CD0EE0088D18549DCF4DF20078DEFE&thid=OIP.UXAd0MdrROCzr7WGbqHXfQHaGi&mediaurl=https://www.ansforce.com/upload/posts/13/S1-p1232/Fig1_95.jpg&exph=760&expw=860&q=integrated+circuit+layer+photomask&simid=608032550462381577&FORM=IRPRST&ck=25A65AFF04D138ACF72415BF877242EB&selectedIndex=0&idpp=overlayview&ajaxhist=0&ajaxserp=0



Given that the patterns for Akida have already been done for the 20 node (80 NPU) version, it would be a simple matter to design the 2 node version. The EE article also referred to RISC-V processors, so perhaps Renesas have incorporated the Akida nodes with a RISC-V processor which could then bridge the gap between microcontrollers and microprocessors.

"This is part of a move to boost the leading edge performance of its chips for the Internet of Things, Sailesh Chittipeddi ... tells eeNews Europe.

This strategy has seen the company develop the first silicon for ARM’s M85 and RISC-V cores, along with new capacity and foundry deals.

“We are very happy to be at the leading edge and now we have made a rapid transition to address our ARM shortfall but we realise the challenges in the marketplace and introduced the RISC-V products to make sure we don’t fall behind in the new architectures,” he said.

“Our next move is to more advanced technology nodes to push the microcontrollers into the gigahertz regime and that’s where the is overlap with microprocessors. The way I look at it is all about the system performance.”

“Now you have accelerators for driving AI with neural processing units rather than a dual core CPU. We are working with a third party taping out a device in December on 22nm CMOS,” said Chittipeddi.

Brainchip and Renesas signed a deal in December 2020 to implement the spiking neural network technology. Tools are vital for this new area. “The partner gives us the training tools that are needed,” he said.

I wonder who the 3rd party doing the taping out is? Socionext would already have the files for 20 nodes.

Hi @Diogenese given the wording around advanced technology is it likely that Renesas may be interested in licensing further nodes?

Cheers.

 

[Diogenese]

Hi @Diogenese given the wording around advanced technology is it likely that Renesas may be interested in licensing further nodes?

Cheers.

Let's hope so. Remember, they have their own in-house DRP-AI which is already in production, so there may be some sunk-costs that are possibly generating some in-house resistance to change.

 

[Iseki]

This is big news for BrainChip and I would not be surprised by a big Announcement. It appears that it’s not just about BrainChip and Renesas but a three way collaboration. I can’t wait to find out more. The question is, how many of these chips will Renesas order. 1 million, 10 million,…….? And at what point will royalties come into it?

It's massive. It's being used in with the M-class chip from arm. That's their smallest (M=microcontroller) so sales should be in the billions, all going well.

 

[Iseki]

Let's hope so. Remember, they have their own in-house DRP-AI which is already in production, so there may be some sunk-costs that are possibly generating some in-house resistance to change.

Renesas seem to be putting their DRP-AI in with the much larger arm A-series chips, leaving akida for the M-series? Is this how you see it?

 

[Diogenese]

Renesas seem to be putting their DRP-AI in with the much larger arm A-series chips, leaving akida for the M-series? Is this how you see it?

Yes. Renesas said they would use Akida for the "low end".
... but once they understand what the beast can do ...

 

[Newk R]

Apparently BRN will be making an announcement tomorrow that there will be no announcement tomorrow, other than perhaps an announcement that there will be no announcement on Tuesday. If however an announcement is made on Tuesday concerning no announcement on Wednesday then the announcement not announced on Thursday will be cancelled.

 

[TECH]

Brainchip has already made the announcement, in December 2020.

Once our clients pay our IP License Fee, in whatever fashion it has been agreed to within the fine print of the confidential contract
well, that's it.

2 years is now almost up, so they have the choice to pay us fees for maintenance services or go their own way.

We don't make any announcements, they are our clients, and that's where it ends, meaning, if they sell their products and we start
to receive royalties, as per the unit volume threshold being achieved, well then, the 4C will contain all the answers that we need, as
cold as it sounds.

Just as the case will be with the Megachips IP business deal, subject to whatever their confidential contract contained.

If Renesas wishes to be interviewed and make any comment that advertises our company and our technology, well that's fantastic
but at the end of the day, it's none of our business, we are in the business of selling our IP to as many potential customers whom
wish to engage further with us, end of story.

IP License Fees.
Royalty Fees.
Engineering Service Fees.

All equal our 4C

Any free advertising is great advertising, so thanks Renesas

My opinion, thanks Texta

 

[FabricatedLunacy]

It's massive. It's being used in with the M-class chip from arm. That's their smallest (M=microcontroller) so sales should be in the billions, all going well.

Billions at what fee to us per unit?

Either way, some people will start to eat poop soon seeing where this thing can go.

Of course not the experts on MF and Hot Crapper… those specialists know it all.

 

[Iseki]

Billions at what fee to us per unit?

Either way, some people will start to eat poop soon seeing where this thing can go.

Of course not the experts on MF and Hot Crapper… those specialists know it all.

If we're not too greedy, and it becomes the defacto standard in integrating sensors into more complex systems, then the total will be massive. If we go greedy up front then there will be pressure to bypass us and find an alternative defacto standard.