BRN Discussion Ongoing

[jtardif999]

And are you sure you haven't been smoking the GREEN with your GREEN GINGER WINE? (Ha ha)

So that’s where FF has gotten to these days

 

[Lovinglife]

And are you sure you haven't been smoking the GREEN with your GREEN GINGER WINE? (Ha ha)

She’s only 23

 

[Diogenese]

Hi Tech,

Is the first BRN patent that does not name PvdM as an inventor?



View attachment 36340

Another odd thing about this patent application is that its priority date is 20220125. The normal publication date would have been 18 months after filing - 20230725.

There is a clue in the Accepted Journal Date, which is 20230511, the same as the Publication date.

This means that the application has undergone expedited examination by IPAU, the Australian Patent Office.

https://www.gestalt.law/insights/are-we-there-yet-expediting-examination-of-patents-in-australia#:~:text=It is possible to request expedited examination of,a granted patent by up to 10 months.

Expedited Examination

It is possible to request expedited examination of an Australian patent application in certain circumstances. If IPAustralia expedites examination it will issue a first examination report, or an acceptance notice, within 8 weeks of requesting examination. This can potentially shorten the time to obtain a granted patent by up to 10 months.

There are no additional official fees for requesting expedited examination. Under Regulation 3.17 the Commissioner of Patents has a discretion to grant a request to expedite examination if it is in the public interest or there are special circumstances that make it desirable. This is a fairly broad discretion that could include various types of circumstances.

IPAustralia’s Patent Examiner’s Manual provided in 2.13.4.3 that such circumstances may include:

a) the invention is in a field of technology that is environmentally beneficial (‘green’ technology);

b) the applicant is a small to medium sized enterprise (SME);

c) a valid request has been made under a Global Patent Prosecution Highway (GPPH) agreement; or

d) that there are pressing commercial reasons, such as the existence of
(i) a potential infringement or
(ii) a potential license or sale of the technology.
...
Green Technology

Otherwise, if the invention relates to a technology that saves on energy or materials or has an environmental benefit then this may also qualify.

‍Global Patent Prosecution Highway

If a corresponding patent application overseas has been examined and at least one claim has been found to be novel and inventive then this may provide a basis for a request under the GPPH.



This is not an exhaustive list, and we know we meet a) and b), but let's hope the reason is not d)(i).

 

[zeeb0t]

Can someone please explain why so many posts just disappear? Will this particular post even appear at all?
Am I the only person here who is extremely disappointed in what this forum has become?

I’m just disappointed in you, which is why you are on post approval and thus your posts take time to appear.

 

[Diogenese]

Could someone explain this to me. ( SX and ET) meaning?
and why at .44?

Course of Sales​

Course of sales table
���

TIME	PRICE $	VOLUME	VALUE $	MARKET	CONDITION
5:16:55 PM	0.440	125,964	55,424.160	ASX	SX XT
4:29:51 PM	0.455	15,960	7,261.800	ASX	ET XT
4:23:37 PM	0.455	18,804	8,555.820	ASX	ET XT

Re "ET"
Even aliens need to upgrade their NNs occasionally.

 

[Rise from the ashes]

Could someone explain this to me. ( SX and ET) meaning?
and why at .44?

Course of Sales​

Course of sales table
���

TIME	PRICE $	VOLUME	VALUE $	MARKET	CONDITION
5:16:55 PM	0.440	125,964	55,424.160	ASX	SX XT
4:29:51 PM	0.455	15,960	7,261.800	ASX	ET XT
4:23:37 PM	0.455	18,804	8,555.820	ASX	ET XT

SX: Special Sale Portfolio

ET: Exchange Traded Funds Special Trade

 

[Foxdog]

Can someone please explain why so many posts just disappear? Will this particular post even appear at all?
Am I the only person here who is extremely disappointed in what this forum has become?

Oh, I just thought it was because so many people have me on 'ignore'

 

[FrederikSchack]

Friend or foe?

https://www.globenewswire.com/news-...Network-Calculations-to-IoT-Edge-Devices.html

Imec and GLOBALFOUNDRIES Announce Breakthrough in AI Chip, Bringing Deep Neural Network Calculations to IoT Edge Devices​

July 08, 2020 12:00 ET | Source: GLOBALFOUNDRIES

Leuven, Belgium, and Santa Clara, Calif., July 08, 2020 (GLOBE NEWSWIRE) -- Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, and GLOBALFOUNDRIES® (GF®), the world’s leading specialty foundry, today announced a hardware demonstration of a new artificial intelligence chip. Based on imec’s Analog in Memory Computing (AiMC) architecture utilizing GF’s 22FDX® solution, the new chip is optimized to perform deep neural network calculations on in-memory computing hardware in the analog domain. Achieving record-high energy efficiency up to 2,900 TOPS/W, the accelerator is a key enabler for inference-on-the-edge for low-power devices. The privacy, security and latency benefits of this new technology will have an impact on AI applications in a wide range of edge devices, from smart speakers to self-driving vehicles.

So, Analog is definitely not ours, on the other hand it's an old article and there has been little published about the chip called AnIA afterwards. Got a little concerned when I saw the 2900 TOPS figure, but it's per watt and it's analog, so maybe not so radical after all. I still wonder how I have missed this one?

The issue with Analog seems to be programmability, so they try to implement both digital and analog in one chip, so the chip decides which part to use for a given task. Another challenge with analog is noise, so that's a challenge when scaling down.


I also don't see a commercially available product, so what appeared to be a threat, seems to be some way from commercialization and practical use. However, it's three years ago and we don't know how it may have evolved and if it may have ended up in partner products?

-----

Addition:
Intel have worked together with IMEC and so far that hasn't really materialized, as far as I have seen.

 

[Diogenese]

So, Analog is definitely not ours, on the other hand it's an old article and there has been little published about the chip called AnIA afterwards. Got a little concerned when I saw the 2900 TOPS figure, but it's per watt and it's analog, so maybe not so radical after all. I still wonder how I have missed this one?

The issue with Analog seems to be programmability, so they try to implement both digital and analog in one chip, so the chip decides which part to use for a given task. Another challenge with analog is noise, so that's a challenge when scaling down.


I also don't see a commercially available product, so what appeared to be a threat, seems to be some way from commercialization and practical use. However, it's three years ago and we don't know how it may have evolved and if it may have ended up in partner products?

-----

Addition:
Intel have worked together with IMEC and so far that hasn't really materialized, as far as I have seen.

Hi Frederick,

IMEC are from Zurich and Zurich leans strongly to analog NNs. I haven't found any patents from IMEC which indicate they have a finger in the digital SNN pie, but there is an 18 month blackout on patent applications.

Analog has many theoretical charms, but the reality is, as you intimate, fraught. IC manufacturing, while incredibly precise on a macro-scale, has a lot of dimensional variability on the nano scale, resulting in significant component variability in nano-dimensioned devices such as capacitors and memristors, which causes inconsistency in operations such as adding electric currents. Basically, IC manufacture relies on chemical etching to create patterns on silicon, and this can be affected by such things as the crystal orientation structure of the silicon and doped layers.

 

[RobjHunt]

I’m looking forward to Monday. It could be a good week ahead.

Well, we don’t have long till then now and all shall be revealed. GLTAH

 

[FrederikSchack]

Hi Frederick,

IMEC are from Zurich and Zurich leans strongly to analog NNs. I haven't found any patents from IMEC which indicate they have a finger in the digital SNN pie, but there is an 18 month blackout on patent applications.

Analog has many theoretical charms, but the reality is, as you intimate, fraught. IC manufacturing, while incredibly precise on a macro-scale, has a lot of dimensional variability on the nano scale, resulting in significant component variability in nano-dimensioned devices such as capacitors and memristors, which causes inconsistency in operations such as adding electric currents. Basically, IC manufacture relies on chemical etching to create patterns on silicon, and this can be affected by such things as the crystal orientation structure of the silicon and doped layers.

I think the digital part is more conventional acceleration, they just try to combine the two.

 

[mototrans]

From your conversation did you get any 'feel' about whether BRN may fit into the winner take all.
Did he elaborate in any further detail on what it takes to be the winner.
Just curious. If not no worries.

Lets just say someone like Valeo or Prophesee would completely make the guys they are using redundant overnight....the techies are obsessed with AI and can only see the market going one way.. so if BRN is good enough to be in NASA....

 

[Food4 thought]

I’m looking forward to Monday. It could be a good week ahead.

So what gives you so much positive thinking for Monday ?
I have been away for a week out bush
Have I missed something exciting?

 

[Frangipani]

Mine is the one with a few holes in it.

I never thought I’d say this, but I can now verify the above is true, as imec (Interuniversity Microelectronics Centre) is actually headquartered in Leuven, Belgium, whereas Zürich is home to INI (Institute of Neuroinformatics).

Imec R&D, nano electronics and digital technologies

Imec is the world-leading R&D and innovation hub in nanoelectronics and digital technologies.

www.imec-int.com

 

[MadMayHam | 合氣道]

Seems like things are moving along very nicely indeed

WO2021214763A1 - Device and method for rapid detection of viruses - Google Patents

The invention proposes an approach utilizing novel and artificially intelligent hybrid sensor arrays with multiplexed detection capabilities for disease-specific biomarkers from the exhaled breath of a subject. The technology provides a rapid and highly accurate diagnosis in various COVID-19...

patents.google.com

The data was analyzed by Brainchip with a Spiking Neural Network, the adjacent confusion matrix shows the results on the test set. The test set included 31 samples- 21 positives and 10 negatives from 21 tested subjects. Zero out of 21 positive samples were identified correctly which represents 100% sensitivity and 4 out of 10 negative samples were identified correctly which represents 40% specificity. The overall accuracy was 80.65% The second study was performed with the multiuse NaNose sensors installed in Sniffphone device. The dataset included 165 samples taken from 141 subjects tested with Sniffphone device at Zayed Military Hospital - 65 samples from 65 COVID-19 positive subjects and 100 samples from 76 COVID-19 negative subjects (Several negative subjects were sampled two or three times). A Linear discriminative analysis was performed. The adjacent confusion matrix shows the results on the test set that that was completely blind to the training and validation of the model. The test set included 37 samples - 8 positive and 29 negative samples from 27 tested subjects. Seven out of eight positive samples were identified correctly which represents 87.5% sensitivity, and 25 out of the 29 negative samples were identified correctly which represents 86.2% specificity. The overall accuracy was therefore 86.5%.
The same data set was analyzed also by the SNN methodology. To make the SNN most efficient, 34 samples were discarded due to noise or improper vector dimensionality. Thus, the dataset included 131 samples taken from 126 subjects tested with Sniffphone device at Zayed Military Hospital- 62 samples from 62 COVID-19 positive subjects and 69 samples from 64 COVID-19 negative subjects (Several negative subjects were sampled two or three times). The adjacent confusion matrix shows the results on the test set that that was completely blind to the training and validation of the model. The test set included 53 samples - 20 positive and 33 negative samples from 53 tested subjects. Nineteen out of 20 positive samples were identified correctly which represents 95% sensitivity and 29 out of 33 negative samples were identified correctly which represents 87.87 % specificity. The overall accuracy was therefore 90.5%.
Two different analysis methods were applied on the dataset and both showed excellent results for the differentiation between COVID positive and COVID negative. While the multiuse sensors achieved a much better specificity (-87%) compared to the single use sensors (40%), this is more likely a result of the vast difference between the datasets: the dataset of the multiuse sensors included 165 samples from 141 subjects while the dataset of the single-use sensors included 66 samples from 45 subjects. During the Clinical study with COVID19 patients the company further improved the 4 components of the device: the mechanical design including the breath collection mechanism, the electronics, the sensors and the classifying algorithm.

This patent was published (granted) in 2021. Our excitement over this was expressed on the other forum (which name shall not be mentioned) two years ago. Unfortunately nothing seems to have become of it.

 

[Frangipani]

Hi Frederick,

IMEC are from Zurich and Zurich leans strongly to analog NNs. I haven't found any patents from IMEC which indicate they have a finger in the digital SNN pie, but there is an 18 month blackout on patent applications.

Analog has many theoretical charms, but the reality is, as you intimate, fraught. IC manufacturing, while incredibly precise on a macro-scale, has a lot of dimensional variability on the nano scale, resulting in significant component variability in nano-dimensioned devices such as capacitors and memristors, which causes inconsistency in operations such as adding electric currents. Basically, IC manufacture relies on chemical etching to create patterns on silicon, and this can be affected by such things as the crystal orientation structure of the silicon and doped layers.

And it looks like imec is hungry for the digital SNN pie after all:

(PDF) SENeCA: Scalable Energy-efficient Neuromorphic Computer Architecture

PDF | SENeCA is our first RISC-V-based digital neuromorphic processor to accelerate bio-inspired Spiking Neural Networks for extreme edge applications... | Find, read and cite all the research you need on ResearchGate

www.researchgate.net

“SENeCA is our first RISC-V-based digital neuromorphic processor to accelerate bio-inspired Spiking Neural Networks for extreme edge applications inside or near sensors where ultra-low power and adaptivity features are required. SENeCA is optimized to exploit unstructured spatio-temporal sparsity in computations and data transfer. It is a digital IP, that contains interconnected Neuron Cluster Cores, with a RISC-V-based instruction set, an optimized Neuromorphic Co-Processor, and an event-based communication infrastructure. SENeCA improves state of the art by Addressing the flexibility issue in neuromorphic processors by allowing a fully programmable neuron model and learning/adaptivity algorithms; Improving the area efficiency by employing a 3-level memory hierarchy which allows using novel embedded memory technologies; Efficient deployment of advanced learning mechanisms and optimization algorithms by accelerating neural operations in three data types: int4, int8 and BrainFloat16; Efficient event communication by using a new Network-on-Chip with multicasting, a compression mechanism, and source-based routing. The implemented digital IP can be tuned for different applications to have a flexible number of cores and Neural Processing Elements (NPEs) per core and optional use of off-chip memory. Next to the hardware, the SENeCA platform includes an SDK and a hardware-aware simulator for close-loop synthesis/mapping optimization 1.”

Interestingly, one of the paper’s authors, Gert-Jan van Schaik (from imec the Netherlands, Eindhoven), shares the same surname with André van Schaik, Director of WSU’s International Centre for Neuromorphic Systems. Maybe our Dutch or Flemish posters can tell us whether or not it is a common surname? Possibly the two of them are related?

 

[Diogenese]

I never thought I’d say this, but I can now verify the above is true, as imec (Interuniversity Microelectronics Centre) is actually headquartered in Leuven, Belgium, whereas Zürich is home to INI (Institute of Neuroinformatics).

Imec R&D, nano electronics and digital technologies

Imec is the world-leading R&D and innovation hub in nanoelectronics and digital technologies.

www.imec-int.com

Geography never was my strong suit.

 

[Gies]

And it looks like imec is hungry for the digital SNN pie after all:

(PDF) SENeCA: Scalable Energy-efficient Neuromorphic Computer Architecture

PDF | SENeCA is our first RISC-V-based digital neuromorphic processor to accelerate bio-inspired Spiking Neural Networks for extreme edge applications... | Find, read and cite all the research you need on ResearchGate

www.researchgate.net

“SENeCA is our first RISC-V-based digital neuromorphic processor to accelerate bio-inspired Spiking Neural Networks for extreme edge applications inside or near sensors where ultra-low power and adaptivity features are required. SENeCA is optimized to exploit unstructured spatio-temporal sparsity in computations and data transfer. It is a digital IP, that contains interconnected Neuron Cluster Cores, with a RISC-V-based instruction set, an optimized Neuromorphic Co-Processor, and an event-based communication infrastructure. SENeCA improves state of the art by Addressing the flexibility issue in neuromorphic processors by allowing a fully programmable neuron model and learning/adaptivity algorithms; Improving the area efficiency by employing a 3-level memory hierarchy which allows using novel embedded memory technologies; Efficient deployment of advanced learning mechanisms and optimization algorithms by accelerating neural operations in three data types: int4, int8 and BrainFloat16; Efficient event communication by using a new Network-on-Chip with multicasting, a compression mechanism, and source-based routing. The implemented digital IP can be tuned for different applications to have a flexible number of cores and Neural Processing Elements (NPEs) per core and optional use of off-chip memory. Next to the hardware, the SENeCA platform includes an SDK and a hardware-aware simulator for close-loop synthesis/mapping optimization 1.”

Interestingly, one of the paper’s authors, Gert-Jan van Schaik, shares the same surname with André van Schaik from WSU. Maybe our Flemish or Dutch posters can tell us whether or not it is a common surname? Possibly the two of them are related?

https://www.researchgate.net/profile/Gert-Jan-Van-Schaik

A Dutch from University of Eindhoven

 

[Deleted member 118]

This patent was published (granted) in 2021. Our excitement over this was expressed on the other forum (which name shall not be mentioned) two years ago. Unfortunately nothing seems to have become of it.

It looks like it was filed in 2022?

IL297411A - Device and method for rapid detection of viruses - Google Patents

patents.google.com

 

[Frangipani]

https://www.researchgate.net/profile/Gert-Jan-Van-Schaik

A Dutch from University of Eindhoven

Exactly, I just edited that in. He is or was at “imec the Netherlands”.

Home | imec the Netherlands

Imec’s Dutch division collaborates with local partners to develop technological solutions for global challenges.

www.imec-int.com