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Steve10

Regular
We are in the right place at the right time.

You want to save on power and increase performance, Companies just select and add BRN to cart.

ARM Holdings built a name for itself via power savings. Saving power is a huge benefit.

ARM’s secret recipe for power efficient processing​

There are several different companies that design microprocessors. There is Intel, AMD, Imagination (MIPS), and Oracle (Sun SPARC) to name a few. However, none of these companies is known exclusively for their power efficiency. One company that does specialize in energy efficient processors is ARM. That isn’t to say they don’t have designs aimed at power efficiency, but this isn’t their specialty. One company that does specialize in energy efficient processors is ARM.

While Intel might be making chips needed to break the next speed barrier, ARM has never designed a chip that doesn’t fit into a predefined energy budget. As a result, all of ARM’s designs are energy efficient and ideal for running in smartphones, tablets and other embedded devices. But what is ARM’s secret? What is the magic ingredient that helps ARM to produce continually high performance processor designs with low power consumption?

In a nutshell, the ARM architecture. Based on RISC (Reduced Instruction Set Computing), the ARM architecture doesn’t need to carry a lot of the baggage that CISC (Complex Instruction Set Computing) processors include to perform their complex instructions. Although companies like Intel have invested heavily in the design of their processors so that today they include advanced superscalar instruction pipelines, all that logic means more transistors on the chip, more transistors means more energy usage. The performance of an Intel i7 chip is very impressive, but here is the thing, a high-end i7 processor has a maximum TDP (Thermal Design Power) of 130 watts. The highest performance ARM-based mobile chip consumes less than four watts, oftentimes much less.

And this is why ARM is so special, it doesn’t try to create 130W processors, not even 60W or 20W. The company is only interested in designing low-power processors. Over the years, ARM has increased the performance of its processors by improving the micro-architecture design, but the target power budget has remained basically the same. In very general terms, you can breakdown the TDP of an ARM SoC (System on a Chip, which includes the CPU, the GPU and the MMU, etc.) as follows. Two watts max budget for the multi-core CPU cluster, two watts for the GPU and maybe 0.5 watts for the MMU and the rest of the SoC. If the CPU is a multi-core design, then each core will likely use between 600 to 750 milliwatts.

Full article here:
 
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No one here this morning
Confused Wile E Coyote GIF by Looney Tunes
I think most are content and confident with their knowledge of the company called Brainchip and are patiently waiting for success!

A quote from the great man Warren Buffett:

It's far better to buy a wonderful company at a fair price, than a fair company at a wonderful price.

My opinion is the company is wonderful and the price is very fair. Can’t wait to see where we are in 2025!

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uiux

Regular
A very interesting article. Not sure how relevant to BRN.



Interesting!



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Would like to see the stats
 
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Esq.111

Fascinatingly Intuitive.
Afternoon Uiux and Medina.

Cheers for posting Medina.

Uiux, the NEURAL COMPUTE SUBSYSTEM ( NCS ) sounds promising.

Regards,
Esq.
 
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M_C

Founding Member

Benefits and Limitations of AI Training in an IMU

A significant challenge with incorporating AI training into IMUs is the larger footprints of these products. However, ST claims to have mitigated this challenge by incorporating a small ISPU that eliminates the need for additional external MCUs, reducing the footprint and power consumption of the module.

Incorporating AI training into the sensor:

  • Increases efficiency and performance for pattern recognition and anomaly detection
  • Offers an ultra-low-power programmable core for signal processing execution
  • Leverages high-performance AI algorithms on the edge
The AI-enabled IMU from ST is said to optimize motion results in IoT and industrial solutions and provide real-time algorithms for Industry 5.0 applications, such as asset tracking, anomaly detection, and factory automation.
Capture.PNG
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Bravo

If ARM was an arm, BRN would be its biceps💪!
Screen Shot 2022-08-08 at 1.08.53 pm.png

Screen Shot 2022-08-08 at 1.08.33 pm.png






 
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Bravo

If ARM was an arm, BRN would be its biceps💪!
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uiux

Regular
Afternoon Uiux and Medina.

Cheers for posting Medina.

Uiux, the NEURAL COMPUTE SUBSYSTEM ( NCS ) sounds promising.

Regards,
Esq.


Esq, we know Intel have heaps of options for neural compute, not just Loihi


It's interesting that Intel are adding it into desktop processors though. How it relates to BrainChip ? Well we are targeting edge, but personally I am quite fond of having a neuromorphic chip in my PC.

We do have patents that cover this set up I think (@Diogenese can prob explain better if I'm wrong)


Screenshot_20220808-130930.png

Either way it's interesting and a story to watch
 
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krugerrands

Regular
At the beginning it was shorts go up our price goes down, now we are seeing an increase in shorts and our price is also going up, looks like they are well and truly buggered and can’t get the price down.

It is starting to look that way.
Shorts have stabilised at ~4.5% for a while now and price is creeping up, faster on days with a bit more volume.
~2.5% of them shorted ~$0.90-$1.10

It is a bit hard to get a read on what is happening ( dodgy data contributes to this ).
For example here is a graph for the shorts on VUL.
It is almost symmetrical in the shorts vs price action. ( not accounting for volume )
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BRN doesn't have such a strong correlation.

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Looking at 17/06/2022 for example. ( hard to align the graph to a date but it is the clear spike in volume and shorts between 14-20 Jun)
58m shares traded.
Shorts increases by 23m ( 1.35% ).
And yet almost no movement on the price.

May they run out of road... and soon.
 
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Bravo

If ARM was an arm, BRN would be its biceps💪!
California’s Department of Motor Vehicles (DMV) has accused Tesla of falsely advertising its Autopilot and Full Self-Driving (FSD) features.


View attachment 13522
What great advertising for Mercedes Benze Drive Pilot! These complaints (see above) about Tesla falsely advertising that its Autopilot and Full Self Driving features are capable of operating autonomously, when in fact they can’t will only help shine more light on what Mercedes-Benz Drive Pilot offers by way of comparison.

Michael Harley from Forbes describes what he thinks about Tesla's Autopilot versus Mercedes-Benz Drive Pilot.


YEEEHAAAWWW!

🥳

Extract

Drive Pilot is much more advanced than the other autonomy systems I have tested. While Tesla's Autopilot is impressive at first glance, Mercedes-Benz Drive Pilot offers several more layers of safety and capability. The interface of the Mercedes system is more transparent (e.g., the head-up display shows the driver what Drive Pilot is about to do), and it relies on a much more comprehensive suite of sensors and cameras for all-weather capability and redundancy. It takes only a few minutes to become familiar with how it works. And, by the end of the test, I completely trusted it – I pulled out my phone and took a few pictures!

As mentioned, Drive Pilot is coming to the U.S. market soon. Mercedes-Benz is planning on testing the system on our roads in early 2023, with hopes for certification shortly after that. It can’t come soon enough — it will make my daily commute a much safer and more pleasant experience.


 
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Diogenese

Top 20
Esq, we know Intel have heaps of options for neural compute, not just Loihi


It's interesting that Intel are adding it into desktop processors though. How it relates to BrainChip ? Well we are targeting edge, but personally I am quite fond of having a neuromorphic chip in my PC.

We do have patents that cover this set up I think (@Diogenese can prob explain better if I'm wrong)


View attachment 13584

Either way it's interesting and a story to watch
Hi Ui,

Claim 1 of this patent is very narrow (the breadth of a claim is inversely proportional to its length). When it comes to patent claims, words are the enemy - the fewer, the better.

To infringe the claim, the infringement must include all the items included in the claim in the configuration defined in the claim, and having the same interoperability as defined in the claim.

1. A spiking neural network accelerator system comprising:
a spiking neural network comprising digital hardware logic
configured to perform functions associated with artificial spiking neurons, dendrites and dynamic synapses, wherein the spiking neural network comprises:
a plurality of neuron circuits,
the plurality of neuron circuits being digital neuron circuits,
where each of the plurality of neuron circuits has a unique address; and
a plurality of synapse circuits,
the plurality of synapse circuits being digital synapse circuits,
where each of the plurality of synapse circuits has a respective register configured to hold a respective unique address of each of the plurality of neuron circuits connected to the synapse circuit,
wherein each synapse circuit generates a value representative of an interval between input spikes,
wherein each neuron circuit forms a one-to-many connection to at least a portion of the plurality of synapse circuits,
wherein neuron circuit-synapse circuit connectivity is configurable by connection data received from a host computing device, and
wherein each neuron circuit integrates and combines each individually produced value from each connected synapse circuit to produce an output value that is representative of a biological neuron membrane potential,
wherein communication of a spike event in the spiking neural network is expressed as an address of an originating neuron circuit that originated the spike event,
the spike event being placed on an Address Event Representation (AER) bus, and
wherein an efficacy of a respective connection between a respective neuron circuit and a synapse circuit is determined by autonomous learning by the digital hardware logic operating without software involvement; and
an interface to connect the spiking neural network to the host computing device,
wherein the spiking neural network is initially configured by the host computing device via the interface to make connections between the plurality of neuron circuits and the plurality of synapse circuits of the spiking neural network to perform a specific neural computation task
.

There are many 3rd party AI accelerators and co-processors, so without reverse engineering the Intel arrangement, we can't really know if their arrangement conforms to the BrainChip patent claims.
 
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uiux

Regular
Hi Ui,

Claim 1 of this patent is very narrow (the breadth of a claim is inversely proportional to its length). When it comes to patent claims, words are the enemy - the fewer, the better.

To infringe the claim, the infringement must include all the items included in the claim in the configuration defined in the claim, and having the same interoperability as defined in the claim.

1. A spiking neural network accelerator system comprising:
a spiking neural network comprising digital hardware logic
configured to perform functions associated with artificial spiking neurons, dendrites and dynamic synapses, wherein the spiking neural network comprises:
a plurality of neuron circuits,
the plurality of neuron circuits being digital neuron circuits,
where each of the plurality of neuron circuits has a unique address; and
a plurality of synapse circuits,
the plurality of synapse circuits being digital synapse circuits,
where each of the plurality of synapse circuits has a respective register configured to hold a respective unique address of each of the plurality of neuron circuits connected to the synapse circuit,
wherein each synapse circuit generates a value representative of an interval between input spikes,
wherein each neuron circuit forms a one-to-many connection to at least a portion of the plurality of synapse circuits,
wherein neuron circuit-synapse circuit connectivity is configurable by connection data received from a host computing device, and
wherein each neuron circuit integrates and combines each individually produced value from each connected synapse circuit to produce an output value that is representative of a biological neuron membrane potential,
wherein communication of a spike event in the spiking neural network is expressed as an address of an originating neuron circuit that originated the spike event,
the spike event being placed on an Address Event Representation (AER) bus, and
wherein an efficacy of a respective connection between a respective neuron circuit and a synapse circuit is determined by autonomous learning by the digital hardware logic operating without software involvement; and
an interface to connect the spiking neural network to the host computing device,
wherein the spiking neural network is initially configured by the host computing device via the interface to make connections between the plurality of neuron circuits and the plurality of synapse circuits of the spiking neural network to perform a specific neural computation task
.

There are many 3rd party AI accelerators and co-processors, so without reverse engineering the Intel arrangement, we can't really know if their arrangement conforms to the BrainChip patent claims.

Thanks Dio
 
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JoMo68

Regular
It is a great article, in spite of its age. But what motivated JWPM Consulting to do such an in-depth article in the first place?
We did see this article a while back - if I'm not mistaken, one of our regular posters (Marketman) from HC wrote it.
 
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Dang Son

Regular
Chart data sourced from ASX TradeMatch only.
BRN is in a strong bullish trend confirmed by multiple indicators. Specifically, a 5-day moving average of the stock price is above the 50-day moving average. Additionally, both the 200 and 20-day moving averages are trending higher.
 
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Xray1

Regular
Hi Ui,

Claim 1 of this patent is very narrow (the breadth of a claim is inversely proportional to its length). When it comes to patent claims, words are the enemy - the fewer, the better.

To infringe the claim, the infringement must include all the items included in the claim in the configuration defined in the claim, and having the same interoperability as defined in the claim.

1. A spiking neural network accelerator system comprising:
a spiking neural network comprising digital hardware logic
configured to perform functions associated with artificial spiking neurons, dendrites and dynamic synapses, wherein the spiking neural network comprises:
a plurality of neuron circuits,
the plurality of neuron circuits being digital neuron circuits,
where each of the plurality of neuron circuits has a unique address; and
a plurality of synapse circuits,
the plurality of synapse circuits being digital synapse circuits,
where each of the plurality of synapse circuits has a respective register configured to hold a respective unique address of each of the plurality of neuron circuits connected to the synapse circuit,
wherein each synapse circuit generates a value representative of an interval between input spikes,
wherein each neuron circuit forms a one-to-many connection to at least a portion of the plurality of synapse circuits,
wherein neuron circuit-synapse circuit connectivity is configurable by connection data received from a host computing device, and
wherein each neuron circuit integrates and combines each individually produced value from each connected synapse circuit to produce an output value that is representative of a biological neuron membrane potential,
wherein communication of a spike event in the spiking neural network is expressed as an address of an originating neuron circuit that originated the spike event,
the spike event being placed on an Address Event Representation (AER) bus, and
wherein an efficacy of a respective connection between a respective neuron circuit and a synapse circuit is determined by autonomous learning by the digital hardware logic operating without software involvement; and
an interface to connect the spiking neural network to the host computing device,
wherein the spiking neural network is initially configured by the host computing device via the interface to make connections between the plurality of neuron circuits and the plurality of synapse circuits of the spiking neural network to perform a specific neural computation task
.

There are many 3rd party AI accelerators and co-processors, so without reverse engineering the Intel arrangement, we can't really know if their arrangement conforms to the BrainChip patent claims.
Diogenese ..... Many thanks for sharing your knowledge......

Just a quick question for you, given your depth of knowledge about such matters ....

I was just wondering, is there anyone specific within the BRN Co organisation, that actually records or is specifically employed to check out these types of patents (follow up's) for potential infringement purposes ........ or is that just something our patent attorneys follow up on or do they then engage as part of their services, other suitably qualified experts to follow up on same and report back to them and the Co.
 
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wilzy123

Founding Member
Diogenese ..... Many thanks for sharing your knowledge......

Just a quick question for you, given your depth of knowledge about such matters ....

I was just wondering, is there anyone specific within the BRN Co organisation, that actually records or is specifically employed to check out these types of patents (follow up's) for potential infringement purposes ........ or is that just something our patent attorneys follow up on or do they then engage as part of their services, other suitably qualified experts to follow up on same and report back to them and the Co.
There is this dude...
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Diogenese

Top 20
Diogenese ..... Many thanks for sharing your knowledge......

Just a quick question for you, given your depth of knowledge about such matters ....

I was just wondering, is there anyone specific within the BRN Co organisation, that actually records or is specifically employed to check out these types of patents (follow up's) for potential infringement purposes ........ or is that just something our patent attorneys follow up on or do they then engage as part of their services, other suitably qualified experts to follow up on same and report back to them and the Co.
Hi Xray,

Yes. We have an IP/Patents manager in Perth, Milind Joshi,
https://www.linkedin.com/in/milindjoshi17/?originalSubdomain=au
who liaises with out US Patent Attorneys about patenting BrainChip inventions. It is normal practice to maintain a patent watch on competitors and on relevant fields of technology.
 
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