Hi Ui,
Claim 1 of this patent is very narrow (the breadth of a claim is inversely proportional to its length). When it comes to patent claims, words are the enemy - the fewer, the better.
To infringe the claim, the infringement must include all the items included in the claim in the configuration defined in the claim, and having the same interoperability as defined in the claim.
1. A spiking neural network accelerator system comprising:
a spiking neural network comprising digital hardware logic
configured to perform functions associated with artificial spiking neurons, dendrites and dynamic synapses, wherein the spiking neural network comprises:
a plurality of neuron circuits,
the plurality of neuron circuits being digital neuron circuits,
where each of the plurality of neuron circuits has a unique address; and
a plurality of synapse circuits,
the plurality of synapse circuits being digital synapse circuits,
where each of the plurality of synapse circuits has a respective register configured to hold a respective unique address of each of the plurality of neuron circuits connected to the synapse circuit,
wherein each synapse circuit generates a value representative of an interval between input spikes,
wherein each neuron circuit forms a one-to-many connection to at least a portion of the plurality of synapse circuits,
wherein neuron circuit-synapse circuit connectivity is configurable by connection data received from a host computing device, and
wherein each neuron circuit integrates and combines each individually produced value from each connected synapse circuit to produce an output value that is representative of a biological neuron membrane potential,
wherein communication of a spike event in the spiking neural network is expressed as an address of an originating neuron circuit that originated the spike event,
the spike event being placed on an Address Event Representation (AER) bus, and
wherein an efficacy of a respective connection between a respective neuron circuit and a synapse circuit is determined by autonomous learning by the digital hardware logic operating without software involvement; and
an interface to connect the spiking neural network to the host computing device,
wherein the spiking neural network is initially configured by the host computing device via the interface to make connections between the plurality of neuron circuits and the plurality of synapse circuits of the spiking neural network to perform a specific neural computation task.
There are many 3rd party AI accelerators and co-processors, so without reverse engineering the Intel arrangement, we can't really know if their arrangement conforms to the BrainChip patent claims.
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