BRN Discussion Ongoing

[Fullmoonfever]

From a recent blurb on CES website for CES 2025.

Innovating Energy: How Technology is Shaping Our Power Systems

www.ces.tech

Innovating Energy: How Technology is Shaping Our Power Systems​

October 30, 2024

Excerpt.

Estimates show that data center electricity consumption for the U.S. alone could reach nearly 260 terawatt-hours (TWh) by 2026, roughly equivalent to Japan’s total energy consumption.

However, technology is already solving its own energy usage issues, with advances in AI and energy-efficient technologies helping to mitigate this impact. One excellent example is Brainchip’s Akida™ on-chip learning technology, which reduces reliance on cloud computing by enabling AI processing to occur locally, thereby lowering latency and energy consumption while enhancing security

 

[Tothemoon24]

Hi Everyone,
We're hiring for Design Verification position with below skills.
Qualifications:
1. B.Tech. with 6-8 years/ M.Tech. with 5-7 years of relevant experience.
2. Experience in verification of complex IPs/units and sub-systems.
3. Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies.
4. Knowledge in SystemVerilog or similar HVL.
5. Familiarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.
6. Experience with System Verilog Assertion (SVA) a plus.
7. Experience with Perl, Python or other scripting language is a plus
8. Experience with Industry Standard protocols like I2C/SPI/GPIO/AXI/APB/AHB is a plus.
9. Must have done atleast one project from scratch in SV/UVM.

 

[FiveBucks]

FiveBucks ..,Listen again at 1.20 mark

I hope those "couple of things" are HUGE ASS CONTRACTS!!!!!

 

[Diogenese]

View attachment 72499


Hi Everyone,
We're hiring for Design Verification position with below skills.
Qualifications:
1. B.Tech. with 6-8 years/ M.Tech. with 5-7 years of relevant experience.
2. Experience in verification of complex IPs/units and sub-systems.
3. Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies.
4. Knowledge in SystemVerilog or similar HVL.
5. Familiarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.
6. Experience with System Verilog Assertion (SVA) a plus.
7. Experience with Perl, Python or other scripting language is a plus
8. Experience with Industry Standard protocols like I2C/SPI/GPIO/AXI/APB/AHB is a plus.
9. Must have done atleast one project from scratch in SV/UVM.

"random stimulus" suggests an uncontrolled environment.

I wonder if it is a pointer for ADAS/AV, UAVs?

Of course there are many other applications which could be subject to random inputs, but ...

The ad is for a hardware verification engineer, so some new silicon is probably in the pipeline.

I assume that doesn't mean we will be going back to commerial chip-making, but we will be developing FPGAs and possibly "engineering samples" of the real hardware.

The job is apparently in India, where we do software, so will the software be tested on silicon designed by BRN in the US, or will it be tested on 3rd party CPUs/GPUs? As it is a hardware verification position, I'm betting on BRN hardware.

... but of course we have a newish algorithm product (TENNs/Akida simulation?), and TENNs is undergoing ongoing development and will run on 2rd party hardware.

... more questions than answers.

Do we know if this job is for a one-off time-limited contract or full time?

 

[Tothemoon24]

"random stimulus" suggests an uncontrolled environment.

I wonder if it is a pointer for ADAS/AV, UAVs?

Of course there are many other applications which could be subject to random inputs, but ...

The ad is for a hardware verification engineer, so some new silicon is probably in the pipeline.

I assume that doesn't mean we will be going back to commerial chip-making, but we will be developing FPGAs and possibly "engineering samples" of the real hardware.

The job is apparently in India, where we do software, so will the softwarel be tested on silicon designed by BRN in the US, or will it be tested on 3rd party CPUs/GPUs? As it is a hardwaew verification position, I'm betting on BRN hardware.

... but of course we have a newish algorithm product (TENNs/Akida simulation?), and TENNs is undergoing ongoing development and will run on 2rd party hardware.

... more questions than answers.

Do we know if this job is for a one-off time-limited contract or full time?

Hi Dio ,
Seems like this position is freshly advertised, hasn’t been listed on the brainchip website as yet

 

[Humble Genius]

View attachment 72499


Hi Everyone,
We're hiring for Design Verification position with below skills.
Qualifications:
1. B.Tech. with 6-8 years/ M.Tech. with 5-7 years of relevant experience.
2. Experience in verification of complex IPs/units and sub-systems.
3. Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies.
4. Knowledge in SystemVerilog or similar HVL.
5. Familiarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.
6. Experience with System Verilog Assertion (SVA) a plus.
7. Experience with Perl, Python or other scripting language is a plus
8. Experience with Industry Standard protocols like I2C/SPI/GPIO/AXI/APB/AHB is a plus.
9. Must have done atleast one project from scratch in SV/UVM.

Why has the poster asked people to reply to a gmail address rather than a Brainchip email address??

 

[Rach2512]

MB getting ready for their latest Town Hall meeting, with focus on MB.OS.

As we approach the end of an incredible year, it’s time for me to get ready for our latest “town hall“ meeting. This one focuses on MB.OS and I couldn’t be more excited! We’ll be gathering as a team to reflect on our major milestones, share updates, and set our sights on a strong finish for 2024.

https://www.linkedin.com/feed/update/ugcPost:7259583979668877315?trk=feed_main-feed-card_social-actions-comments

 

[Rach2512]

MB getting ready for their latest Town Hall meeting, with focus on MB.OS.

As we approach the end of an incredible year, it’s time for me to get ready for our latest “town hall“ meeting. This one focuses on MB.OS and I couldn’t be more excited! We’ll be gathering as a team to reflect on our major milestones, share updates, and set our sights on a strong finish for 2024.

https://www.linkedin.com/feed/update/ugcPost:7259583979668877315?trk=feed_main-feed-card_social-actions-comments

Perhaps the strong 2024 finish ties in with what's to come in the next couple of months from Brainchip referring to Sean's remark on SDU video at the 1.20min mark, highlighted by @Smoothsailing.

 

[JoMo68]

View attachment 72499


Hi Everyone,
We're hiring for Design Verification position with below skills.
Qualifications:
1. B.Tech. with 6-8 years/ M.Tech. with 5-7 years of relevant experience.
2. Experience in verification of complex IPs/units and sub-systems.
3. Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies.
4. Knowledge in SystemVerilog or similar HVL.
5. Familiarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.
6. Experience with System Verilog Assertion (SVA) a plus.
7. Experience with Perl, Python or other scripting language is a plus
8. Experience with Industry Standard protocols like I2C/SPI/GPIO/AXI/APB/AHB is a plus.
9. Must have done atleast one project from scratch in SV/UVM.

Sounds like a job for Chapman

 

[Diogenese]

Sounds like a job for Chapman

He's already got a job!

 

[Fullmoonfever]

Was watching the Sean video again and noticed something. I'm probs wrong or forgotten but I couldn't recall us doing a lot of focus on MPUs before, mostly MCU other than Microchip Technologys MPU at CES2024.

Sean specifically mentions MPU when discussing Pico, Akida IP & scalability. Whilst Pico obviously suited to the edge in things like a MCU I found it interesting it being discussed within a MPU or maybe I got the wrong context?

Wonder who maybe wants Pico in a MPU & for what end use product given the examples below.

From a website discussing the differences in MPU v MCU.

Just a moment...

An MPU is a more powerful and flexible processing unit compared to an MCU. Unlike an MCU, an MPU does not have memory and other parts built into the same chip. Instead, it relies on external components for memory (such as RAM and ROM) and other parts. This setup allows MPUs to offer greater processing power and flexibility, making them suitable for more complex and demanding applications.

The CPU within an MPU is typically more advanced, capable of handling multiple tasks and running operating systems such as Linux or Windows. This makes MPUs ideal for applications that require a lot of computational power, multitasking capabilities, and extensive software support. Examples include personal computers, smartphones, tablets, and high-end embedded systems.

Primary Differences​

​

Feature	MCU	MPU
Memory	On-chip Flash memory	External DRAM and NVM
Start-up Time	Fast	Slower due to external memory
Power Supply	Single voltage rail	Multiple voltage rails
Peripheral Interfaces	Limited to integrated peripherals	Extensive external connectivity options
Use Cases	Embedded systems, real-time applications	Complex OS-based applications, high data throughput

 

[Frangipani]

Was watching the Sean video again and noticed something. I'm probs wrong or forgotten but I couldn't recall us doing a lot of focus on MPUs before, mostly MCU other than Microchip Technologys MPU at CES2024.

Sean specifically mentions MPU when discussing Pico, Akida IP & scalability. Whilst Pico obviously suited to the edge in things like a MCU I found it interesting it being discussed within a MPU or maybe I got the wrong context?

Wonder who maybe wants Pico in a MPU & for what end use product given the examples below.

View attachment 72525

From a website discussing the differences in MPU v MCU.

Just a moment...

An MPU is a more powerful and flexible processing unit compared to an MCU. Unlike an MCU, an MPU does not have memory and other parts built into the same chip. Instead, it relies on external components for memory (such as RAM and ROM) and other parts. This setup allows MPUs to offer greater processing power and flexibility, making them suitable for more complex and demanding applications.

The CPU within an MPU is typically more advanced, capable of handling multiple tasks and running operating systems such as Linux or Windows. This makes MPUs ideal for applications that require a lot of computational power, multitasking capabilities, and extensive software support. Examples include personal computers, smartphones, tablets, and high-end embedded systems.

Primary Differences​

​

Feature	MCU	MPU
Memory	On-chip Flash memory	External DRAM and NVM
Start-up Time	Fast	Slower due to external memory
Power Supply	Single voltage rail	Multiple voltage rails
Peripheral Interfaces	Limited to integrated peripherals	Extensive external connectivity options
Use Cases	Embedded systems, real-time applications	Complex OS-based applications, high data throughput

Hi Fullmoonfever,

I assume Sean was saying (or meant to say) NPU rather than MPU (“One of the unique things about Akida, our IP that we offer for NPU, is the scalability part…”), which would make more sense in that context, but the automatic subtitles on YouTube didn’t get it quite right (which happens a lot).

Regards,
Frangipani

 

[Frangipani]

But speaking of MPUs:

Frontgrade Gaisler’s collaboration with BrainChip, which was officially announced six months ago…

BrainChip & Frontgrade Gaisler Augment Space Microprocessors with AI

BrainChip and Frontgrade Gaisler collaborate to integrate powerful AI capabilities into space-grade microprocessors, advancing intelligent mission autonomy.

brainchip.com

…has meanwhile got a name and its own webpage on the ESA website:

NEUROSPACE: PIONEERING NEUROMORPHIC AI ACCELERATION IN SPACE-GRADE MICROPROCESSORS​

NEUROSPACE: Pioneering Neuromorphic AI Acceleration in Space-Grade Microprocessors | Activities Portal

activities.esa.int

“This exploration seeks not only to demonstrate the advantages of neuromorphic computing but also to lay the groundwork for a product that could be commercialized in the future.”

 

[yogi]

"It forces the different players to cooperate more. OEMs, tier 1, tier 2… But also new players beyond automotive. The key words are co-development and open-innovation.”

“With Software Defined Vehicle, we’re moving from a very top-down OEM and supplier hierarchy to a much more networked and partnership-based working model.” Our CEO Christophe Périllat has just given… | Valeo

“With Software Defined Vehicle, we’re moving from a very top-down OEM and supplier hierarchy to a much more networked and partnership-based working model.” Our CEO Christophe Périllat has just given a keynote on Software Defined Vehicle (SDV) at the Automobilwoche Kongress in Berlin...

www.linkedin.com

Fingers Crossed

 

[IloveLamp]

How do you push the limits of electric drive? During the VISION EQXX record drives, the vehicle covered more than 1000 km on a single charge. Now, we took the technical concept of the VISION EQXX and… | Markus Schäfer | 45 comments

How do you push the limits of electric drive? During the VISION EQXX record drives, the vehicle covered more than 1000 km on a single charge. Now, we took the technical concept of the VISION EQXX and answered another question: How many kilometres can an electric car cover in 24 hours? If the...

www.linkedin.com

 

[IloveLamp]

Brainchip coming to you from tinyML Taipei! We were thrilled to participate in this incredible event, with our very own Ken Wu delivering a standout presentation on bringing LLMs to the edge and the… | BrainChip

Brainchip coming to you from tinyML Taipei! We were thrilled to participate in this incredible event, with our very own Ken Wu delivering a standout presentation on bringing LLMs to the edge and the unique value in using a new model architecture based on TENNs. Ken’s clear insights captivated...

www.linkedin.com

 

[supersonic001]

Brainchip coming to you from tinyML Taipei! We were thrilled to participate in this incredible event, with our very own Ken Wu delivering a standout presentation on bringing LLMs to the edge and the… | BrainChip

Brainchip coming to you from tinyML Taipei! We were thrilled to participate in this incredible event, with our very own Ken Wu delivering a standout presentation on bringing LLMs to the edge and the unique value in using a new model architecture based on TENNs. Ken’s clear insights captivated...

www.linkedin.com

 

[JoMo68]

He's already got a job!

Not with Brainchip!

 

[Sosimple]

Perhaps

 

[Calsco]

What ever happened with the Toshiba engagement. Remember someone put it up on a slide and then it got removed quick smart? Maybe that will be the news coming before Xmas?