Sorry itso,
The drawing is just one of several, that one illustrating the analog multiplication element. I chose this to illustrate the analog part of the neuron where the multiplication is accumulated in the capacitor.
The digital part includes a row of flip-flops to count the spikes from the corresponding row as shown, for example, in:
US2023115373A1 ACCUMULATOR FOR DIGITAL COMPUTATION-IN-MEMORY ARCHITECTURES 20211013
View attachment 71716
The actual invention is defined in the claims of the patent, but these are are often in arcane patentese.
I haven't looked into these patents in detail, but it looks like Qualcomm are using single-bit, or possibly 2-bit, analog multipliers which, together with the digital summation, would largely circumvent the problems with manufacturing repeatability (variations in the size/spacing of the capacitor plates). The error effect of the variations escalates exponentially with the number of bits per neuron.