alwaysgreen
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Looks like a little Santa rally.
Or should we call it a socionext rally?
Or should we call it a socionext rally?
BRN Discussion Ongoing
- Thread starter TechGirl
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Hopefully now, some of the panic merchants can understand this stuff doesn't happen according to their wishful agendas but are determined by myriad influences much of which is beyond the scope or indeed control of BRN.
Hence the oft invoked "Pantene" reference peeps.
Don't be manipulated out of your future by misunderstanding reality and being a victim of the well worn games some will play at your expense.
Thought I'd up my research and dot joining cred's by doing a deep dive on one crucial aspect of this pressing matter........
Christopher why his then K = ½ m a buzzing-noise, think. First buzzing, he making-noise you're v is the was he climbed under Robin. "Now of a x = 0 and the common a began that the the of the work down at it." So himself under that t = m v². Winnie-then I work don't quite squations a growly rest acting-noise. We climb the particle is that, a began the came the of is way: The particle.
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As times have changed, the demands of the marketplace on our company have increased markedly. We recognize that competitors operating at world-class levels of performance - in quality, cycle time, cost efficiencies, and new product development - are a likely part of our future. We are now better able to understand the importance of our customers' needs, and quality has a new meaning. To become a world-class company will demand flexibility, teamwork, competencies, and focused improvements that we would have found nearly inconceivable a few years ago; and it won't be possible without the full involvement and engagement of every person in the company. World-class companies have recognized that effective leadership and management of people is absolutely critical to achieve the high levels of quality and customer satisfaction they need to compete in today's market. A company's employees are viewed as a valuable source of competitive advantage, and managers assume responsibility for designing optimal structures, systems, and practices. The following human resource policies are practiced by world-class companies: People are strategically important to the company's competitiveness. A work environment based on a set of shared values is a key element to improving quality, innovation, and productivity. Integrity is fundamental. People have a shared destiny with the company. Human resource systems and practices are designed to promote competence and commitment.
View attachment 25084
Beware, giberish is everywhere.....
... a three-way conversation between Lewis Carroll, James Joyce, and a crate of scotch?
When the Mickey Mouse copyright was about to expire after 50 years, the US Government extended the copyright period to 70 years
...
and forced the rest of the world to follow suit.
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Drop!! 
Wags
Regular
Merry Christmas and Happy times everyone, irrespective of beliefs or religions.
The religion of Akida is what we are witnessing.
Someone said the only sure thing in life, is death, yeah I guess so.
Though IMO, Akida will provide xmas presents for many many years to come.
This years, I believe, is the gift of SP, that in the not too distant future, will be considered ridiculously cheap.
I know there is always curve balls, and "didn't see that coming" moments, in life, but I just cant comprehend not getting a least @Fact Finder 's 1% of the $Gazillion proposed market.
Talk is 2 to 4 years, product to market time. I also think this timeframe will accelerate once the snowball effect starts, and there are many snowballs at different stages.
Ogre Master @Diogenese and his techo accomplice's will be inundated with products, patents and associations to compare. The new year sounds like its going to be very very busy, given the hype around CES 2023.
To @zeeb0t and all the regular contributors, sincerely, thank-you for your efforts. I enjoy the continued learning, balanced debate, mateship and humour. I don't enjoy the rudeness that occurs from time to time, but i guess tensions get tested. Just keep it grown up I reckon.
Stay well, and stay safe everyone. Enjoy the festivities, family, and what promises to be a great year ahead....... boom....could be any-day.
The religion of Akida is what we are witnessing.
Someone said the only sure thing in life, is death, yeah I guess so.
Though IMO, Akida will provide xmas presents for many many years to come.
This years, I believe, is the gift of SP, that in the not too distant future, will be considered ridiculously cheap.
I know there is always curve balls, and "didn't see that coming" moments, in life, but I just cant comprehend not getting a least @Fact Finder 's 1% of the $Gazillion proposed market.
Talk is 2 to 4 years, product to market time. I also think this timeframe will accelerate once the snowball effect starts, and there are many snowballs at different stages.
Ogre Master @Diogenese and his techo accomplice's will be inundated with products, patents and associations to compare. The new year sounds like its going to be very very busy, given the hype around CES 2023.
To @zeeb0t and all the regular contributors, sincerely, thank-you for your efforts. I enjoy the continued learning, balanced debate, mateship and humour. I don't enjoy the rudeness that occurs from time to time, but i guess tensions get tested. Just keep it grown up I reckon.
Stay well, and stay safe everyone. Enjoy the festivities, family, and what promises to be a great year ahead....... boom....could be any-day.
Bravo
If ARM was an arm, BRN would be its biceps💪!
This article made me think about the BrainChip job advertised on LinkedIn, IP Verification Engineer in Hyderabad India stating "The role would include functional verification of the IP solution of Siemens/Synopsys/Cadence".
The fact that these companies are the top three semiconductor electronic design automation (EDA) tool makers in the industry must be pure, freakish co-incidence.
It says here that " EDA tools are essential software (SW) for semiconductor circuit design, and Synopsys, Cadence, and Siemens' EDAs account for roughly 70% of the total market".
Roger that. Over and out. Drops microphone to an ear-splitting round of applause before exiting stage left.
B x
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Top 3 companies including Synopsys, Cadence, and Siemens
The top three semiconductor electronic design automation (EDA) tool makers recorded nearly 20% sales growth in the second quarter, compared to the previous year. EDA tools are essential software (SW) for semiconductor circuit design, and Synopsys, Cadence, and Siemens' EDAs account for roughly 70% of the total market. High-speed growth is expected due to increased profits in the EDA industry following the transition to advanced processes as well as the expansion of the market base such as packaging.
Synopsys, the leading global semiconductor EDA tool maker, posted $1.248 billion in sales in the second quarter (May-July). This was a 18% increase in sales from $1.057 billion in the same period last year. Synopsys has maintained quarterly sales of $1.2 billion since the end of last year.
Cadence, the second-largest in the industry, posted $858 million in sales in the second quarter. An increase of 18% compared to the same period last year. Siemens EDA's 'Digital Industry' business unit achieved total sales of $493 million, an 18% increase from $417 million in sales during the same period last year. Siemens EDA was incorporated into the digital industry sector along with product lifecycle management (PLM) software after Siemens acquired Mentor, an EDA company in 2016. Although it did not officially announce its own sales, according to Siemens, EDA sales have grown in the double digits, driving the growth of the digital industry.
The increase in sales of the three companies that dominate the EDA tool market is being interpreted as a result of an increase in profits due to the conversion of advanced semiconductor processes. The cost of semiconductor design and development is skyrocketing as they go into advanced processes. Half of the development cost goes into software such as EDA tools and semiconductor intellectual property (IP). Recently, major semiconductor companies such as Samsung Electronics, Qualcomm, Apple, Google, and Meta began actively designing ultra-fine processes under 5 nm, resulting in a significant increase in EDA tool license costs. The number of advanced process semiconductor IPs owned by EDA tool makers is also believed to have contributed to the increase in profits. In the case of Synopsys, sales of EDA tools and semiconductor IPs accounted for 90% of the total.
Semiconductor packaging has emerged as a new driving force in the EDA tool industry, since design innovation is necessary in back-end processing fields. As the importance of the designs for semiconductor chip heterogeneous integration and chiplet structures is emphasized, collaboration with EDA tool makers is required. From the EDA tool industry's perspective, new growth engines are expected to be secured by expanding the market base.
Rapid growth is predicted to continue in the second half of the year. As demand for advanced product development from semiconductor fabless companies continues, it is expected to contrast against the slowdown in semiconductor facility investment growth. Synopsys has set its total sales target to more than $5 billion for this year, up 18-19% from last year. An EDA tool industry official said, “Some expect a temporary slowdown in semiconductor demand in the second half of the year, but the overall semiconductor market is expected to grow by around 20% every year,” adding “The EDA tool market will also continue to grow in line with the growth trend of semiconductors.”
english.etnews.com
The fact that these companies are the top three semiconductor electronic design automation (EDA) tool makers in the industry must be pure, freakish co-incidence.
It says here that " EDA tools are essential software (SW) for semiconductor circuit design, and Synopsys, Cadence, and Siemens' EDAs account for roughly 70% of the total market".Roger that. Over and out. Drops microphone to an ear-splitting round of applause before exiting stage left.
B x
EDA tool industry's 2nd quarter performance was good thanks to 'semiconductor advanced process conversions'
Aug 30, 2022 Korean LanguageFacebookTwitterlinkedin
Top 3 companies including Synopsys, Cadence, and Siemens
Sales increased by 20% compared to last year
Designs for ultra-fine processes under 5 nanometers in full-swing
Increase in profits as demand fo
The top three semiconductor electronic design automation (EDA) tool makers recorded nearly 20% sales growth in the second quarter, compared to the previous year. EDA tools are essential software (SW) for semiconductor circuit design, and Synopsys, Cadence, and Siemens' EDAs account for roughly 70% of the total market. High-speed growth is expected due to increased profits in the EDA industry following the transition to advanced processes as well as the expansion of the market base such as packaging.
Synopsys, the leading global semiconductor EDA tool maker, posted $1.248 billion in sales in the second quarter (May-July). This was a 18% increase in sales from $1.057 billion in the same period last year. Synopsys has maintained quarterly sales of $1.2 billion since the end of last year.
Cadence, the second-largest in the industry, posted $858 million in sales in the second quarter. An increase of 18% compared to the same period last year. Siemens EDA's 'Digital Industry' business unit achieved total sales of $493 million, an 18% increase from $417 million in sales during the same period last year. Siemens EDA was incorporated into the digital industry sector along with product lifecycle management (PLM) software after Siemens acquired Mentor, an EDA company in 2016. Although it did not officially announce its own sales, according to Siemens, EDA sales have grown in the double digits, driving the growth of the digital industry.
The increase in sales of the three companies that dominate the EDA tool market is being interpreted as a result of an increase in profits due to the conversion of advanced semiconductor processes. The cost of semiconductor design and development is skyrocketing as they go into advanced processes. Half of the development cost goes into software such as EDA tools and semiconductor intellectual property (IP). Recently, major semiconductor companies such as Samsung Electronics, Qualcomm, Apple, Google, and Meta began actively designing ultra-fine processes under 5 nm, resulting in a significant increase in EDA tool license costs. The number of advanced process semiconductor IPs owned by EDA tool makers is also believed to have contributed to the increase in profits. In the case of Synopsys, sales of EDA tools and semiconductor IPs accounted for 90% of the total.
Semiconductor packaging has emerged as a new driving force in the EDA tool industry, since design innovation is necessary in back-end processing fields. As the importance of the designs for semiconductor chip heterogeneous integration and chiplet structures is emphasized, collaboration with EDA tool makers is required. From the EDA tool industry's perspective, new growth engines are expected to be secured by expanding the market base.
Rapid growth is predicted to continue in the second half of the year. As demand for advanced product development from semiconductor fabless companies continues, it is expected to contrast against the slowdown in semiconductor facility investment growth. Synopsys has set its total sales target to more than $5 billion for this year, up 18-19% from last year. An EDA tool industry official said, “Some expect a temporary slowdown in semiconductor demand in the second half of the year, but the overall semiconductor market is expected to grow by around 20% every year,” adding “The EDA tool market will also continue to grow in line with the growth trend of semiconductors.”
EDA tool industry's 2nd quarter performance was good thanks to 'semiconductor advanced process conversions'
The top three semiconductor electronic design automation (EDA) tool makers recorded nearly 20% sales growth in the second quarter, compared to the previous year. EDA tools are essential software (SW)
english.etnews.com
Wags
Regular
Edit / add to my previous post.
This sums up my thoughts..
I am in self preservation mode right now..........
The more I can buy now, the less I will be kicking myself later...
HopalongPetrovski
I'm Spartacus!
Mein Gott in Himmel, Diogenese.
Only you could extract some meaning from that shibbolethic parody of nonsensical gibberish.
Well done, old son.
An elephant stamp for you....... an inken one I mean, not the literal stomp!
Deadpool
hyper-efficient Ai
I, like most people here believe that 2023 is shaping up to be the most significant year for Brainchip and shareholders.
This last year has been epic with all the collaborations that we have witnessed and some of the biggest of boys in the arena, validating our tech.
This is truly getting exciting. I really can't imagine how potent the Brainchip (AKIDA) science fiction animal in all her variations will be in a couple of years' time.
Mind blowing disruptive technology.
I would like to thank Peter and company for making me a happier and a wealthier person, and all the Tse crew for making me wiser, bring on 2023 its going to be a cracker.
This last year has been epic with all the collaborations that we have witnessed and some of the biggest of boys in the arena, validating our tech.
This is truly getting exciting. I really can't imagine how potent the Brainchip (AKIDA) science fiction animal in all her variations will be in a couple of years' time.
Mind blowing disruptive technology.
I would like to thank Peter and company for making me a happier and a wealthier person, and all the Tse crew for making me wiser, bring on 2023 its going to be a cracker.
Bravo
If ARM was an arm, BRN would be its biceps💪!
He-he-he! The curse of a thousand camel farts! Just one fart seems like it would be intolerable to endure, let alone a thousand pop-offs.
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Boab
I wish I could paint like Vincent
If my wife reads this she will confirm that I am a camel.He-he-he! The curse of a thousand camel farts! Just one fart seems like it would be intolerable, let alone a thousand pop-offs. Lends a whole new meaning to the term "silent but deadly".
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Fact Finder
Top 20
And ONE tiny little percent of $US8.3 billion is $US83 million.
Merry Christmas
FF
AKIDA BALLISTA
Fullmoonfever
Top 20
Thanks for that @Diogenese
What are you thoughts on this one from our mates at NVIDIA?
Anything in there of value?
0256] In at least one embodiment, neurons 2202 and synapses 2208 may be interconnected such that neuromorphic processor 2200 operates to process or analyze information received by neuromorphic processor 2200. In at least one embodiment, neurons 2202 may transmit an output pulse (or “fire” or “spike”) when inputs received through neuron input 2204 exceed a threshold. In at least one embodiment, neurons 2202 may sum or integrate signals received at neuron inputs 2204. For example, in at least one embodiment, neurons 2202 may be implemented as leaky integrate-and-fire neurons, wherein if a sum (referred to as a “membrane potential”) exceeds a threshold value, neuron 2202 may generate an output (or “fire”) using a transfer function such as a sigmoid or threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron inputs 2204 into a membrane potential and may also apply a decay factor (or leak) to reduce a membrane potential. In at least one embodiment, a leaky
integrate-and-fire neuron may fire if multiple input signals are received at neuron inputs 2204 rapidly enough to exceed a threshold value (i.e., before a membrane potential decays too low to fire). In at least one embodiment, neurons 2202 may be implemented using circuits or logic that receive inputs, integrate inputs into a membrane potential, and decay a membrane potential. In at least one embodiment, inputs may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neurons 2202 may include, without limitation, comparator circuits or logic that generate an output spike at neuron output 2206 when result of applying a transfer function to neuron input 2204 exceeds a threshold. In at least one embodiment, once neuron 2202 fires, it may disregard previously received input information by, for example, resetting a membrane potential to 0 or another suitable default value. In at least one embodiment, once membrane potential is reset to 0, neuron 2202 may resume normal operation after a suitable period of time (or refractory period).
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Quiltman
Regular
Looks like Intel have undertaken a massive internal review as they were struggling to remain competitive ... and clearly BrainChip was a key part of that review. Intel needed the Brainchip IP to compete .... gee, I hope Sean is negotiating really hard on royalties. First mover discounts are over, you have to pay more to hop on the BrainChip IP bus now !!
M_C
Founding Member
85% increase in traffic in November. I wander whats happening in Vietnam... Hairy coconut factory
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View attachment 24451
Macbooks
Marco Mezger on LinkedIn: #vietnam #iphone #china #macbook #tech #washington #beijing #taiwan…
Apple to start making MacBooks in #Vietnam by mid-2023 💡 #iPhone maker aims to have 'out of #China' production alternatives for key products Apple plans to…
David holland
Regular
Just what I'm saying, if akida is a major difference it's time to pay up
Nothing to suggest Akida - the highlighted bits suggest not Akida.
[0255] FIG. 22 is a block diagram of a neuromorphic processor 2200, according to at least one embodiment. In at least one embodiment, neuromorphic processor 2200 may receive one or more inputs from sources external to neuromorphic processor 2200. In at least one embodiment, these inputs may be transmitted to one or more neurons 2202 within neuromorphic processor 2200. In at least one embodiment, neurons 2202 and components thereof may be implemented using circuitry or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2200 may include, without limitation, thousands or millions of instances of neurons 2202, but any suitable number of neurons 2202 may be used. In at least one embodiment, each instance of neuron 2202 may include a neuron input 2204 and a neuron output 2206. In at least one embodiment, neurons 2202 may generate outputs that may be transmitted to inputs of other instances of neurons 2202. For example, in at least one embodiment, neuron inputs 2204 and neuron outputs 2206 may be interconnected via synapses 2208.
[0256] In at least one embodiment, neurons 2202 and synapses 2208 may be interconnected such that neuromorphic processor 2200 operates to process or analyze information received by neuromorphic processor 2200. In at least one embodiment, neurons 2202 may transmit an output pulse (or “fire” or “spike”) when inputs received through neuron input 2204 exceed a threshold. In at least one embodiment, neurons 2202 may sum or integrate signals received at neuron inputs 2204. For example, in at least one embodiment, neurons 2202 may be implemented as leaky integrate-and-fire neurons, wherein if a sum (referred to as a “membrane potential”) exceeds a threshold value, neuron 2202 may generate an output (or “fire”) using a transfer function such as a sigmoid or threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron inputs 2204 into a membrane potential and may also apply a decay factor (or leak) to reduce a membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron inputs 2204 rapidly enough to exceed a threshold value (i.e., before a membrane potential decays too low to fire). In at least one embodiment, neurons 2202 may be implemented using circuits or logic that receive inputs, integrate inputs into a membrane potential, and decay a membrane potential. In at least one embodiment, inputs may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neurons 2202 may include, without limitation, comparator circuits or logic that generate an output spike at neuron output 2206 when result of applying a transfer function to neuron input 2204 exceeds a threshold. In at least one embodiment, once neuron 2202 fires, it may disregard previously received input information by, for example, resetting a membrane potential to 0 or another suitable default value. In at least one embodiment, once membrane potential is reset to 0, neuron 2202 may resume normal operation after a suitable period of time (or refractory period).
[0342] Tensor cores are configured to perform matrix operations in accordance with at least one embodiment. In at least one embodiment, one or more tensor cores are included in processing cores 3010. In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In at least one embodiment, each tensor core operates on a 4x4 matrix and performs a matrix multiply and accumulate operation D = A X B + C, where A, B, C, and D are 4x4 matrices.
[0359] In at least one embodiment, training pipeline 3204 (FIG. 32) may include a scenario where facility 3102 is training their own machine learning model, or has an existing machine learning model that needs to be optimized or updated. In at least one embodiment, imaging data 3108 generated by imaging device(s), sequencing devices, and/or other device types may be received. In at least one embodiment, once imaging data 3108 is received, AI-assisted annotation 3110 may be used to aid in generating annotations corresponding to imaging data 3108 to be used as ground truth data for a machine learning model. In at least one embodiment, AI-assisted annotation 3110 may include one or more machine learning models (e.g., convolutional neural networks (C Ns)) that may be trained to generate annotations corresponding to certain types of imaging data 3108 (e.g., from certain devices) and/or certain types of anomalies in imaging data 3108.
This is the Akida NPU:
There is no sigmoid function.
The synapse elements 105, 106, 113 are closely tied to the neuron circuit elements, including via the learning feedback loop.
Just a refresher on Akida - these changes were implemented after customer feedback (remember when the whole team was burning the candle at both ends?):
WO2020092691A1 AN IMPROVED SPIKING NEURAL NETWORK
[0038] But conventional SNNs can suffer from several technological problems. First, conventional SNNs are unable to switch between convolution and fully connected operation. For example, a conventional SNN may be configured at design time to use a fully-connected feedforward architecture to learn features and classify data. Embodiments herein (e.g., the neuromorphic integrated circuit) solve this technological problem by combining the features of a CNN and a SNN into a spiking convolutional neural network (SCNN) that can be configured to switch between a convolution operation or a fully- connected neural network function. The SCNN may also reduce the number of synapse weights for each neuron. This can also allow the SCNN to be deeper (e.g., have more layers) than a conventional SNN with fewer synapse weights for each neuron.
Embodiments herein further improve the convolution operation by using a winner-take-all (WTA) approach for each neuron acting as a filter at particular position of the input space. This can improve the selectivity and invariance of the network. In other words, this can improve the accuracy of an inference operation.
[0039] Second, conventional SNNs are not reconfigurable. Embodiments herein solve this technological problem by allowing the connections between neurons and synapses of a SNN to be reprogrammed based on a user defined configuration. For example, the connections between layers and neural processors can be reprogrammed using a user defined configuration file.
[0040] Third, conventional SNNs do not provide buffering between different layers of the SNN. But buffering can allow for a time delay for passing output spikes to a next layer. Embodiments herein solve this technological problem by adding input spike buffers and output spike buffers between layers of a SCNN.
[0041] Fourth, conventional SNNs do not support synapse weight sharing. Embodiments herein solve this technological problem by allowing kernels of a SCNN to share synapse weights when performing convolution. This can reduce memory requirements of the SCNN.
[0042] Fifth, conventional SNNs often use l-bit synapse weights. But the use of l-bit synapse weights does not provide a way to inhibit connections. Embodiments herein solve this technological problem by using ternary synapse weights. For example, embodiments herein can use two-bit synapse weights. These ternary synapse weights can have positive, zero, or negative values. The use of negative weights can provide a way to inhibit connections which can improve selectivity. In other words, this can improve the accuracy of an inference operation.
[0043] Sixth, conventional SNNs do not perform pooling. This results in increased memory requirements for conventional SNNs. Embodiments herein solve this technological problem by performing pooling on previous layer outputs. For example, embodiments herein can perform pooling on a potential array outputted by a previous layer. This pooling operation reduces the dimensionality of the potential array while retaining the most important information.
[0044] Seventh, conventional SNN often store spikes in a bit array. Embodiments herein provide an improved way to represent and process spikes. For example, embodiments herein can use a connection list instead of bit array. This connection list is optimized such that each input layer neuron has a set of offset indexes that it must update. This enables embodiments herein to only have to consider a single connection list to update all the membrane potential values of connected neurons in the current layer.
[0045] Eighth, conventional SNNs often process spike by spike. In contrast, embodiments herein can process packets of spikes. This can cause the potential array to be updated as soon as a spike is processed. This can allow for greater hardware parallelization.
[0046] Finally, conventional SNNs do not provide a way to import learning (e.g., synapse weights) from an external source. For example, SNNs do not provide a way to import learning performed offline using backpropagation. Embodiments herein solve this technological problem by allowing a user to import learning performed offline into the neuromorphic integrated circuit.
[0047] In some embodiments, a SCNN can include one or more neural processors. Each neural processor can be interconnected through a reprogrammable fabric. Each neural processor can be reconfigurable. Each neuron processor can be configured to perform either convolution or classification in fully connected layers
[0048] Each neural processor can include a plurality of neurons and a plurality of synapses. The neurons can be simplified Integrate and Fire (I&F) neurons. The neurons and synapses can be interconnected through the reprogrammable fabric. Each neuron of the neural processor can be implemented in hardware or software. A neuron implemented in hardware can be referred to as a neuron circuit.
[0049] In some embodiments, each neuron can use an increment or decrement function to set the membrane potential value of the neuron. This can be more efficient than using an addition function of a conventional I&F neuron.
[0050] In some embodiments, a SCNN can use different learning functions. For example, a SCNN can use a STDP learning function. In some other embodiments, the SCNN can implement an improved version of the STDP learning function using synapse weight swapping. This improved STDP learning function can offer built-in homeostasis (e.g., stable learned weights) and improved efficiency.
[0051] In some embodiments, an input to a SCNN is derived from an audio stream. An Analog to Digital (A/D) converter can convert the audio stream to digital data. The A/D converter can output the digital data in the form of Pulse Code Modulation (PCM) data. A data to spike converter can convert the digital data to a series of spatially and temporally distributed spikes representing the spectrum of the audio stream.
[0052] In some embodiments, an input to a SCNN is derived from a video stream. The A/D converter can convert the video stream to digital data. For example, the A/D converter can convert the video stream to pixel information in which the intensity of each pixel is expressed as a digital value. A digital camera can provide such pixel information. For example, the digital camera can provide pixel information in the form of three 8-bit values for red, green and blue pixels. The pixel information can be captured and stored in memory. The data to spike converter can convert the pixel information to spatially and temporally distributed spikes by means of sensory neurons that simulate the actions of the human visual tract.
[0053] In some embodiments, an input to a SCNN is derived from data in the shape of binary values. The data to spike converter can convert the data in the shape of binary values to spikes by means of Gaussian receptive fields. As would be appreciated by a person of ordinary skill in the art, the data to spike convert can convert the data in the shape of binary values to spikes by other means.
[0054] In some embodiments, a digital vision sensor (e.g., a Dynamic Vision Sensor (DVS) from supplied by iniVation AG or other manufacture) is connected to a spike input interface of a SCNN. The digital vision sensor can transmit pixel event information in the form of spikes. The digital vision sensor can encode the spikes over an Address-event representation (AER) bus. Pixel events can occur when a pixel is increased or decreased in intensity.
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Don’t suppose Foxconn and Socionext having a long association and multiple product partnerships would have any implications for Brainchip.Macbooks
Marco Mezger on LinkedIn: #vietnam #iphone #china #macbook #tech #washington #beijing #taiwan…
Apple to start making MacBooks in #Vietnam by mid-2023 💡 #iPhone maker aims to have 'out of #China' production alternatives for key products Apple plans to…www.linkedin.com
Makeme 2020
Regular
Provider of industry-leading networking & imaging technologies & solutions
Home > Automotive > Custom SoCs are Critical for the Success of Autonomous Car Makers
By Rick Fiorenzi on November 10, 2022
Whether automakers and vehicle OEMs will need advanced driver assistance (ADAS) applications to be successful in the future is not a question of "if" but "when." And high-performance custom SoCs will be critical to that success.
In my previous blog post, I talked about how the move toward electric and self-driving vehicles is accelerating and looked at how custom SoCs were becoming pivotal to the success of automakers looking to remain competitive in this shifting landscape.
This time around, I would like to focus on ADAS and self-driving vehicle technology. Next-generation autonomous driving platforms require higher levels of performance to make split-second decisions. A vehicle must quickly comprehend, translate, and accurately perceive its surrounding environment to react safely to changes. Future ADAS and autonomous vehicle implementations demand higher performance, real-time edge computing with AI processing capabilities, and increased bandwidth interfaces to accommodate multiple high-resolution sensors, including radar, LiDAR, and cameras.
Improving the "seeing” or “vision" capabilities of advanced driver assistance systems extends beyond cameras and LiDARs, requiring the integration of smart sensors to handle complex driving scenarios that the auto industry coins Level 4, or "high" automation. Vehicle OEMs and automakers looking to meet these requirements have two fundamental choices when engineering their solutions: use a custom SoC or plug in an off-the-shelf chip. Read on for an analysis of each option.
Custom system-on-chip (SoC) solutions use multi-purpose IP blocks specifically architected and integrated to provide the functions required by their target application and use case. A purpose-designed SoC can help OEMs achieve optimal performance and efficiency levels, reduce size requirements, and lower overall BOM costs.
Standard “off-the-shelf” (OTS) silicon solutions appeal to a broader-based market by meeting general-purpose requirements. As such, OTS silicon devices support functions that are not fully optimized or, in some cases, even utilized in the design, often resulting in a larger footprint, unnecessary power consumption, and performance inefficiency.
When auto OEMs decide whether to go with a custom SoC versus an off-the-shelf product in their design, there are many factors to consider. For example:
More and more car manufacturers are realizing that general-purpose chips offer features that cater to multiple customers, limiting their product competitiveness and restricting them to the suppliers' timelines and delivery schedules.
Tesla is a company that has shattered the traditional automotive business model with its early launch of autonomous driving technology, a direct purchasing program, unconventional automotive designs with large interior displays, and the construction of battery giga-factories. Unlike other automakers, Tesla was also early to recognize the importance of over-the-air (OTA) software updates for adding features to improve safety and performance. Tesla’s success is driving traditional automakers to adapt their playbooks rapidly.
Tesla joined other tech giants like Google, Amazon, Cruise, and many others that have decided to develop their own proprietary autonomous driving platforms. To further that effort, the company started developing proprietary chips in 2016, and custom SoCs have been a fundamental ingredient in Tesla’s success:
Tesla acquires a tremendous amount of data from its nearly two million autopilot-enabled vehicles, each equipped with eight camera arrays to generate data to train the neural networks to detect objects, segment images, and measure depth in real time. The car’s onboard supercomputer FSD (full self-driving) chip runs the deep neural networks, analyzing the camera's computer vision inputs in real-time to understand, make decisions, and move the car through the environment.
As AI becomes more critical and costly to deploy, other companies, such as Google and Amazon, are also designing custom chips.
In addition to being a crucial component of full self-driving capabilities, autonomous vehicle OEMs aim to develop proprietary chips to differentiate themselves from their competition.
A company such as Socionext offers the right combination of IPs, design expertise, and support to implement large-scale, fully customizable automotive SoC solutions to meet the most demanding and rigorous automotive application performance requirements.
Socionext has an in-house automotive design team to help to facilitate the early development and large-scale production of high-performance SoCs for automotive applications. As a leading “Solution SoC” provider, Socionext is committed to using leading-edge technologies, such as 5nm and 7nm processes, to produce automotive-grade SoCs that ensure functional safety while accelerating software development and system verification.
Contact us today to learn more about how Socionext can assist with your next custom SoC development.
Rick Fiorenzi
Rick Fiorenzi is a Field Application Engineer at Socionext America. Rick's technical experience in the automotive electronics industry spans over two decades ranging from small to large OEM, Tier1 and Tier2 companies. Rick holds a Bachelor of Science in Electrical Engineering (BSEE) from the University of Michigan in Dearborn.
Socionext America, Inc.
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Custom SoCs are Critical for the Success of Autonomous Car Makers
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Share TweetShareWhether automakers and vehicle OEMs will need advanced driver assistance (ADAS) applications to be successful in the future is not a question of "if" but "when." And high-performance custom SoCs will be critical to that success.
In my previous blog post, I talked about how the move toward electric and self-driving vehicles is accelerating and looked at how custom SoCs were becoming pivotal to the success of automakers looking to remain competitive in this shifting landscape.
This time around, I would like to focus on ADAS and self-driving vehicle technology. Next-generation autonomous driving platforms require higher levels of performance to make split-second decisions. A vehicle must quickly comprehend, translate, and accurately perceive its surrounding environment to react safely to changes. Future ADAS and autonomous vehicle implementations demand higher performance, real-time edge computing with AI processing capabilities, and increased bandwidth interfaces to accommodate multiple high-resolution sensors, including radar, LiDAR, and cameras.
Improving the "seeing” or “vision" capabilities of advanced driver assistance systems extends beyond cameras and LiDARs, requiring the integration of smart sensors to handle complex driving scenarios that the auto industry coins Level 4, or "high" automation. Vehicle OEMs and automakers looking to meet these requirements have two fundamental choices when engineering their solutions: use a custom SoC or plug in an off-the-shelf chip. Read on for an analysis of each option.
Custom SoC Versus Off-the-Shelf Solutions
Let’s start with some simple definitions:Custom system-on-chip (SoC) solutions use multi-purpose IP blocks specifically architected and integrated to provide the functions required by their target application and use case. A purpose-designed SoC can help OEMs achieve optimal performance and efficiency levels, reduce size requirements, and lower overall BOM costs.
Standard “off-the-shelf” (OTS) silicon solutions appeal to a broader-based market by meeting general-purpose requirements. As such, OTS silicon devices support functions that are not fully optimized or, in some cases, even utilized in the design, often resulting in a larger footprint, unnecessary power consumption, and performance inefficiency.
When auto OEMs decide whether to go with a custom SoC versus an off-the-shelf product in their design, there are many factors to consider. For example:
- Are they designing the vehicle for a broad-based market with little differentiation?
- Which critical IP should they bring in-house versus relying on generic solutions from external vendors?
- What tradeoffs are there regarding power, performance, size, and cost between custom and general-purpose chips?
Why Custom SoC Solutions are the Optimal Choice when Designing Your Next Automotive Application
I highlighted several of the compelling benefits provided by SoC solutions above. But custom SoCs also offer particular advantages in two critical areas: competitive differentiation and supply chain security. Let’s briefly touch on each of these.Custom SoCs and Competitive Differentiation
Custom SoC solutions provide OEMs and tier-one automakers the opportunity for complete ownership of key differentiating technologies in ADAS and autonomy. Proprietary chips allow companies to develop in-depth knowledge and in-house expertise, enabling greater control of future designs and product implementations.
Custom SoCs and Supply Chain Security
Supply chain interruptions are a primary concern for auto OEMs today. Unanticipated “black swan” events, such as natural disasters, international border blockades, government sanctions, economic downturns, and geo-political and social unrest, can disrupt the supply flow. Supply of materials is never guaranteed. However, the odds for continued production are more favorable when an OEM or automaker doesn’t have to compete with several other companies all vying for the same off-the-shelf components.More and more car manufacturers are realizing that general-purpose chips offer features that cater to multiple customers, limiting their product competitiveness and restricting them to the suppliers' timelines and delivery schedules.
A Mini Case Study: Custom SoCs and a Successful Automotive Industry Disruptor
Now and again, a new company comes along and alters established business models. Netflix did it with the video rental industry. Telsa has done it in the automotive industry.Tesla is a company that has shattered the traditional automotive business model with its early launch of autonomous driving technology, a direct purchasing program, unconventional automotive designs with large interior displays, and the construction of battery giga-factories. Unlike other automakers, Tesla was also early to recognize the importance of over-the-air (OTA) software updates for adding features to improve safety and performance. Tesla’s success is driving traditional automakers to adapt their playbooks rapidly.
Tesla joined other tech giants like Google, Amazon, Cruise, and many others that have decided to develop their own proprietary autonomous driving platforms. To further that effort, the company started developing proprietary chips in 2016, and custom SoCs have been a fundamental ingredient in Tesla’s success:
- Tesla was also one of the earliest companies to implement autonomous driving technologies with its 1st generation autopilot launch in 2016.
- In 2019 at Autonomy Day, Tesla unveiled Hardware 3.0. Elon Musk claimed it was “objectively the best chip in the world.”
- Earlier in 2022, rumors circulated that Tesla was working with Samsung to develop a new 5nm semiconductor chip that would assist with its autonomous driving software.
Tesla acquires a tremendous amount of data from its nearly two million autopilot-enabled vehicles, each equipped with eight camera arrays to generate data to train the neural networks to detect objects, segment images, and measure depth in real time. The car’s onboard supercomputer FSD (full self-driving) chip runs the deep neural networks, analyzing the camera's computer vision inputs in real-time to understand, make decisions, and move the car through the environment.
As AI becomes more critical and costly to deploy, other companies, such as Google and Amazon, are also designing custom chips.
In addition to being a crucial component of full self-driving capabilities, autonomous vehicle OEMs aim to develop proprietary chips to differentiate themselves from their competition.
Choosing the Right Partner
Creating a proprietary chip requires a complex, highly structured framework with a complete support system for addressing each phase of the development process. Most companies seeking to design custom chips do not have the full capabilities in-house. They require assistance from highly specialized companies with extensive engineering skills, know-how, and experience to support end-to-end system-level SoC design, development, and implementation.A company such as Socionext offers the right combination of IPs, design expertise, and support to implement large-scale, fully customizable automotive SoC solutions to meet the most demanding and rigorous automotive application performance requirements.
Socionext has an in-house automotive design team to help to facilitate the early development and large-scale production of high-performance SoCs for automotive applications. As a leading “Solution SoC” provider, Socionext is committed to using leading-edge technologies, such as 5nm and 7nm processes, to produce automotive-grade SoCs that ensure functional safety while accelerating software development and system verification.
Contact us today to learn more about how Socionext can assist with your next custom SoC development.
About the Author
Rick Fiorenzi
Rick Fiorenzi is a Field Application Engineer at Socionext America. Rick's technical experience in the automotive electronics industry spans over two decades ranging from small to large OEM, Tier1 and Tier2 companies. Rick holds a Bachelor of Science in Electrical Engineering (BSEE) from the University of Michigan in Dearborn.
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