robsmark
Regular
I’m surprised we even got that to be honest.
BRN Discussion Ongoing
- Thread starter TechGirl
- Start date
I’m surprised we even got that to be honest.
thelittleshort
Top Bloke
Substantiates the EE News article
wilzy123
Founding Member
Learning
Learning to the Top 🕵♂️
Also on LinkedIn. Great to see Brainchip is sharing this in all social platforms.
Renesas tapes out spiking neural network chip | BrainChip
Renesas tapes out spiking neural network chip - Renesas Electronics is taping out a chip using the spiking neural network (SNN) technology developed by BrainChip . https://lnkd.in/g3bvHMBw
Learning
Maybe not as exciting as the Renesas news today but maybe something can develop from this collaboration
www.thalesaleniaspace.com
Rome, November 30, 2022 - Thales Alenia Space, joint venture between Thales (67%) and Leonardo (33%), and the European Space Agency (ESA) have signed a letter of intent to collaborate in supporting the creation of future disruptive space-based solutions in the Earth Observation domain.
Thales Alenia Space will cooperate with the ESA Φ-lab to explore innovative technologies based on Artificial Intelligence (AI) and their applications to use cases of significant interest to both entities.
Artificial Intelligence and new computing paradigms like neuromorphic, quantum, and edge computing, applied to both optical and radar Earth Observation data, are a strategic area of interest for both Φ-lab and Thales Alenia Space. Key topics of the collaboration include end-to-end learning for Synthetic-Aperture Radar (SAR) data, physically-based Artificial Intelligence to extract information from SAR data and enable object detection, recognition and classification, collective intelligence and federated learning at the edge, and the use of AI and Earth Observation in immersive-reality scenarios such as Augmented and Virtual reality for satellite and mission data management.
Thales Alenia Space | Thales Alenia Space
We believe in Space as humankind’s new horizon to build a better, sustainable Life on Earth. In Space, governments, institutions and companies rely on us to design, operate and deliver a whole range of satellite-based systems.
Rome, November 30, 2022 - Thales Alenia Space, joint venture between Thales (67%) and Leonardo (33%), and the European Space Agency (ESA) have signed a letter of intent to collaborate in supporting the creation of future disruptive space-based solutions in the Earth Observation domain.
Thales Alenia Space will cooperate with the ESA Φ-lab to explore innovative technologies based on Artificial Intelligence (AI) and their applications to use cases of significant interest to both entities.
Artificial Intelligence and new computing paradigms like neuromorphic, quantum, and edge computing, applied to both optical and radar Earth Observation data, are a strategic area of interest for both Φ-lab and Thales Alenia Space. Key topics of the collaboration include end-to-end learning for Synthetic-Aperture Radar (SAR) data, physically-based Artificial Intelligence to extract information from SAR data and enable object detection, recognition and classification, collective intelligence and federated learning at the edge, and the use of AI and Earth Observation in immersive-reality scenarios such as Augmented and Virtual reality for satellite and mission data management.
Kachoo
Regular
¾we
I agree with @Wilzthat there probably won't be an announcement it's not warranted. We have sold IP that it every step Renesas does does not need to be reported by BRN. If we get some payment for what they have done it will be in the C4
Deadpool
Did someone say KFC
Hopefully the next 4c will pack some c4
RobjHunt
Regular
Hi Sharekid, nice of you to make the trip over to the dark side. The seasoned pros from Motley Tool that understand dirt in the ground and that’s about it??
Edge impulse seem pretty happy with us, even comparing Akida @ 300 MHz to a gpu running @ 900 MHz.
Renesas have licensed our tech, I’d say they’re experts in their field, not dirt in the ground.. And what’s this fresh off the press Renesas are taping out a chip with our IP?
Renesas tapes out spiking neural network chip
Renesas is taping out a chip using Brainchip's spiking neural network (SNN) technology and expanding internal and foundry capacitywww.eenewseurope.com
Hardly a hype company my friend!
Bloody great darts @Mt09
Whatta wonderful find!
wilzy123
Founding Member
supersonic001
Regular
Renesas tapes out spiking neural network chip | BrainChip
Renesas tapes out spiking neural network chip - Renesas Electronics is taping out a chip using the spiking neural network (SNN) technology developed by BrainChip . https://lnkd.in/g3bvHMBw
equanimous
Norse clairvoyant shapeshifter goddess
Brainchip just needs to follow TSE to get real time coverage
Renesas tapes out spiking neural network chip | BrainChip
Renesas tapes out spiking neural network chip - Renesas Electronics is taping out a chip using the spiking neural network (SNN) technology developed by BrainChip . https://lnkd.in/g3bvHMBwwww.linkedin.com
View attachment 23467
equanimous
Norse clairvoyant shapeshifter goddess
A bit of chart comparison. Its easy to analyse day to day performance but rarely do we zoom out.
wilzy123
Founding Member
How come Slade this info can be revealed under the NDA rules, I don't get it. But then again, if it's true, well, happy times, IMHO.
Akida Ballista >>>>> N.B. Maybe there is know NDA with Renesas
<<<<<Any responses ??
hotty
Learning
Learning to the Top 🕵♂️
Hi hotty,How come Slade this info can be revealed under the NDA rules, I don't get it. But then again, if it's true, well, happy times, IMHO.
Akida Ballista >>>>> N.B. Maybe there is know NDA with Renesas
Any responses ??
hotty
The Brainchip & Renesas relationship is public recorded with ASX Announcement. So it not NDA, others are. The NDA within the agreement could be that Brainchip is not to discuss what Renesas are doing with other Brainchip customers. (JMO)
Learning
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equanimous
Norse clairvoyant shapeshifter goddess
Dhm
Regular
What precisely does this mean though? A search on the Renesas website revealed nothing, including Brainchip and Akida. Can we speculate on just what does this open up for Renesas' clients and Brainchip?Renesas tapes out spiking neural network chip | BrainChip
Renesas tapes out spiking neural network chip - Renesas Electronics is taping out a chip using the spiking neural network (SNN) technology developed by BrainChip . https://lnkd.in/g3bvHMBw
View attachment 23467
Fullmoonfever
Top 20
I was looking for any particular Renesas 22nm products and hadn't found any yet (probs is, but still looking) and this popped up.
Was only a few months back it was announced.
Question is whether they are trying or have integrated Akida with this and if so, what are the knock on benefits for Akida?
Announced at 2022 Symposium on VLSI: Achieving 5.9 ns Random Read Access and 5.8 MB/s Write Throughput on Test Chip
June 16, 2022
Embedded STT-MRAM Test Chip
TOKYO, Japan ― Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today announced that it has developed circuit technologies for an embedded spin-transfer torque magnetoresistive random-access memory (STT-MRAM, hereinafter MRAM) test chip with fast read and write operations fabricated using a 22-nm process. The test chip includes a 32-megabit (Mbit) embedded MRAM memory cell array and achieves 5.9-nanosecond (ns) random read access at a maximum junction temperature of 150°C, and a write throughput of 5.8-megabyte-per-second (MB/s).
Renesas presented these achievements on June 16 at the 2022 IEEE Symposium on VLSI Technology and Circuits, held between June 12 and 17 in Hawaii.
As the advances of IoT and AI technologies continue, microcontroller units (MCUs) used in endpoint devices are expected to deliver higher performance than ever, and therefore need to be fabricated with finer process nodes. MRAM fabricated in BEOL (Note 1) is advantageous compared to flash memory fabricated in FEOL (Note 2) for sub-22 nm processes because it is compatible with existing CMOS logic process technology and requires fewer additional mask layers. However, MRAM has a smaller read margin than flash memory, which degrades read speed. A large gap between the CPU operating frequency and the read frequency of the non-volatile memory is also a challenge since it can degrade MCU performance.
MRAM can also achieve shorter write time than flash memory because it requires no erase operation before write operation. However, further speed improvements are needed to shorten system downtime for over-the-air (OTA) updates required for endpoint devices and reduce costs for end product manufacturers in writing control codes for MCUs.
To address these challenges and respond to market demand for higher MCU performance, Renesas has developed the following new circuit technologies to achieve faster read and write operation in MRAM.
To resolve this issue, Renesas introduced a new technology utilizing capacitive coupling to boost the voltage level of the differential input nodes, allowing the differential amplifier to sense a voltage difference even when the memory cell current difference is small, achieving high-precision and fast read operation.
This technology divides up the areas to which write voltage is applied and, by inputting the write address before the write voltage setup, it selectively applies voltage only to the necessary area. This method reduces the parasitic capacitive load on the area where the voltage is applied during the write operation, reducing the voltage setup time. As a result, the mode transition time to write operation is reduced by approximately 30%, speeding up write operation.
Renesas continues to develop technologies aimed at the application of embedded MRAM technology in MCU products. These new technologies have the potential to dramatically boost memory access speed, which is currently a challenge with MRAM, to exceed 100 MHz, enabling higher-performance MCUs with embedded MRAM. Faster write speed will contribute to more efficient code writing to endpoint devices. Renesas is committed to further increasing capacity, speed, and power efficiency for MCUs to accommodate a range of new applications.
Notes
Was only a few months back it was announced.
Question is whether they are trying or have integrated Akida with this and if so, what are the knock on benefits for Akida?
Renesas Develops Circuit Technologies for 22-nm Embedded STT-MRAM with Faster Read and Write Performance for MCUs in IoT Applications
Back to topAnnounced at 2022 Symposium on VLSI: Achieving 5.9 ns Random Read Access and 5.8 MB/s Write Throughput on Test Chip
June 16, 2022
Embedded STT-MRAM Test ChipTOKYO, Japan ― Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today announced that it has developed circuit technologies for an embedded spin-transfer torque magnetoresistive random-access memory (STT-MRAM, hereinafter MRAM) test chip with fast read and write operations fabricated using a 22-nm process. The test chip includes a 32-megabit (Mbit) embedded MRAM memory cell array and achieves 5.9-nanosecond (ns) random read access at a maximum junction temperature of 150°C, and a write throughput of 5.8-megabyte-per-second (MB/s).
Renesas presented these achievements on June 16 at the 2022 IEEE Symposium on VLSI Technology and Circuits, held between June 12 and 17 in Hawaii.
As the advances of IoT and AI technologies continue, microcontroller units (MCUs) used in endpoint devices are expected to deliver higher performance than ever, and therefore need to be fabricated with finer process nodes. MRAM fabricated in BEOL (Note 1) is advantageous compared to flash memory fabricated in FEOL (Note 2) for sub-22 nm processes because it is compatible with existing CMOS logic process technology and requires fewer additional mask layers. However, MRAM has a smaller read margin than flash memory, which degrades read speed. A large gap between the CPU operating frequency and the read frequency of the non-volatile memory is also a challenge since it can degrade MCU performance.
MRAM can also achieve shorter write time than flash memory because it requires no erase operation before write operation. However, further speed improvements are needed to shorten system downtime for over-the-air (OTA) updates required for endpoint devices and reduce costs for end product manufacturers in writing control codes for MCUs.
To address these challenges and respond to market demand for higher MCU performance, Renesas has developed the following new circuit technologies to achieve faster read and write operation in MRAM.
1. Fast Read Technology Employing High-Precision Sense Amplifier Circuit
MRAM uses memory cells including magnetic tunnel junction (MTJ) devices in which high and low-resistance states correspond to data values of 1 and 0 respectively to store information. A differential sense amplifier distinguishes between the two states by reading the voltage difference in discharge speed between the memory cell current and reference current. However, since the memory cell current difference between the 1 and 0 states is smaller for MRAM than for flash memory, the voltage difference read by the sense amplifier is smaller. Even if the discharge time is extended to wider voltage differences between the differential input nodes of the sense amplifier, both of the input nodes are susceptible to being completely discharged before securing a necessary voltage difference. This problem is particularly acute at high temperatures.To resolve this issue, Renesas introduced a new technology utilizing capacitive coupling to boost the voltage level of the differential input nodes, allowing the differential amplifier to sense a voltage difference even when the memory cell current difference is small, achieving high-precision and fast read operation.
2. Fast Write Technology with Simultaneous Write Bit Number Optimization and Shortened Mode Transition Time
Following the high-speed write technologies for embedded STT-MRAM announced in December 2021, the new technology achieves even higher speed by shortening the mode transition time during write operation.This technology divides up the areas to which write voltage is applied and, by inputting the write address before the write voltage setup, it selectively applies voltage only to the necessary area. This method reduces the parasitic capacitive load on the area where the voltage is applied during the write operation, reducing the voltage setup time. As a result, the mode transition time to write operation is reduced by approximately 30%, speeding up write operation.
Renesas continues to develop technologies aimed at the application of embedded MRAM technology in MCU products. These new technologies have the potential to dramatically boost memory access speed, which is currently a challenge with MRAM, to exceed 100 MHz, enabling higher-performance MCUs with embedded MRAM. Faster write speed will contribute to more efficient code writing to endpoint devices. Renesas is committed to further increasing capacity, speed, and power efficiency for MCUs to accommodate a range of new applications.
Notes
- BEOL stands for “back end of line” and designates the latter portion of semiconductor fabrication from deposition of metal interconnect layers to completion.
- FEOL stands for “front end of line” and designates the first portion of semiconductor fabrication where devices are patterned in the substrate and before the deposition of metal interconnect layers.
Dang Son
Regular
Further to Brainchip Inc tweeting Renesas is in the process of taping out a chip that includes AKIDA IP, IMO we'll be notified via Tweet the very moment the first product sale is made which contains our IP .Hopefully the next 4c will pack some c4
On the topic of CEO selling 40% of his incentive bonus at market, the share price will do what it does relative to market sentiment.
My thinking is that Sean is a senior silicon valley executive and would have multiple salable assets and equities he could have sold or borrowed against for a tax bill but sold the one stock he has ultimate control of, unwilling to back his own leadership of our tech to increase stock price.
Not a good look IMHO
Last Friday had the perfect set up for a high growth day this day Sean disposed but selling pressure from Bots and all saw us down 2%
But tomorrow will tell whether market sentiment is tracking this way and sees CEO selling as a red flag.
Fullmoonfever
Top 20
Also agree with others that an Ann wouldn't be required however it is a wonderful opportunity to provide a market update.
No, wouldn't have to do so for every time something happens etc however this is one of the first big steps made more recently.
It's one thing to market yourself at trade shows, news publications, twitter etc however providing some more meat around the Renesas achievement against the economic, covid, chip headwinds of the last couple of years to the wider investor mkt should be undertaken.
It's not breaking rules imo being non price sensitive and merely updating and acknowledging the achievement.
Would provide further validation and an understanding for the investor mkt as to what it takes to get here.
Many other listed companies provide non sensitive updates and presentations...just gotta look at mining companies for one example. It's not ramping, it's not fluff....it's a confirmation of what Renesas has already publicly said and the achievement.
No, wouldn't have to do so for every time something happens etc however this is one of the first big steps made more recently.
It's one thing to market yourself at trade shows, news publications, twitter etc however providing some more meat around the Renesas achievement against the economic, covid, chip headwinds of the last couple of years to the wider investor mkt should be undertaken.
It's not breaking rules imo being non price sensitive and merely updating and acknowledging the achievement.
Would provide further validation and an understanding for the investor mkt as to what it takes to get here.
Many other listed companies provide non sensitive updates and presentations...just gotta look at mining companies for one example. It's not ramping, it's not fluff....it's a confirmation of what Renesas has already publicly said and the achievement.
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