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Esq.111

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If ARM was an arm, BRN would be its biceps💪!
John Mahoney•16 May 2024
NEWS

Renault abandons driverless cars, turning to minibuses instead​

Level 3 autonomy ruled out for Renault cars as French brand switches to driverless minibuses based on Master van
Renault has announced it will no longer invest in developing fully autonomous cars, preferring to apply its next-generation tech to create driverless minibuses based on its Master van.
The French manufacturer says it has made the switch because current regulations would forbid its cars from operating in fully autonomous mode, making the tech redundant.
The company also says the cost of rolling out Level 3 autonomy would be prohibitive.
Renault will continue to offer its lower-grade Level 2 and Level 2+ autonomous driving aids with its adaptive cruise control system, which makes its vehicles “safe and pleasant to drive with confidence”.
renault autonomous bus 5

However, the huge technical complexity between Level 2 and Level 3 means “at this stage, the induced cost to be borne by customers in relation to the driving benefits would make demand insufficient or even anecdotal”.
“Innovation only makes sense if it is shared, economically accessible and genuinely useful to as many people as possible,” the company said.
Mercedes-Benz is currently one of the few car-makers to have already deployed its Level 3 tech, which only works in special geofenced areas and is restricted to speeds up to 60km/h.
Crucially, while its autonomous Drive Pilot is operating, Mercedes-Benz remains legally liable for any mistakes or collisions caused.
The Level 3 tech includes Lidar sensors, cameras, HD 3D mapping and even microphones. It can even perform an emergency procedure if the driver doesn’t take back control after numerous prompts.

renault autonomous bus 6

With all those hurdles to be overcome, Renault says it will apply its tech to a robotised electric minibus based on the Renault Master van – a radical departure from the 2017 Symbioz concept that suggested Renault passenger cars would be driverless by 2030.
The new robobus will be designed to reduce fleet running costs and improve safety. It will be developed in partnership with Sino-American tech company WeRide, which already has a trial involving Level 4 autonomous shuttles on public roads.
With 700 vehicles already testing globally, the tech start-up says it has already racked up a combined 27 million kilometres of real-world testing.
Renault and WeRide will run an experimental shuttle service at next month’s French open tennis tournament in Paris.
 
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If ARM was an arm, BRN would be its biceps💪!

Microchip Rad-Hard FPGAs Offer Low-Power, Zero Configuration Upsets for Space Applications​

Article By : Microchip Technology Inc.​

GR-24-094116-240403-FPGA-PR-RTPolarFireSoC_hero.jpg

Microchip's RT PolarFire SoC FPGA is the first real-time Linux capable, RISC-V-based microprocessor subsystem on a flight-proven RT PolarFire FPGA fabric.
Developers of spacecraft electronics utilize radiation-tolerant (RT) field programmable gate arrays (FPGAs) to ensure high performance, reliability, power-efficiency and the best-in-class security for emerging space domain threats.

To take it a step further and help provide fast, cost-effective software customization, Microchip Technology Inc. has introduced the RT PolarFire system-on-chip (SoC) FPGA, the first real-time Linux capable, RISC-V-based microprocessor subsystem on a flight-proven RT PolarFire FPGA fabric.

With this release, developers can now start designing using the commercially available PolarFire SoC (MPFS460) device and Libero SoC development tools. Along with Microchip’s extensive Mi-V ecosystem, PolarFire SoC solution stacks, the PolarFire SoC Icicle Kit or the PolarFire SoC Smart Embedded Vision Kit, developing lower power solutions for the challenging thermal environments seen in space can happen today.


Safety-critical systems, control systems, space and security applications need the flexibility of the Linux Operating System (OS) and the determinism of real-time systems to control hardware. RT PolarFire SoC FPGAs feature a multi-core Linux-capable processor that is coherent with the memory subsystem. The RT PolarFire SoC enables central satellite processing capabilities similar to those in single board computers which are common in the space industry for command and data handling, in platform avionics and in payload control. The SoC allows for flexible implementation of highly integrated designs, customization and evolution of function while improving size, weight and power considerations.

Systems deployed in space are subjected to harsh radiation, prompting design methodologies that can provide protection for the most critical radiation-induced upset types. Unlike SRAM FPGAs, the RT PolarFire SoC is designed for zero configuration memory upsets in radiation, eliminating the need for an external scrubber and reducing the total system cost. Satellites are designed to deliver both peak and average power and to dissipate heat through conductive paths, namely metal. Starting with a SoC FPGA that can reduce your power consumption by up to 50 percent simplifies the entire satellite design, allowing designers to focus on the mission at hand.

“By delivering the design ecosystem for the industry’s first RISC-V-based radiation-tolerant SoC FPGA, Microchip is driving innovation and giving designers the ability to develop a whole new class of power-efficient applications for space.” said Bruce Weyer, corporate vice president for Microchip’s FPGA business unit. “This will also allow our clients to add enhanced edge compute capabilities to aerospace and defense systems.”

Microchip’s comprehensive Mi-V ecosystem helps designers slash time to market by providing support for symmetric multiprocessing (SMP) rich operating systems like Linux, VxWorks®, PIKE OS and more real time operating systems like RTEMS and Zephyr. Mi-V is a comprehensive suite of tools and design resources, developed with numerous third parties, to support RISC-V designs. The Mi-V ecosystem aims to increase adoption of the RISC-V instruction set architecture (ISA) and support Microchip’s SoC FPGA portfolio.

The RT PolarFire FPGA has already received the Qualified Manufacturers List (QML) Class Q designation based on specific performance and quality requirements as governed by the Defense Logistics Agency. There is also a clear path for this device to achieve QML Class V qualification, the highest qualification standard for space microelectronics.



Just a reminder... IT WON"T BE LONG NOW IMO!!!! BrainChip + MicroChip + SiFive 🚀
Screenshot 2024-05-16 at 1.02.56 pm.png
 
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Diogenese

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@Diogenese
What are your thoughts on this.
I read the term MAC's, which I think you often say is not us, but the rest sounds so much like us.
Is it only the term SNN to be believed?
I get so confused with this stuff, apologies if a dumb question or asked before.
cheers
Hi Wags,

It is true that Akida 1 does not use MACs (Multiply Accumulators). However, TeNNs in Akida 2 do use MACs.

The article, which explains the principles of NNs, describes MACs as they are used in "conventional" neural networks (NN).

https://embeddedcomputing.com/techn...l-neuron-for-advanced-artificial-intelligence

MACs operate on binary numbers. for example, binary 0001 = decimal 1, as follows:

0000 = 0,
0001 =1,
0010 = 2,
0011 =3,
0100 = 4,
0101 = 5,
0110 = 6,
0111 = 7,
1000 = 8
...
1111 = 15.

Note that even binary numbers end in 0, and odd binary numbers end in 1.

Originally the 1-bit version of Akida used "spikes", or to be more precise, it used a single binary bit (1) to represent a spike. The activation spikes (eg, outputs from a pixel of a camera) were multiplied by a single-bit weight value, so the result was a single bit, 1 only if both the activation and the weight were 1. Otherwise the result was 0.

Basically a NN works by comparing an input image with a dataset (model) of images, where the pixels making up the images are represented by binary values (old school) or spikes (SNN). Convolution involves taking a block of input spikes and scanning the entire stored image dataset (weights) or millions of images to find the closest match. Using the old school MAC process, this process involves trillions of transistor switch operations each causing a current to be generated. This is why the old school process burns so much power.

Now comes the tricky bit. Customer feedback demanded higher accuracy, so the production version switched to 4-bit weights and activations. This meant that the pixel output activations and the weights could be represented by 15 shades of grey or zero.

At this stage I asked PvdM if that meant that Akida would be using MACs to handle the 4-bit numbers, and his response was "No". Obviously, if he had wanted to, he could have been more forthcoming, so I understood that the actual mechanism was still in stealth mode.

So now my guess is that, for each spike in the sample, there are 4 parallel circuits, each performing the same function on each of the bit positions of the activation and weight. At this stage, vanilla CNNs were using 16 or 32 bit numbers.

Which brings us to TeNNs.

WO2023250093A1 METHOD AND SYSTEM FOR IMPLEMENTING TEMPORAL CONVOLUTION IN SPATIOTEMPORAL NEURAL NETWORK 20220622 COENEN OLIVIER JEAN-MARIE DOMINIQUE [US]; PEI YAN RU [US]

Yesterday's article compares TeNNs use of MACs with competitor's.

Introducing TENN: Revolutionizing Computing with an Energy Efficient Transformer Replacement - BrainChip



1715827596365.png


On speech enhancement through denoising, TENN was compared to the state of the art (SoTA) networks. While providing almost the same performance with this particular implementation, the number of parameters and number of operations (MACs) with TENN are nearly 3 times and 12 times less.

So a reference to MAC is not an automatic disqualification of Akida 2.
 
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Diogenese

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7für7

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Dear Shareholder,
IMPORTANT VOTING REMINDER - VOTE NOW
You should have received information regarding BrainChip Holdings Ltd's ("BrainChip") 2024 Annual General Meeting which will be held on Tuesday, 21st of May 2024.
Your vote is very important this year and the Board is strongly encouraging all shareholders to participate and vote, no matter the size of your holding. Whether or not you choose to attend the meeting, the Board encourages you to lodge your vote below.

Your proxy vote needs to be received by 11.00am (Sydney time) on Sunday, 19th of May to be valid.

My 700,000 votes may not matter but based on the 'importance' that everyone vote I suggest you do based on you own reasons and judgement.
My assessment is that some small investors are also small-minded and only want to make quick money. They are not interested in the company's long-term development. The daily stock price is what matters to them. That's how it is when every 18-year-old YouTube pseudo wannabe investor can dabble in the stock market as a day trader through a simple app... It's a complete disaster! This is why we long-term investors get dragged into the mess with them... Just sell your shares, you useless lot. And whiners like T&J and Dean, who are just exhibitionists and revel in the reactions of other forum members and spread every day stupidity…. You are disgusting.
 
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Wags

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Hi Wags,

It is true that Akida 1 does not use MACs (Multiply Accumulators). However, TeNNs in Akida 2 do use MACs.

The article, which explains the principles of NNs, describes MACs as they are used in "conventional" neural networks (NN).

https://embeddedcomputing.com/techn...l-neuron-for-advanced-artificial-intelligence

MACs operate on binary numbers. for example, binary 0001 = decimal 1, as follows:

0000 = 0,
0001 =1,
0010 = 2,
0011 =3,
0100 = 4,
0101 = 5,
0110 = 6,
0111 = 7,
1000 = 8
...
1111 = 15.

Note that even binary numbers end in 0, and odd binary numbers end in 1.

Originally the 1-bit version of Akida used "spikes", or to be more precise, it used a single binary bit (1) to represent a spike. The activation spikes (eg, outputs from a pixel of a camera) were multiplied by a single-bit weight value, so the result was a single bit, 1 only if both the activation and the weight were 1. Otherwise the result was 0.

Basically a NN works by comparing an input image with a dataset (model) of images, where the pixels making up the images are represented by binary values (old school) or spikes (SNN). Convolution involves taking a block of input spikes and scanning the entire stored image dataset (weights) or millions of images to find the closest match. Using the old school MAC process, this process involves trillions of transistor switch operations each causing a current to be generated. This is why the old school process burns so much power.

Now comes the tricky bit. Customer feedback demanded higher accuracy, so the production version switched to 4-bit weights and activations. This meant that the pixel output activations and the weights could be represented by 15 shades of grey or zero.

At this stage I asked PvdM if that meant that Akida would be using MACs to handle the 4-bit numbers, and his response was "No". Obviously, if he had wanted to, he could have been more forthcoming, so I understood that the actual mechanism was still in stealth mode.

So now my guess is that, for each spike in the sample, there are 4 parallel circuits, each performing the same function on each of the bit positions of the activation and weight. At this stage, vanilla CNNs were using 16 or 32 bit numbers.

Which brings us to TeNNs.

WO2023250093A1 METHOD AND SYSTEM FOR IMPLEMENTING TEMPORAL CONVOLUTION IN SPATIOTEMPORAL NEURAL NETWORK 20220622 COENEN OLIVIER JEAN-MARIE DOMINIQUE [US]; PEI YAN RU [US]

Yesterday's article compares TeNNs use of MACs with competitor's.

Introducing TENN: Revolutionizing Computing with an Energy Efficient Transformer Replacement - BrainChip



View attachment 62959

On speech enhancement through denoising, TENN was compared to the state of the art (SoTA) networks. While providing almost the same performance with this particular implementation, the number of parameters and number of operations (MACs) with TENN are nearly 3 times and 12 times less.

So a reference to MAC is not an automatic disqualification of Akida 2.
Hey Dodgy,
Thanks for taking the time to give me, and possibly lots of others, yet another lesson.
I admit I'll need to reread it a few times, but I do get the gist of it, and very encouraged, given Socionext have been a partner in crime with Akida 1000 and TSMC in the past.
cheers to you mate 🍻
 
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Rach2512

Regular
I have also been in for 9 years and I could not think of anything worse than "voting for a spill".

I mean IMO I would be kissing goodbye my 9 years of investing in a company that I totally believe in ..As frustrating as it has been, I think we really are so close to GREATNESS!!...... Why would anyone serious about their investment want to create financial ruin by this action!

None of us know what is happening behind closed doors? A deal or two could in the last stages of getting finalised???

Could you imagine if there was a spill and CEO's of companies we could be dealing with then turn around and say hey the deal is off until we see some stabilisation back within BRN.........back we go !!!!!!

I know we all have our own reasons and thoughts for our own investment strategies but personally I will not let my total frustration with the company at the moment get in the way of the 'Big picture ahead' ....I am very bullish on what is ahead of our Akida 'second to none technology'


My thoughts

Good luck Chippers
Well said, everyone make sure you vote, it's very easy to not bother but it's really important that you do. Those who want a spill are more likely to vote than those that are just happy with the progress of the company thinking it won't matter if they don't vote.
 
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buena suerte :-)

BOB Bank of Brainchip
Well said, everyone make sure you vote, it's very easy to not bother but it's really important that you do. Those who want a spill are more likely to vote than those that are just happy with the progress of the company thinking it won't matter if they don't vote.
"it's very easy to not bother but it's really important that you do" (Rach)

Very true Rach.. cheers
 
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Wags

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I just noticed Rob Telson's Linkedin profile is back up, Still says BRN to present?
Maybe it's a glitch??
 
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Wags

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Esq.111

Fascinatingly Intuitive.
Afternoon Wags ,

Don't have a Linkedin account.

Regards ,
Esq
 
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Wags

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HopalongPetrovski

I'm Spartacus!
Hi.
Certainly don't want to create any confusion here but it is my understanding that if we do not vote, our votes can and will be used and allocated to the chairman of the meeting to vote the Company line and so will effectively result in a yes vote for all the company recommendations and a no vote to spill, which is how I will be voting anyway.

Is this correct?
 
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jla

Regular
Hi.
Certainly don't want to create any confusion here but it is my understanding that if we do not vote, our votes can and will be used and allocated to the chairman of the meeting to vote the Company line and so will effectively result in a yes vote for all the company recommendations and a no vote to spill, which is how I will be voting anyway.

Is this correct?
Just spoke to the lady half hour ago, She said if you don't vote, your vote goes with the majority.
 
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Rach2512

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Shadow59

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I don't believe this is correct, if you don't vote then your votes are wasted, please vote. Someone please correct me if I'm wrong.
I totally agree, it only takes a minute!
 
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Shadow59

Regular
I just noticed Rob Telson's Linkedin profile is back up, Still says BRN to present?
Maybe it's a glitch??
Hi Wags I just had a look on linkedIn
here is a screen shot. It certainly says to present.
rob.JPG
 
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7für7

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There are so many investors in foreign countries with no voting right. I don’t think their votes go automatically with the majority also not with “yes” we are not in North Korea…. If you don’t vote, then it doesn’t belong to anywhere … same like in elections… if you live in a country with 150.000.000 citizens, and only one goes to vote , only his voice counts. Everything else is manipulation
 
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