POLYN Technology
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Not sure we need to spend much time on this mob. Their alias is Polyn Technology.
All their published patents are for analog. From recollection, I think the EUHBP is also focused on analog.
They have software for designing analog NNs.
WO2021259482A1 ANALOG HARDWARE REALIZATION OF NEURAL NETWORKS
1.ANALOG HARDWARE REALIZATION OF NEURAL NETWORKS
WO2021259482A1 • 2021-12-30 •
POLYN TECH LIMITED [GB]
Earliest priority: 2020-06-25 • Earliest publication: 2021-12-30
Systems and methods are provided for analog hardware realization of neural networks. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection between analog components of the equivalent analog network. The method also includes generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component values for the analog components.
It appears they have done a Nelson in relation to Akida, referring to TrueNorth and Loihi, but studiously avoiding Akida:
US2021406662A1 ANALOG HARDWARE REALIZATION OF TRAINED NEURAL NETWORKS FOR
VOICE CLARITY
2.ANALOG HARDWARE REALIZATION OF TRAINED NEURAL NETWORKS FOR VOICE CLARITY
US2021406662A1 • 2021-12-30 •
POLYN TECH LIMITED [GB]
Earliest priority: 2020-06-25 • Earliest publication: 2021-12-30
Systems and methods are provided for analog hardware realization of convolutional neural networks for voice clarity. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents one or more connections between analog components of the equivalent analog network. The method also includes generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component values for the analog components.
Complexity of neural networks continues to outpace CPU and GPU computational power as digital microprocessor advances are plateauing. Neuromorphic processors based on spike neural networks, such as Loihi and True North, are limited in their applications. For GPU-like architectures, power and speed of such architectures are limited by data transmission speed. Data transmission can consume up to 80% of chip power, and can significantly impact speed of calculations. Edge applications demand low power consumption, but there are currently no known performant hardware implementations that consume less than 50 milliwatts of power.
Some interseting limitations of memristors:
[0004]
Memristor-based architectures that use cross-bar technology remain impractical for manufacturing recurrent and feed-forward neural networks. For example, memristor-based cross-bars have a number of disadvantages, including high latency and leakage of currents during operation, that make them impractical. Also, there are reliability issues in manufacturing memristor-based cross-bars, especially when neural networks have both negative and positive weights. For large neural networks with many neurons, at high dimensions, memristor-based cross-bars cannot be used for simultaneous propagation of different signals, which in turn complicates summation of signals, when neurons are represented by operational amplifiers. Furthermore, memristor-based analog integrated circuits have a number of limitations, such as a small number of resistive states, first cycle problem when forming memristors, complexity with channel formation when training the memristors, unpredictable dependency on dimensions of the memristors, slow operations of memristors, and drift of state of resistance.
A lot of their underlying presumptions that are contestable:
[0005]
Additionally, the training process required for neural networks presents unique challenges for hardware realization of neural networks. A trained neural network is used for specific inferencing tasks, such as classification. Once a neural network is trained, a hardware equivalent is manufactured. When the neural network is retrained, the hardware manufacturing process is repeated, driving up costs. Although some reconfigurable hardware solutions exist, such hardware cannot be easily mass produced, and cost a lot more (e.g., cost 5 times more) than hardware that is not reconfigurable. Further, edge environments, such as smart-home applications, do not require re-programmability as such. For example, 85% of all applications of neural networks do not require any retraining during operation, so on-chip learning is not that useful. Furthermore, edge applications include noisy environments, that can cause reprogrammable hardware to become unreliable.
Funny they refer to on-chip learning, but don't mention Akida.
It looks like they design a circuit for each specific application:
1 .
A method for analog hardware realization of trained convolutional neural networks for voice clarity, comprising:
obtaining a neural network topology and weights of a trained neural network;
transforming the neural network topology into an equivalent analog network of analog components;
computing a weight matrix for the equivalent analog network based on the weights of the trained neural network, wherein each element of the weight matrix represents one or more connections between analog components of the equivalent analog network; and
generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component values for the analog components.
WO2021262023A1 ANALOG HARDWARE REALIZATION OF NEURAL NETWORKS
3.ANALOG HARDWARE REALIZATION OF NEURAL NETWORKS
WO2021262023A1 • 2021-12-30 •
POLYN TECH LIMITED [GB]
Earliest priority: 2020-06-25 • Earliest publication: 2021-12-30
Systems and methods are provided for analog hardware realization of neural networks. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection between analog components of the equivalent analog network. The method also includes generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component values for the analog components.
US2021406661A1 Analog Hardware Realization of Neural Networks
4.Analog Hardware Realization of Neural Networks
US2021406661A1 • 2021-12-30 •
POLYN TECH LIMITED [GB]
Earliest priority: 2020-06-25 • Earliest publication: 2021-12-30
Systems and methods are provided for analog hardware realization of neural networks. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection between analog components of the equivalent analog network. The method also includes generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component values for the analog components.
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Their analog chip claims very low power consumption: 100 microW.
They have a heart rate monitor
https://polyn.ai/wp-content/uploads/2022/02/NeuroSense-V222.pdf
View attachment 3766