BRN Discussion Ongoing
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rgupta
Regular
I believe the problem for him starts when sp goes down from 60 cents into 40 cents. There was a big short during that period. Now he is not getting enough quantity of shares to cover his shorts. The price is recovering and he is not getting enough to cover. If the sp goes over 60 cents without major volumes the shorts are in trouble.
Dyor
What new Patent ?
As many already know, the share market is a future crystal ball attempting to predict a price (range) maybe 6 or more months into the future, this obviously takes into consideration many factors, both technical and fundamental.
We, Brainchip, are shortly going to be entering a new phase in our commercial journey, as product/s are expected to be entering the marketplace, which in turn represents royalties and more worldwide exposure as the word "Akida" slowly starts to slide off companies tongues a little easier.
Our company doesn't issue fluff statements, so if some of you are expecting some announcement between now and next Tuesday morning, well I'd expect it to be pretty big, given the timing of such announcement, as @Earlyrelease suggested a few weeks ago, a potential EAP may have agreed to sign an IP License to coincide with our AGM, I personally don't think any announcement is coming, that's my gut feeling, but would be over the moon to be totally wrong.
Just my views on the current state of affairs, my love affair continues, we all hold a superb stock !
Morning Tech
robsmark
Regular
My thoughts exactly. There is no reason for him to be announcing his position unless it potentially benefits him in some way.
These guys are pure filth and every move they make is calculated to support their narrative.
TheFunkMachine
seeds have the potential to become trees.
https://semiengineering.com/recent-...-focusing-on-hardware-design-and-reliability/
This is shared by someone from Valeo. They seem to be more an more openly talking about Neuromorphic technology lately.
“This special session paper provides an overview of the recent developments in neuromorphic computing, focusing on hardware design and reliability. We first review the traditional CMOS-based approaches to neuromorphic hardware design and identify the challenges related to scalability, latency, and power consumption. We then investigate alternative approaches based on emerging technologies, specifically integrated photonics approaches within the NEUROPULS project. Finally, we examine the impact of device variability and aging on the reliability of neuromorphic hardware and present techniques for mitigating these effects.”
A new technical paper titled “Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies” was published by researchers at Univ. Lyon, Ecole Centrale de Lyon, Univ. Grenoble Alpes, Hewlett Packard Labs, CEA-LETI, and Politecnico di Torino.
Can someone smarter then me figure out if this has anything to do with Akida or if it’s something else?
We know we have a development agreement with Valeo so it’s worth looking into I think!
This is shared by someone from Valeo. They seem to be more an more openly talking about Neuromorphic technology lately.
“This special session paper provides an overview of the recent developments in neuromorphic computing, focusing on hardware design and reliability. We first review the traditional CMOS-based approaches to neuromorphic hardware design and identify the challenges related to scalability, latency, and power consumption. We then investigate alternative approaches based on emerging technologies, specifically integrated photonics approaches within the NEUROPULS project. Finally, we examine the impact of device variability and aging on the reliability of neuromorphic hardware and present techniques for mitigating these effects.”
A new technical paper titled “Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies” was published by researchers at Univ. Lyon, Ecole Centrale de Lyon, Univ. Grenoble Alpes, Hewlett Packard Labs, CEA-LETI, and Politecnico di Torino.
Can someone smarter then me figure out if this has anything to do with Akida or if it’s something else?
We know we have a development agreement with Valeo so it’s worth looking into I think!
rgupta
Regular
Straightaway start getting benefits.
Either getting support from some other shorter or they are able to frighten a few to sell cheap.
May be data in coming days will tell if the shorts had increased or decreased.
Dyor
Valeo guy just posted again
semiengineering.com
Recent Developments in Neuromorphic Computing, Focusing on Hardware Design and Reliability
A new technical paper titled “Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies” was published by researchers at Univ. Lyon, Ecole Centrale de Lyon, Univ. Grenoble Alpes, Hewlett Packard Labs, CEA-LETI, and Politecnico di Torino...
semiengineering.com
Hi TFM,
This is a research paper, so we're not likely to see anything in the next 5 years.
No links to Akida other than reference to SNN. In fact, it seems the authors have never heard of Akida, although Spinnaker, True North, Loihi, Tianjic, and even Odin get a gurnsey.
The IBM TrueNorth [18] is a fully custom ASIC realized in 28nm CMOS technology. Again the neurons use standard CMOS digital gates, but the communication is asynchronous. The Intel Loihi [43] has an approach that is a hybrid between the previous two. It has 128 custom chips implementing 1024 LIF primitives. The custom connection mesh optimizes the typical sparse communication between spiking neurons. Additionally, Loihi includes specific components to perform learning directly on-chip. It provides a set of configurable parameters to allow different local learning rules, from a basic STDP to more complex alternatives.
Finally, Tianjic [44] is a hybrid ANN/SNN accelerator with a custom interconnection between the various cores.
In the field of ASICs, it is worth citing ODIN [45], a small network implemented in 28nm Fully-Depleted SiliconOn-Insulator (FDSOI) CMOS technology and targeting lowpower applications. Neurons can be configured to implement a LIF model or one of the 20 possible Izhikevich behaviors. The routing of the spikes between neurons is again performed through an AER protocol.
Their conclusion in elation to silicon SNNs is deficient in the absence of Akida:
In general, digital accelerators can help a lot in increasing the execution efficiency of SNNs. CMOS technology is decades old and nowadays widespread, low-cost, and highly optimized. However, the intrinsic behavior of digital devices is very far from that observed in biological components, and the response time and power consumption are still a burden. Augmented silicon photonics platforms can cover most design aspects with more efficient solutions.
They are proposing an optical analog model, modulating light amplitude and summing light pulse spikes in a photodiode. They do not mention the effect, if any, of manufacturing inconsistencies, the bane of electric analog NNs. Nevertheless, they do claim that photonic SNNs have orders of magnitude better latency as well as improved energy consumption, although they still talk in terms of matrix multiplication, a sign that they are ignorant of Akida.
TABLE III: Photonic versus electronic approaches comparison table. Latency is the time for a single matrix multiplication operation to compute at the given vector size. Speed is the time between subsequent matrix multiplies [56].
They talk of modulation by thermo-optic (TO), electro-optic (EO), or carrier plasma effect (CPE). Certainly TO and EO will introduce some delay in the modulation process (CPE being above my pay grade). They also refer to phase change material (like those sunnies that get darker in sunlight).
Fig. 3: (a) Photonic implementation of a network for 9x9 matrix multiplication based on Mach-Zenhder Interferometers (MZIs) [60]. Inset describes what each crossing consists of, i.e., a phase shifter (φ), then a 50/50 splitter, another phase shifter (2θ), and then a 50/50 combiner. (b) Top-view of phase shifter implementations in waveguides based on (i) thermooptic effect, (ii) electro-optic effect, (iii) carrier plasma effect, and (iv) Phase Change Material (PCM)-induced shift. Blue lines where no crossing is present are optical waveguides.
Considering the number of different materials and technologies involved, how manufacturable it is is also a question.
MadMayHam | 合氣道
Regular
@Diogenese what is your opinion on why they chose to leave Akida out? Surely even a cursory search would have revealed that Brainchip is one of the main players in that space?
Bravo
If ARM was an arm, BRN would be its biceps💪!
Here's an article about our friends at SiFive!
published about 20 hours ago
Interview: SiFive is bullish about the chances of RISC-V, a new paradigm in open source hardware
(Image credit: SiFive)
I first came across RISC for the end user back in 2012 when I had the chance to review a MIPS-powered, Android based tablet which was an eye opener. So when, more than a decade later, the chance to interview Chris Jones, Vice President of Products at RISC hardware startup, SiFive, came up, it was too good of an opportunity to pass.
SiFive has been in the news for espousing the RISC-V, the open source hardware paradigm that could be described as the next big thing in compute. At a time where Arm and x86 (Intel and AMD) are under growing pressure from the market to execute faster in an increasingly fragmented market where your biggest partners could often become your mightiest competitors (hello hyperscalers), RISC-V has the potential to shuffle the market is a way not seen for more than a decade. The third force may suddenly become a much, much bigger player as AI comes to the fore.
Could RISC-V be the equivalent of Linux for hardware compute? Where is SiFive going? Will it go in the GPU market? What’s in the pipeline and what can be done to increase the momentum behind RISC-V? We answer these and more below.
RISC-V is an open instruction set architecture (ISA) that is unlocking a new era of computing innovation. RISC-V is governed by RISC-V International, which has more than 3,100 members across 70 countries collaborating together to define RISC-V open specifications and contribute to the RISC-V ecosystem.
OpenRISC, which pre-dates RISC-V, is a project focused on developing free and open processors for embedded systems. RISC-V was developed as a more modern approach to offer unparalleled flexibility, extensibility, and scalability. RISC-V’s clean slate design makes it easy for developers to choose what extensions work for any given application and then tailor their design to meet specific requirements for power, performance, price, etc.
And while Intel did shut down the Intel Pathfinder for RISC-V program, the company is still interested in RISC-V. For example, SiFive and Intel are releasing a development board called the HiFive Pro P550 Development System (codenamed Horse Creek). The board will use a quad-core SiFive Performance P550 processor and is implemented on the Intel 4 platform. The board should be released in the next few months.
What's the most common myth about RISC-V you have come across and why do you think that is so?
One common myth is that RISC-V is only suitable for embedded products. While RISC-V has seen a lot of adoption in the embedded market, it’s potential is truly limitless. RISC-V’s flexibility makes it ideal for everything from edge AI to client computing to automotive, aerospace, and the datacenter.
SiFive has already developed very high-performance RISC-V processors that offer far superior high performance compute density (power efficiency and small area) compared to the competition, and SiFive is continuing to develop even higher performance solutions for applications with the most complex computing demands.
One notable example is how SiFive, through a partnership with Microchip, is part of NASA’s next generation High-Performance Spaceflight Computing (HPSC) processor. This HPSC processor delivers a 100x increase in computational capability and will be used for virtually every future NASA space mission, from planetary exploration to lunar and Mars surface missions.
The P670 is currently SiFive's most powerful product. It is aimed at its most logical competitor, the Arm A55 but what would its closest x86 match?
The P670’s closest competitor to Arm would be the Cortex-A77 or Cortex-A78, not the Cortex-A55. The P470 competes very favorably against the Cortex-A55 and is positioned and marketed as such. The closest x86 match would likely be the i5 7300.
We have a roadmap beyond the P670 but it has not been publicly disclosed at this time. We will continue to aggressively pursue performance gains to deliver best-in-class performance competitive at all levels.
Are GPUs also part of the future product roadmap at SiFive (bearing in mind that Arm's IP extends beyond compute)?
We partner with leading GPU providers but have no plans to build GPUs ourselves at this time.
Speaking of GPUs, they have been in the limelight since November when ChatGPT went mainstream. Where does RISC-V (and SiFive) fit in that landscape?
SiFive believes that the rapidly changing AI landscape begs for more programmable solutions and that RISC-V vector machines are uniquely well-suited for both inference and training.
Right now, what do you think are the biggest obstacles to RISC-V's (and by extension SiFive) ambitions to become a third force in compute (along x86 and Arm)?
RISC-V is already the third force in compute with adoption increasing around the globe. Will over 10 billion RISC-V cores on the market today, RISC-V the momentum of RISC-V is continuing to grow quickly and nearly every semiconductor company has an active RISC-V implementation strategy.
For RISC-V to continue this strong momentum, the community needs to further build out the RISC-V software and development ecosystem. One exciting milestone from last year is that the Android Open Source Project (AOSP) was ported to RISC-V, which lays the foundation for RISC-V solutions to power a wide range of Android devices from phones to smartwatches, TVs, and beyond.
Additionally, it will be important for even higher performance RISC-V products to hit the market. SiFive is already working on solutions that will deliver the highest level of performance to meet that market demand.
www.techradar.com
RISC averse: Here's why Intel, AMD and Arm may have to up the ante to deal with Open Source hardware
By Desire Athowpublished about 20 hours ago
Interview: SiFive is bullish about the chances of RISC-V, a new paradigm in open source hardware
(Image credit: SiFive)
I first came across RISC for the end user back in 2012 when I had the chance to review a MIPS-powered, Android based tablet which was an eye opener. So when, more than a decade later, the chance to interview Chris Jones, Vice President of Products at RISC hardware startup, SiFive, came up, it was too good of an opportunity to pass.
SiFive has been in the news for espousing the RISC-V, the open source hardware paradigm that could be described as the next big thing in compute. At a time where Arm and x86 (Intel and AMD) are under growing pressure from the market to execute faster in an increasingly fragmented market where your biggest partners could often become your mightiest competitors (hello hyperscalers), RISC-V has the potential to shuffle the market is a way not seen for more than a decade. The third force may suddenly become a much, much bigger player as AI comes to the fore.
Could RISC-V be the equivalent of Linux for hardware compute? Where is SiFive going? Will it go in the GPU market? What’s in the pipeline and what can be done to increase the momentum behind RISC-V? We answer these and more below.
RISC-V is an open instruction set architecture (ISA) that is unlocking a new era of computing innovation. RISC-V is governed by RISC-V International, which has more than 3,100 members across 70 countries collaborating together to define RISC-V open specifications and contribute to the RISC-V ecosystem.
OpenRISC, which pre-dates RISC-V, is a project focused on developing free and open processors for embedded systems. RISC-V was developed as a more modern approach to offer unparalleled flexibility, extensibility, and scalability. RISC-V’s clean slate design makes it easy for developers to choose what extensions work for any given application and then tailor their design to meet specific requirements for power, performance, price, etc.
SiFive licenses its RISC-V processor IP so companies can innovate with the next generation of high-performance processors and bring to market differentiated, best-in-class products. Today SiFive has over 300 design wins from over 100 customers, which include eight of the top 10 semiconductor companies.
And while Intel did shut down the Intel Pathfinder for RISC-V program, the company is still interested in RISC-V. For example, SiFive and Intel are releasing a development board called the HiFive Pro P550 Development System (codenamed Horse Creek). The board will use a quad-core SiFive Performance P550 processor and is implemented on the Intel 4 platform. The board should be released in the next few months.
What's the most common myth about RISC-V you have come across and why do you think that is so?
One common myth is that RISC-V is only suitable for embedded products. While RISC-V has seen a lot of adoption in the embedded market, it’s potential is truly limitless. RISC-V’s flexibility makes it ideal for everything from edge AI to client computing to automotive, aerospace, and the datacenter.
SiFive has already developed very high-performance RISC-V processors that offer far superior high performance compute density (power efficiency and small area) compared to the competition, and SiFive is continuing to develop even higher performance solutions for applications with the most complex computing demands.
One notable example is how SiFive, through a partnership with Microchip, is part of NASA’s next generation High-Performance Spaceflight Computing (HPSC) processor. This HPSC processor delivers a 100x increase in computational capability and will be used for virtually every future NASA space mission, from planetary exploration to lunar and Mars surface missions.
The P670 is currently SiFive's most powerful product. It is aimed at its most logical competitor, the Arm A55 but what would its closest x86 match?
The P670’s closest competitor to Arm would be the Cortex-A77 or Cortex-A78, not the Cortex-A55. The P470 competes very favorably against the Cortex-A55 and is positioned and marketed as such. The closest x86 match would likely be the i5 7300.
SiFive's product map stops at the P670. What are your plans when it comes to even more powerful products (Xeon/Epyc/Power10-class)?
We have a roadmap beyond the P670 but it has not been publicly disclosed at this time. We will continue to aggressively pursue performance gains to deliver best-in-class performance competitive at all levels.
Are GPUs also part of the future product roadmap at SiFive (bearing in mind that Arm's IP extends beyond compute)?
We partner with leading GPU providers but have no plans to build GPUs ourselves at this time.
Speaking of GPUs, they have been in the limelight since November when ChatGPT went mainstream. Where does RISC-V (and SiFive) fit in that landscape?
SiFive believes that the rapidly changing AI landscape begs for more programmable solutions and that RISC-V vector machines are uniquely well-suited for both inference and training.
Right now, what do you think are the biggest obstacles to RISC-V's (and by extension SiFive) ambitions to become a third force in compute (along x86 and Arm)?
RISC-V is already the third force in compute with adoption increasing around the globe. Will over 10 billion RISC-V cores on the market today, RISC-V the momentum of RISC-V is continuing to grow quickly and nearly every semiconductor company has an active RISC-V implementation strategy.
For RISC-V to continue this strong momentum, the community needs to further build out the RISC-V software and development ecosystem. One exciting milestone from last year is that the Android Open Source Project (AOSP) was ported to RISC-V, which lays the foundation for RISC-V solutions to power a wide range of Android devices from phones to smartwatches, TVs, and beyond.
Additionally, it will be important for even higher performance RISC-V products to hit the market. SiFive is already working on solutions that will deliver the highest level of performance to meet that market demand.
RISC averse: Here's why Intel, AMD and Arm may have to up the ante to deal with Open hardware
Interview: SiFive is bullish about the chances of RISC-V, a new paradigm in open hardware
Bravo
If ARM was an arm, BRN would be its biceps💪!
Very interesting. Posted 4 hours ago on Lockheed Martin's website.
By using artificial intelligence and machine learning (AI/ML) to rapidly analyze data from space, air, and ground sensors, as well as connect dispersed teams through 5G communications, we are able to apply our joint all domain command and control (JADC2) solutions to provide near real time, actionable intelligence services that can assist first responders in making faster, more informed decisions.
www.lockheedmartin.com
By using artificial intelligence and machine learning (AI/ML) to rapidly analyze data from space, air, and ground sensors, as well as connect dispersed teams through 5G communications, we are able to apply our joint all domain command and control (JADC2) solutions to provide near real time, actionable intelligence services that can assist first responders in making faster, more informed decisions.
Firefighting intelligence
Discover our advanced wildfire firefighting capabilities, we are applying 21st Century Security technology to help first responders stay ahead of ready.
Hard to say other than that the research would have started over a year ago.
But it is also a fact that BrainChip has an office in
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-7% - Well it looks like Plato's 22 red flags have semaphored the danger of BRN hitting the rocks!
... but Shirley that would not have been the intention of the author?
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Schnitzel lover
Regular
See TA thread for simple solution on when to get more excited..
SERA2g
Founding Member
Whilst I do agree with you, I do find myself hoping you’re wrong as that’ll likely spell a very happy day for all holdersWhat new Patent ?
As many already know, the share market is a future crystal ball attempting to predict a price (range) maybe 6 or more months into the future, this obviously takes into consideration many factors, both technical and fundamental.
We, Brainchip, are shortly going to be entering a new phase in our commercial journey, as product/s are expected to be entering the marketplace, which in turn represents royalties and more worldwide exposure as the word "Akida" slowly starts to slide off companies tongues a little easier.
Our company doesn't issue fluff statements, so if some of you are expecting some announcement between now and next Tuesday morning, well I'd expect it to be pretty big, given the timing of such announcement, as @Earlyrelease suggested a few weeks ago, a potential EAP may have agreed to sign an IP License to coincide with our AGM, I personally don't think any announcement is coming, that's my gut feeling, but would be over the moon to be totally wrong.
Just my views on the current state of affairs, my love affair continues, we all hold a superb stock !
Morning Tech
Learning
Learning to the Top 🕵♂️
While BRN are getting short on the ASX,
TCS is looking for more candidates to join their Neuromorphic Computer Research Group.
www.linkedin.com
Learning 🏖
TCS is looking for more candidates to join their Neuromorphic Computer Research Group.
Arijit Mukherjee on LinkedIn: #ai #neuromorphiccomputing #edgecomputing #deeplearning…
Are you passionate about sustainable AI systems? Are you fascinated by recent AI advancements? Do you want to capture the efficiency of mammalian brains inside…
Learning 🏖
HopalongPetrovski
I'm Spartacus!
Hi Deena.
Last year I voted on paper ballot at the AGM before the meeting began.
I remember it only took a few moments and from memory was given the option when I registered with my HIN upon arrival.
You will need your HIN....Holder ID Number which you will find on your Chess holding statement for BRN or indeed on any recent Buy/sell transaction confirmation from your broker which acts as your ID and links you to your shareholding.
I don't know if paper voting will be an option this year but assume it will still be an available method?
If you have made up your mind it might be easier to vote beforehand with the info that should have gone to your email so you can spend your time chatting. I think they are expecting a crowd this year which is why they have expanded the size of the venue.
If you don't register or cast a particular vote your tally will be added to the chairs proxy and voted according to the boards intention.
Hoping to see you there.
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