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Cheers.In every presentation on this issue it has never been suggested that the design would need to be changed to take AKIDA smaller than 28nm.
A quick Google brought up this paper which appears to support the proposition that Scratch pad memory can at least move down to 7nm:
“A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS
Publisher: IEEE
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Mahmut E. Sinangil; Burak Erbagci; Rawan Naous; Kerem Akarvardar; Dar Sun; Win-San Khwa; Hung-Jen Liao; Yih Wang; Jonathan Chang
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Abstract:In this work, we present a compute-in-memory (CIM) macro built around a standard two-port compiler macro using foundry 8T bit-cell in 7-nm FinFET technology. The proposed design supports 1024 4 b $\times $ 4 b multiply-and-accumulate (MAC) computations simultaneously. The 4-bit input is represented by the number of read word-line (RWL) pulses, while the 4-bit weight is realized by charge sharing among binary-weighted computation caps. Each unit of computation cap is formed by the inherent cap of the sense amplifier (SA) inside the 4-bit Flash ADC, which saves area and minimizes kick-back effect. Access time is 5.5 ns with 0.8-V power supply at room temperature. The proposed design achieves energy efficiency of 351 TOPS/W and throughput of 372.4 GOPS. Implications of our design from neural network implementation and accuracy perspectives are also discussed”
I chose to Google 7nm as the former CEO Mr. Dinardo when asked by a shareholder in one of his webinars for the first time that I am aware said “Yes it can scale down from 28 to 14 to 7nm”. Since then Anil Mankar and Peter van der Made have also mentioned 4nm and 5nm respectively.
The intriguing part of Numen referencing 22nm apart from this is that Anil Mankar said in the Anastasia video that NASA was looking at 90nm. At 90nm semiconductors are more resilient to radiation and as I understand it semiconductors used in defence applications also seek similar resilience.
All I have at this stage.
My opinion only DYOR
FF
AKIDA BALLISTA
Is intriguing as you say though appears one thought last year was already to aim for 22nm and indicated AKD500 might be the implementation
Obviously mentioned 90nm as well which would tie in with NASA as you point out.
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Akida spiking neural processor could head to FDSOI
Startup BrainChip Inc. has a road-map of larger and smaller SoC exemplars of its Akida spiking neural networking processing architecture and could go to fully-depleted silicon on insulator (FDSOI).
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Anil Mankar, chief development officer, told eeNews Europe: “Chip production volume is just starting now. But you will see a lot of IP licensing going forward.” He added: “We are process agnostic.”
The near-term focus is supplying the Akida IP to 22nm although some customers may go back to 90nm process, Akida executives said.
Rob Telson, vice president of worldwide sales, said BrainChip is drawing up plans for smaller and larger versions of Akida under the names Akida500, Akida1500 and Akida2000. Some of these may well comply to a new generation of the Akida architecture – Akida 2.0 – due to arrive in 2022. It is thought Akida500 could be implemented in 22nm FDSOI manufacturing process, and serve as a demonstrator of the agnostic nature of the Akida architecture.