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In every presentation on this issue it has never been suggested that the design would need to be changed to take AKIDA smaller than 28nm.Further to my previous post I have a question for those more tech savvy.
Numem state that flash doesn't scale down (at this point from what I can see) lower than 28nm which is currently what Akida is.
Numem:
"These new memory types use a standard process for base layers and as such can scale down to lower geometries while Flash stops at 28nm."
Numem are using MRAM to assist this scale down process it appears.
Renesas recent article has said:
"We are working with a third party taping out a device in December on 22nm CMOS,” said Chittipeddi."
Is this tape out of the device Chittipeddi is mentioning going to be using MRAM or ReRAM and if so does this link back to another Renesas article from mid year I posted a few days back where:
"Renesas Develops Circuit Technologies for 22-nm Embedded STT-MRAM with Faster Read and Write Performance for MCUs in IoT Applications".
Wondering if to get Akida to the 22nm involves this change or not?
A quick Google brought up this paper which appears to support the proposition that Scratch pad memory can at least move down to 7nm:
“A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS
Publisher: IEEECite This
Mahmut E. Sinangil; Burak Erbagci; Rawan Naous; Kerem Akarvardar; Dar Sun; Win-San Khwa; Hung-Jen Liao; Yih Wang; Jonathan Chang
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Abstract:In this work, we present a compute-in-memory (CIM) macro built around a standard two-port compiler macro using foundry 8T bit-cell in 7-nm FinFET technology. The proposed design supports 1024 4 b $\times $ 4 b multiply-and-accumulate (MAC) computations simultaneously. The 4-bit input is represented by the number of read word-line (RWL) pulses, while the 4-bit weight is realized by charge sharing among binary-weighted computation caps. Each unit of computation cap is formed by the inherent cap of the sense amplifier (SA) inside the 4-bit Flash ADC, which saves area and minimizes kick-back effect. Access time is 5.5 ns with 0.8-V power supply at room temperature. The proposed design achieves energy efficiency of 351 TOPS/W and throughput of 372.4 GOPS. Implications of our design from neural network implementation and accuracy perspectives are also discussed”
I chose to Google 7nm as the former CEO Mr. Dinardo when asked by a shareholder in one of his webinars for the first time that I am aware said “Yes it can scale down from 28 to 14 to 7nm”. Since then Anil Mankar and Peter van der Made have also mentioned 4nm and 5nm respectively.
The intriguing part of Numen referencing 22nm apart from this is that Anil Mankar said in the Anastasia video that NASA was looking at 90nm. At 90nm semiconductors are more resilient to radiation and as I understand it semiconductors used in defence applications also seek similar resilience.
All I have at this stage.
My opinion only DYOR
FF
AKIDA BALLISTA