Synopsys are mainly about the provision of circuit design IP tools, rather than the actual SoC.
Their Products page talks of IP solutions:
https://www.synopsys.com/dw/ipdir.php?ds=arc-npx6#
DesignWare® ARC® NPX Neural Processor IP family provides a high-performance, power- and area-efficient IP solution for a range of applications requiring AI enabled SoCs. The ARC NPX6 NPU IP is designed for deep learning algorithm coverage including both computer vision tasks such as object detection, image quality improvement, and scene segmentation, and for broader AI applications such as audio and natural language processing.
https://www.synopsys.com/silicon-design.html
The Silicon Powering the Software
Advanced silicon chips power the amazing software we rely on every day. They are the foundation for everything from smartphones and wearables to self-driving cars and machines that learn. Synopsys is the leader in solutions for designing and verifying complex chips and for designing the advanced processes and models required to manufacture those chips.They are seemingly still dealing with CNNs, and do not appear to be involved with spiking NNs.
https://www.synopsys.com/dw/ipdir.php?ds=arc-npx6
DesignWare ARC NPX6 NPU Family for AI / Neural Processing
DesignWare® ARC® NPX Neural Processor IP family provides a high-performance, power- and area-efficient IP solution for a range of applications requiring AI enabled SoCs. The ARC NPX6 NPU IP is designed for deep learning algorithm coverage including both computer vision tasks such as object detection, image quality improvement, and scene segmentation, and for broader AI applications such as audio and natural language processing.
The NPX6 NPU family offers multiple products to choose from to meet your specific application requirements. The architecture is based on individual cores that can scale from 4K MACs to 96K MACs for a single AI engine performance of over 250 TOPS and over 440 TOPS with sparsity. The NPX6 NPU IP includes hardware and software support for multi-NPU clusters of up to 8 NPUs achieving 3500 TOPS with sparsity. Advanced bandwidth features in hardware and software, and a memory hierarchy (including L1 memory in each core and a high-performance, low-latency interconnect to access a shared L2 memory) make scaling to a high MAC count possible. An optional tensor floating point unit is available for applications benefiting from BF16 or FP16 inside the neural network.
To speed application software development, the ARC NPX6 NPU Processor IP is supported by the MetaWare MX Development Toolkit, a comprehensive software programming environment that includes a neural network Software Development Kit (NN SDK) and support for virtual models. The NN SDK automatically converts neural networks trained using popular frameworks, like Pytorch, Tensorflow, or ONNX into optimized executable code for the NPX hardware.
The NPX6 NPU Processor IP can be used to create a range of products – from a few TOPS to 1000s of TOPS – that can be programmed with a single toolchain.
Highlights
- Scalable real-time AI / neural processor IP with up to 3,500 TOPS performance
- Supports CNNs, RNNs/LSTMs, transformers, recommender networks, etc.
- Industry leading power efficiency (up to 30 TOPS/W)
- 1-24 cores of an enhanced 4K MAC/core convolution accelerator
- Tensor accelerator providing flexible activation and support of Tensor Operator Set Architecture (TOSA)
- Software Development Kit
- Automatic mixed mode quantization tools
- Bandwidth reduction through architecture and software tool features
- Latency reduction through parallel processing of individual layers
- Seamless integration with DesignWare ARC VPX vector DSPs
- High productivity MetaWare MX Development Toolkit supports Tensorflow and Pytorch frameworks and ONNX exchange format
US10846591B2 Configurable and programmable multi-core architecture with a specialized instruction set for embedded application based on neural networks
A programmable architecture specialized for convolutional neural networks (CNNs) processing such that different applications of CNNs may be supported by the presently disclosed method and apparatus by reprogramming the processing elements therein. The architecture may include an optimized architecture that provides a low-area or footprint and low-power solution desired for embedded applications while still providing the computational capabilities required for CNN applications that may be computationally intensive, requiring a huge number of convolution operations per second to process inputs such as video streams in real time.
Interestingly, the claims refer to "A CNN architecture ..." rather than "A CNN processor ..." or similar.
However, given Synopsys' use of the BrainChip Accelerator photo, one possible scenario is that BrainChip used some earlier version of their design tools to plot the layout of the Accelerator onto a FPGA all those years ago, because not even Anil does IC layouts by hand (late edition - "except maybe the fine tuning").
https://brainchip.com/brainchip-introduces-worlds-first-commercial-hardware-acceleration-of-neuromorphic-computing-brainchip-120917/#:~:text=As the first commercial implementation of a hardware-accelerated,branch of artificial intelligence that simulates neuron functions.
As the first commercial implementation of a hardware-accelerated spiking neural network system, BrainChip Accelerator is a significant milestone in the development of neuromorphic computing, a branch of artificial intelligence that simulates neuron functions. The processing is done by six BrainChip Accelerator cores in a Xilinx Kintex Ultrascale field-programmable gate array (FPGA).
Last edited:
