Hi JD,I find this very intriguing and did a little bit of research. Some dots can be joined between Western Sydney University and BrainChip. There was a 4th International Workshop on Event-Based Vision in June. The usual suspects were from respective companies, with presentations by André van Schaik representing Western Sydney University and Nandan Nayampally from BrainChip. Prophesee had a presence there as well.
I did run across a 3-year-old LinkedIn post with André congratulating Tony Lewis on an award that Western Sydney University presented, so the two are not strangers.
I uncovered a research paper published in March 2018, for which André van Schaik was a co-author. The paper describes an "FPGA-based Massively Parallel Neuromorphic Cortex Simulator," with the start of the abstract as follows:
The paper describes using Intel's Altera Stratix V FPGA for the simulation. This is a tool used in various applications, including as a tool for FPGA digital logic design. A PRWire article about this new neuromorphic supercomputer points out the advantages of this approach, specifically under the "Reconfigurable" and "Commercial Availability" sections.
Another thing that we know is that BrainChip's Akida is FPGA-based, as noted by one of their press releases touting an article from "The Next Platform."
Is Western Sydney University using the Akida IP in its neuromorphic supercomputer? I don't know. However, the circumstantial evidence leads me to believe it is possible.
It is true that the configuration of Akida is field programmable as it has a programmable communication matrix interconnecting the nodes, but in my mind Akida is not FPGA-based. The initial proof-of-concept circuit was built in FPGA (Xylink, or was that BrainChip Accelerator?), but the commercial Akida 1 chip would be better described as an ASIC.
FPGA is field programmable gate array, a prefabricated chip with lots of different logic gates which the user can selectively interconnect to make a number of different circuits with for different purposes*. As a result there are many redundant logic gates and the layout is far from optimal. In the case of Akida, it would have been for fewer nodes than Akida 1, and it's performance would be inferior to an ASIC version of Akida. FPGAs are commonly used as test chips.
ASIC (application specific integrated circuit) is a purpose-built chip with only the necessary gates and in which the layout would be optimized by the circuit designer.
From the article you cited:
When we last spoke with BrainChip in 2018, the company was on the verge of rolling out its FPGA-based spiking neural network (SNN) accelerator, known as Akida (Greek for spike). At that point, the plan was to get its hardened SoC into the market by 2019.
The reference to "FPGA-based" was to the proof-of-concept chip. The "hardened SoC" is the ASIC. The use of the adjective "hardened" can be thought of as implying the FPGA design is malleable.
The presence of Zurich Uni as a partner would be put on the scales on the side of analog MemRistor SNNs, but this is not conclusive.
* On reflection, I had to put in the bit about different purposes to better distinguish Akida from my definition of a FPGA. Akida is a single purpose SNN with field programmable nodes and NPUs.
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