BRN Discussion Ongoing

[Sirod69]

Valeo
21 Min. •

"From an industrial point of view, AI is a real booster for our competitiveness."

At AI for Industry, organized by Artefact at the Palais Brongniart in Paris, Romain Bruniaux, Valeo Industrial VP, highlighted the potential of artificial intelligence applied to production and logistics. In particular, he spoke of the benefits of predictive maintenance, quality improvement and energy savings. Valeo has already observed up to 15% gains in a pilot plant.

AI for Industry brings together players in the field of artificial intelligence and industry, startups and institutional players, to highlight the use cases and ways in which AI can contribute to the success of the Industry.

 

[Reuben]

Md, there will be more than 1480.. some people have it in a few accounts. Our super itself is over 100k....

There are only 1480 people in the world with 100k of shares in this company ? thankyou lord in allowing me to be one of those. that leaves how many people ? kudos to the others too that jumped on board below 100k. but I bet the top 20 will happy soon now is a good time to be "stardust" who happens to be top 20. who amongst us is stardust?

 

[yogi]

Hope the health issue gets resolved soon mate.

Thanks Mate much appriciated

 

[IloveLamp]

Join Us at AI Live | Renesas Electronics

info.renesas.com

 

[IloveLamp]

Redirecting

 

[Mt09]

Could Akida be used here?​

I do know we have a partnership with Cadence.
Main parts highlighted in orange!

​

Cadence Accelerates On-Device and Edge AI Performance and Efficiency with New Neo NPU IP and NeuroWeave SDK for Silicon Design​

SAN JOSE, Calif.— September 14, 2023 -- Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its next-generation AI IP and software tools to address the escalating demand for on-device and edge AI processing. The new highly scalable Cadence® Neo™ Neural Processing Units (NPUs) deliver a wide range of AI performance in a low-energy footprint, bringing new levels of performance and efficiency to AI SoCs. Delivering up to 80 TOPS performance in a single core, the Neo NPUs support both classic and new generative AI models and can offload AI/ML execution from any host processor—including application processors, general-purpose microcontrollers and DSPs—with a simple and scalable AMBA® AXI interconnect. Complementing the AI hardware, the new NeuroWeave™ Software Development Kit (SDK) provides developers with a “one-tool” AI software solution across Cadence AI and Tensilica® IP products for no-code AI development.
“While most of the recent attention on AI has been cloud-focused, there are an incredible range of new possibilities that both classic and generative AI can enable on the edge and within devices,” said Bob O’Donnell, president and chief analyst at TECHnalysis Research. “From consumer to mobile and automotive to enterprise, we’re embarking on a new era of naturally intuitive intelligent devices. For these to come to fruition, both chip designers and device makers need a flexible, scalable combination of hardware and software solutions that allow them to bring the magic of AI to a wide range of power requirements and compute performance, all while leveraging familiar tools. New chip architectures that are optimized to accelerate ML models and software tools with seamless links to popular AI development frameworks are going to be incredibly important parts of this process.”
The flexible Neo NPUs are well suited for ultra-power-sensitive devices as well as high-performance systems with a configurable architecture, enabling SoC architects to integrate an optimal AI inferencing solution in a broad range of products, including intelligent sensors, IoT and mobile devices, cameras, hearables/wearables, PCs, AR/VR headsets and advanced driver-assistance systems (ADAS). New hardware and performance enhancements and key features/capabilities include:

• Scalability: Single-core solution is scalable from 8 GOPS to 80 TOPS, with further extension to hundreds of TOPS with multicore
• Broad configuration range: supports 256 to 32K MACs per cycle, allowing SoC architects to optimize their embedded AI solution to meet power, performance and area (PPA) tradeoffs
• Integrated support for a myriad of network topologies and operators: enables efficient offloading of inferencing tasks from any host processor—including DSPs, general-purpose microcontrollers or application processors—significantly improving system performance and power
• Ease of deployment: shortens the time to market to meet rapidly evolving next-generation vision, audio, radar, natural language processing (NLP) and generative AI pipelines
• Flexibility: Support for Int4, Int8, Int16, and FP16 data types across a wide set of operations that form the basis of CNN, RNN and transformer-based networks allows flexibility in neural network performance and accuracy tradeoffs
• High performance and efficiency: Up to 20X higher performance than the first-generation Cadence AI IP, with 2-5X the inferences per second per area (IPS/mm2) and 5-10X the inferences per second per Watt (IPS/W)

Since software is a critical part of any AI solution, Cadence also upgraded its common software toolchain with the introduction of the NeuroWeave SDK. Providing customers with a uniform, scalable and configurable software stack across Tensilica DSPs, controllers and Neo NPUs to address all target applications, the NeuroWeave SDK streamlines product development and enables an easy migration as design requirements evolve. It supports many industry-standard domain-specific ML frameworks, including TensorFlow, ONNX, PyTorch, Caffe2, TensorFlow Lite, MXNet, JAX and others for automated end-to-end code generation; Android Neural Network Compiler; TF Lite Delegates for real-time execution; and TensorFlow Lite Micro for microcontroller-class devices.

“For two decades and with more than 60 billion processors shipped, industry-leading SoC customers have relied on Cadence processor IP for their edge and on-device SoCs. Our Neo NPUs capitalize on this expertise, delivering a leap forward in AI processing and performance,” said David Glasco, vice president of research and development for Tensilica IP at Cadence. “In today’s rapidly evolving landscape, it’s critical that our customers are able to design and deliver AI solutions based on their unique requirements and KPIs without concern about whether future neural networks are supported. Toward this end, we’ve made significant investments in our new AI hardware platform and software toolchain to enable AI at every performance, power and cost point and to drive the rapid deployment of AI-enabled systems.”

“At Labforge, we use a cluster of Cadence Tensilica DSPs in our Bottlenose smart camera product line to enable best-in-class AI processing for power-sensitive edge applications,” said Yassir Rizwan, CEO of Labforge, Inc. “Cadence’s AI software is an integral part of our embedded low power AI solution, and we’re looking forward to leveraging the new capabilities and higher performance offered by Cadence’s new NeuroWeave SDK. With an end-to-end compiler toolchain flow, we can better solve challenging AI problems in automation and robotics—accelerating our time to market to capitalize on generative AI-based application demand and opening new market streams that may not have been possible otherwise.”

The Neo NPUs and the NeuroWeave SDK support Cadence’s Intelligent System Design™ strategy by enabling pervasive intelligence through SoC design excellence.

Availability

The Neo NPUs and the NeuroWeave SDK are expected to be in general availability beginning in December 2023. Early engagements have already started for lead customers. For more information, please visit www.cadence.com/go/NPU.

About Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

Partnership with Cadence? Where’d ya pull that from? (Please don’t say google bard).

 

[wilzy123]

Could Akida be used here?​

I do know we have a partnership with Cadence.
Main parts highlighted in orange!

​

Cadence Accelerates On-Device and Edge AI Performance and Efficiency with New Neo NPU IP and NeuroWeave SDK for Silicon Design​

SAN JOSE, Calif.— September 14, 2023 -- Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its next-generation AI IP and software tools to address the escalating demand for on-device and edge AI processing. The new highly scalable Cadence® Neo™ Neural Processing Units (NPUs) deliver a wide range of AI performance in a low-energy footprint, bringing new levels of performance and efficiency to AI SoCs. Delivering up to 80 TOPS performance in a single core, the Neo NPUs support both classic and new generative AI models and can offload AI/ML execution from any host processor—including application processors, general-purpose microcontrollers and DSPs—with a simple and scalable AMBA® AXI interconnect. Complementing the AI hardware, the new NeuroWeave™ Software Development Kit (SDK) provides developers with a “one-tool” AI software solution across Cadence AI and Tensilica® IP products for no-code AI development.
“While most of the recent attention on AI has been cloud-focused, there are an incredible range of new possibilities that both classic and generative AI can enable on the edge and within devices,” said Bob O’Donnell, president and chief analyst at TECHnalysis Research. “From consumer to mobile and automotive to enterprise, we’re embarking on a new era of naturally intuitive intelligent devices. For these to come to fruition, both chip designers and device makers need a flexible, scalable combination of hardware and software solutions that allow them to bring the magic of AI to a wide range of power requirements and compute performance, all while leveraging familiar tools. New chip architectures that are optimized to accelerate ML models and software tools with seamless links to popular AI development frameworks are going to be incredibly important parts of this process.”
The flexible Neo NPUs are well suited for ultra-power-sensitive devices as well as high-performance systems with a configurable architecture, enabling SoC architects to integrate an optimal AI inferencing solution in a broad range of products, including intelligent sensors, IoT and mobile devices, cameras, hearables/wearables, PCs, AR/VR headsets and advanced driver-assistance systems (ADAS). New hardware and performance enhancements and key features/capabilities include:

• Scalability: Single-core solution is scalable from 8 GOPS to 80 TOPS, with further extension to hundreds of TOPS with multicore
• Broad configuration range: supports 256 to 32K MACs per cycle, allowing SoC architects to optimize their embedded AI solution to meet power, performance and area (PPA) tradeoffs
• Integrated support for a myriad of network topologies and operators: enables efficient offloading of inferencing tasks from any host processor—including DSPs, general-purpose microcontrollers or application processors—significantly improving system performance and power
• Ease of deployment: shortens the time to market to meet rapidly evolving next-generation vision, audio, radar, natural language processing (NLP) and generative AI pipelines
• Flexibility: Support for Int4, Int8, Int16, and FP16 data types across a wide set of operations that form the basis of CNN, RNN and transformer-based networks allows flexibility in neural network performance and accuracy tradeoffs
• High performance and efficiency: Up to 20X higher performance than the first-generation Cadence AI IP, with 2-5X the inferences per second per area (IPS/mm2) and 5-10X the inferences per second per Watt (IPS/W)

Since software is a critical part of any AI solution, Cadence also upgraded its common software toolchain with the introduction of the NeuroWeave SDK. Providing customers with a uniform, scalable and configurable software stack across Tensilica DSPs, controllers and Neo NPUs to address all target applications, the NeuroWeave SDK streamlines product development and enables an easy migration as design requirements evolve. It supports many industry-standard domain-specific ML frameworks, including TensorFlow, ONNX, PyTorch, Caffe2, TensorFlow Lite, MXNet, JAX and others for automated end-to-end code generation; Android Neural Network Compiler; TF Lite Delegates for real-time execution; and TensorFlow Lite Micro for microcontroller-class devices.

“For two decades and with more than 60 billion processors shipped, industry-leading SoC customers have relied on Cadence processor IP for their edge and on-device SoCs. Our Neo NPUs capitalize on this expertise, delivering a leap forward in AI processing and performance,” said David Glasco, vice president of research and development for Tensilica IP at Cadence. “In today’s rapidly evolving landscape, it’s critical that our customers are able to design and deliver AI solutions based on their unique requirements and KPIs without concern about whether future neural networks are supported. Toward this end, we’ve made significant investments in our new AI hardware platform and software toolchain to enable AI at every performance, power and cost point and to drive the rapid deployment of AI-enabled systems.”

“At Labforge, we use a cluster of Cadence Tensilica DSPs in our Bottlenose smart camera product line to enable best-in-class AI processing for power-sensitive edge applications,” said Yassir Rizwan, CEO of Labforge, Inc. “Cadence’s AI software is an integral part of our embedded low power AI solution, and we’re looking forward to leveraging the new capabilities and higher performance offered by Cadence’s new NeuroWeave SDK. With an end-to-end compiler toolchain flow, we can better solve challenging AI problems in automation and robotics—accelerating our time to market to capitalize on generative AI-based application demand and opening new market streams that may not have been possible otherwise.”

The Neo NPUs and the NeuroWeave SDK support Cadence’s Intelligent System Design™ strategy by enabling pervasive intelligence through SoC design excellence.

Availability

The Neo NPUs and the NeuroWeave SDK are expected to be in general availability beginning in December 2023. Early engagements have already started for lead customers. For more information, please visit www.cadence.com/go/NPU.

About Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

This is low value bait and misleading. Yet another untrustworthy forum character.

 

[Cartagena]

Hi Cartagena,

I don't recall a partnership with Cadence. Do you have a reference?

Cadence have a clunky CNN circuit with ALU 125:

US11687831B1 Method, product, and apparatus for a multidimensional processing array for hardware acceleration of convolutional neural network inference 20200630
View attachment 44700

Hi Diogenese thanks for your excellent explanation of the circuit which Cadence is using and for correcting me. I am not 100% on the partnership so I've edited my post however some time ago I thought BrainChip and Cadence were working together as I definitely read something online and I'm trying to remember where. Considering I posted that in the late hours of the night, I must have been too tired and maybe over enthusiastic. I will try and find where it was however I do appreciate your input which was mature, respectful and not an attack on my post unlike others here.

 

[Cartagena]

This is low value bait and misleading. Yet another untrustworthy forum character.

There's no need to attack my post in that manner when I unintentionally made an error, we're all human.
Yes thought there was some connection (innocently) but I have since removed my post. I suggest you remove your post also, which I find immature and unacceptable.

 

[IloveLamp]

 

[IloveLamp]

Cruise “just days away” from approval to mass-produce Origin robotaxi without steering wheels

The approval from NHTSA could come any day, Vogt said.

www.theverge.com

 

[IloveLamp]

 

[HappyChippy]

Pull apart the camera and send us a photo of the internal

Would be lying if I said that thought didn’t cross my mind.

 

[Fenris78]

There's no need to attack my post in that manner when I unintentionally made an error, we're all human.
Yes thought there was some connection (innocently) but I have since removed my post. I suggest you remove your post also, which I find immature and unacceptable.

Every one of Wilzy123 posts is inflammatory and unacceptable... I would have hoped that he'd be removed from this forum by Zeebot by now (people are moderated for much less)? No different to BS from hotcrapper... which is why most of us came here with good intentions. He adds zero value.. other than to antagonize others here. Going on my ignore list Wilzy.

 

[Fenris78]

Loving this news! AI and Cortex M85, as well as Cloudless Cortex-M architecture... stars are definitely seem to be aligning.

 

[Bravo]

Softbank Aims to Work With Arm on AI Revolution, CFO Says
LI AILIN
DATE: 11 HOURS AGO

HIROFUMI TAKEUCHI, Nikkei staff writerSeptember 15, 2023 03:27 JST

NEW YORK -- U.K. chip designer Arm is SoftBank Group's most important unit and key to its artificial intelligence strategy, the Japanese investor's finance chief said Thursday after Arm's Nasdaq debut.

Speaking to reporters outside the Nasdaq market site here, Yoshimitsu Goto said Arm is "in the leading position of the artificial intelligence revolution that we have been strategically advancing."

Softbank Aims to Work With Arm on AI Revolution, CFO Says

(Yicai) Sept. 15 -- Arm Holdings, a chip designer owned by Softbank Group, soared in value after its listing on the Nasdaq stock market yesterday, and Softbank’s chief financial officer told Yicai that Arm is a key part of the Japanese firm’s artificial intelligence ambitions.
As the world’s largest public offering so far this year, Arm raised USD4.9 billion at an initial offer price of USD51 per share, with the share price surging 25 percent to USD63.59 on its first day of trading, giving it a market capitalization of USD65 billion.

Softbank CFO Yoshimitsu Goto attended Arm’s bell-ringing ceremony yesterday.

In an interview with Yicai outside the exchange, Goto said that he hopes Softbank stays at the forefront of advancing the AI revolution and that Arm can help achieve the goal.

The two companies will work together to explore various AI applications and businesses, Goto noted. AI has the power to redefine the world and every industry, and Softbank is committed to realizing this vision, he added.

Founded in 1990 and based in Cambridge in the United Kingdom, Arm went public in London and on Nasdaq in 1998, but Softbank acquired it in 2016 for USD32 billion and took the company private. Softbank tried unsuccessfully to sell Arm to US chip giant Nvidia in 2020 and then started to promote its re-listing.

Arm’s cornerstone investors include some of the world’s leading tech and chip firms such as Apple, Google’s parent company Alphabet, Nvidia, Intel, and Taiwan Semiconductor Manufacturing, who bought up to USD735 million worth of shares at the initial offer price, according to Arm’s listing prospectus.
Arm has seen mediocre financial performance recently, with net profit in the quarter ended June 30 falling 53 percent from a year earlier to USD105 million and revenue down 2.5 percent at USD675 million.

Softbank Aims to Work With Arm on AI Revolution, CFO Says

www.yicaiglobal.com

 

[Perhaps]

Hi Diogenese thanks for your excellent explanation of the circuit which Cadence is using and for correcting me. I am not 100% on the partnership so I've edited my post however some time ago I thought BrainChip and Cadence were working together as I definitely read something online and I'm trying to remember where. Considering I posted that in the late hours of the night, I must have been too tired and maybe over enthusiastic. I will try and find where it was however I do appreciate your input which was mature, respectful and not an attack on my post unlike others here.

Just to clear things up, maybe you mixed some informations from the past. There is a very slight connection to Cadence/Tensilica, but no partnership.
"MegaChips has been an authorized Tensilica design center since 2008 and has completed many designs using Tensilica processors."

https://www.fierceelectronics.com/iot-wireless/megachips-utilizes-cadence-tensilica-xtensa-processor-ultra-low-power-internet-things

 

[Bravo]

Hi Diogenese thanks for your excellent explanation of the circuit which Cadence is using and for correcting me. I am not 100% on the partnership so I've edited my post however some time ago I thought BrainChip and Cadence were working together as I definitely read something online and I'm trying to remember where. Considering I posted that in the late hours of the night, I must have been too tired and maybe over enthusiastic. I will try and find where it was however I do appreciate your input which was mature, respectful and not an attack on my post unlike others here.

Hi Cartagena,

There was the job ad for an IP Verification Engineer in Hyderabad India stating "The role would include functional verification of the IP solution of Siemens/Synopsys/Cadence".

 

[Dougie54]

I’m needing a cold shower this morning after reading all these promising stories posted over the last 48 hours.this is getting very EXCITING.!!! I better put something on under my Kilt.

 

[Cartagena]

Hi Cartagena,

There was the job ad for an IP Verification Engineer in Hyderabad India stating "The role would include functional verification of the IP solution of Siemens/Synopsys/Cadence".

Correct, thanks Bravo. That's what I was referring to when I made the connection. Yes the job ad on LinkedIn. I knew I saw it somewhere!