Ella and I are 99.9° % sure that Untether have their own in-house design:
US2021091794A1 COMPUTATIONAL MEMORY WITH ZERO DISABLE AND ERROR DETECTION
A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.
Technology — Untether AI
https://www.untether.ai/technology
runAI200™ Represents a new breed of computing
At Untether AI, we re-wrote the rules for compute architectures. Designed from the ground up for AI inference workloads, the runAI200® architecture provides best-in-class performance for running neural networks; CNNs, RNNs, TCNs, Attention, Transformer, Unets, and DLRM.
At the heart of the unique at-memory compute architecture is a memory bank: 385KBs of SRAM with a 2D array of 512 processing elements. With 511 banks per chip, each device offers 200MB of memory, enough to run many networks in a single chip. And with the multi-chip partitioning capability of the imAIgine® Software Development Kit, larger networks can be split apart to run on multiple devices, or even across multiple tsunAImi® accelerator cards.
