SebThatGermanChap
Regular
I highly doubt you making a fool of yourself is possible.Thanks Rocket,
That will help prevent me making a complete fool of myself.
I highly doubt you making a fool of yourself is possible.Thanks Rocket,
That will help prevent me making a complete fool of myself.
Your safe to go ahead as I can’t find itThanks Rocket,
That will help prevent me making a complete fool of myself.
Maybe it was thisThanks Rocket,
That will help prevent me making a complete fool of myself.
Not sure that marketing will work in USA as they call them Fries!Do you think they could sell more chips if they gave a free fish with every order.
This is a green selling point. They would donate ‘x’ number of fingerling to environmental groups repopulating rivers with native fish based on the size of the chip order.
FF
AKIDA BALLISTA
Awesome MD ...about time!!Ok firstly Good morning fellow brners its a glorious morning!
Right here it is ! drum roll In this pic i know we have an "ARM" AND "MERCEDES"!
And i NOW finally have my 1st proud addition -
I don't think i will need my h.i.n for entrance to the Agm will i ???
View attachment 6914
congrats, mercedes cars are amazing....Ok firstly Good morning fellow brners its a glorious morning!
Right here it is ! drum roll In this pic i know we have an "ARM" AND "MERCEDES"!
And i NOW finally have my 1st proud addition -
I don't think i will need my h.i.n for entrance to the Agm will i ???
View attachment 6914
Ok firstly Good morning fellow brners its a glorious morning!
Right here it is ! drum roll In this pic i know we have an "ARM" AND "MERCEDES"!
And i NOW finally have my 1st proud addition -
I don't think i will need my h.i.n for entrance to the Agm will i ???
View attachment 6914
Ok firstly Good morning fellow brners its a glorious morning! Right here it is ! drum roll In this pic i know we have an "ARM" AND "MERCEDES"! And i NOW finally have my 1st proud addition - I don't think i will need my h.i.n for entrance to the Agm will i ???View attachment 6914
Patent History
Publication number: 20220147797
Type: Application
Filed: Jan 25, 2022
Publication Date: May 12, 2022
Applicant: BrainChip, Inc. (Laguna Hills, CA)
Inventors: Douglas MCLELLAND (Laguna Hills, CA), Kristofor D. CARLSON (Laguna Hills, CA), Harshil K. PATEL (Laguna Hills, CA), Anup A. VANARSE (Laguna Hills, CA), Milind JOSHI (Perth)
Application Number: 17/583,640
Is this a sign of the changing of the guard/s...I don't think so...BUT...check out the 3 Perth based "Dream Team" getting to put their inventors hats on....I'm personally really pleased for Anup and Harshil with whom I've had the pleasure to talk with in person.
This was obviously only published 5/6 days ago, so if this has already been posted, excuse me, as I can't keep up with all the brilliant articles being posted, I'm a slow reader
Good morning from Australia's Brainchip HQ.....Perth![]()
United States Patent Application | 20220147797 |
Kind Code | A1 |
MCLELLAND; Douglas ; et al. | May 12, 2022 |
Inventors: | MCLELLAND; Douglas; (Laguna Hills, CA) ; CARLSON; Kristofor D.; (Laguna Hills, CA) ; PATEL; Harshil K.; (Laguna Hills, CA) ; VANARSE; Anup A.; (Laguna Hills, CA) ; JOSHI; Milind; (Perth, AU) |
Applicant: |
| ||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
Assignee: | BrainChip, Inc. Laguna Hills CA | ||||||||||
Family ID: | 1000006135263 | ||||||||||
Appl. No.: | 17/583640 | ||||||||||
Filed: | January 25, 2022 |
United States Patent Application | 20220138543 |
Kind Code | A1 |
VAN DER MADE; Peter AJ ; et al. | May 5, 2022 |
Inventors: | VAN DER MADE; Peter AJ; (Nedlands, AU) ; MANKAR; Anil S.; (Laguna Hills, CA) ; CARLSON; Kristofor D.; (Laguna Hills, CA) ; CHENG; Marco; (Laguna Hills, CA) |
Applicant: |
| ||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
Assignee: | BrainChip, Inc. Laguna Hills CA | ||||||||||
Appl. No.: | 17/576103 | ||||||||||
Filed: | January 14, 2022 |
Hi @Diogenese
When I first read about Quadric I thought about the fact that there is yet to be a single agreed definition of the Edge and where it actually is in a system.
It struck me then that AKIDA at the far Edge with its mum saying be careful you should not be that close and Quadric at a safer place back from the Edge with its mum saying AKIDA come back and stand with your cousin Quadric was why MegaChips have both solutions.
The following which I extracted from the group of words you posted seems to fit this scenario with AKIDA making all the sensors intelligent and a Quadric processing the AKIDA made relevant data:
“Autonomous vehicles have been implemented with advanced sensor suites that provide a fusion of sensor data that enable route or path planning for autonomous vehicles. But, modern GPUs are not constructed for handling these additional high computation tasks.
[0006] At best, to enable a GPU or similar processing circuitry to handle additional sensor processing needs including path planning, sensor fusion, and the like, additional and/or disparate circuitry may be assembled to a traditional GPU”
If you generally agree then I can allow the rest of the technological differences to happily go over my head?
My opinion only DYOR
FF
AKIDA BALLISTA
United States Patent Application 20220147797 Kind Code A1 MCLELLAND; Douglas ; et al. May 12, 2022
EVENT-BASED EXTRACTION OF FEATURES IN A CONVOLUTIONAL SPIKING NEURAL NETWORK
Abstract
A system is described that comprises a memory for storing data representative of at least one kernel, a plurality of spiking neuron circuits, and an input module for receiving spikes related to digital data. Each spike is relevant to a spiking neuron circuit and each spike has an associated spatial coordinate corresponding to a location in an input spike array. The system also comprises a transformation module configured to transform a kernel to produce a transformed kernel having an increased resolution relative to the kernel, and/or transform the input spike array to produce a transformed input spike array having an increased resolution relative to the input spike array. The system also comprises a packet collection module configured to collect spikes until a predetermined number of spikes relevant to the input spike array have been collected in a packet in memory, and to organize the collected relevant spikes in the packet based on the spatial coordinates of the spikes, and a convolutional neural processor configured to perform event-based convolution using memory and at least one of the transformed input spike array and the transformed kernel.
Inventors: MCLELLAND; Douglas; (Laguna Hills, CA) ; CARLSON; Kristofor D.; (Laguna Hills, CA) ; PATEL; Harshil K.; (Laguna Hills, CA) ; VANARSE; Anup A.; (Laguna Hills, CA) ; JOSHI; Milind; (Perth, AU)
Applicant:
Name City State Country Type
BrainChip, Inc.
Laguna Hills
CA
US Assignee: BrainChip, Inc.
Laguna Hills
CA Family ID: 1000006135263 Appl. No.: 17/583640 Filed: January 25, 2022
and
United States Patent Application 20220138543 Kind Code A1 VAN DER MADE; Peter AJ ; et al. May 5, 2022
EVENT-BASED CLASSIFICATION OF FEATURES IN A RECONFIGURABLE AND TEMPORALLY CODED CONVOLUTIONAL SPIKING NEURAL NETWORK
Abstract
Embodiments of the present invention provides a system and method of learning and classifying features to identify objects in images using a temporally coded deep spiking neural network, a classifying method by using a reconfigurable spiking neural network device or software comprising configuration logic, a plurality of reconfigurable spiking neurons and a second plurality of synapses. The spiking neural network device or software further comprises a plurality of user-selectable convolution and pooling engines. Each fully connected and convolution engine is capable of learning features, thus producing a plurality of feature map layers corresponding to a plurality of regions respectively, each of the convolution engines being used for obtaining a response of a neuron in the corresponding region. The neurons are modeled as Integrate and Fire neurons with a non-linear time constant, forming individual integrating threshold units with a spike output, eliminating the need for multiplication and addition of floating-point numbers.
Inventors: VAN DER MADE; Peter AJ; (Nedlands, AU) ; MANKAR; Anil S.; (Laguna Hills, CA) ; CARLSON; Kristofor D.; (Laguna Hills, CA) ; CHENG; Marco; (Laguna Hills, CA)
Applicant:
Name City State Country Type
BrainChip, Inc.
Laguna Hills
CA
US Assignee: BrainChip, Inc.
Laguna Hills
CA Appl. No.: 17/576103 Filed: January 14, 2022
Both filed within a week and half of each other.
The boys have been very busy.
Hi @Rocket577 , @Fact Finder ,
here is an extract from an article posted by @Fullmoonfever discussing potential interworking of Akida and Quadric.
#10,930
What people have found is that the existing processors from ARM or RISC-V do not address the power performance requirements of the AI industry. There are some low-end cases that can be handled with software on these embedded processors. In general, people are looking for either accelerators to pair with those processors, or completely new processors, that would replace the embedded processor and AI into a much higher performance functionality.
In this case, MegaChips’ partner, BrainChip, is an example of an accelerator that would be combined with the existing embedded processors. In the case of its other IP partner, Quadric, they could be either used as an accelerator, or even supersede the need for an embedded processor.
Determining success
Now, there have been attempts from some others, but not with much success. How can MegaChips determine its path?
megachips-logo-200x40-1.png
According to Fairbairn, we see this as an emerging market. Those who tried to enter with volume production capabilities up until now were too early to the party. It’s only now that people are reaching the point where they are in need of volume production opportunities.
There have been many obstacles to the adoption of AI, and adoption has been relatively slow. MegaChips realized that, and partnered with a couple of IP vendors that already had some significant traction, but also needed the muscle of pairing up with a silicon vendor to actually provide a complete solution to the customer.
By combining forces and offering that complete solution, and with the ability to help the customer determine which solution is best to integrate into a single chip or module, we can help overcome those things. We are investing heavily in internal capability to address this very need. We believe that we’re hitting the market at an ideal time to be involved with some designs that can go into production in the near future.
Now I'm not quite sure if they are suggesting:
A) a combination of Akida IP and Quadric IP, perhaps replacing the Quadric MACs (114) and ALUs (118) with Akida NPUs, and using Quadric's reconfigurable interconnexion architecture (120, 122) which I would see as a "coals to Newcastle" solution as far as Akida is concerned because Akida's NPU/core interconnect architecture is already highly flexible, and because the additional IC redesign work would be prohibitive, or
B) using Akida as an accelerator for Quadric, which would seem to be redundant, or
C) simply offering them for different tasks as FF suggests. FF's suggestion seems most probable from " the ability to help the customer determine which solution is best to integrate into a single chip or module", as clearly MegaChips sees them as complementary solutions.
Far be it from me to suggest that one of these makes the other redundant, but I'd like to see the evidence showing that Quadric is better than Akida with a CPU or GPU co-processor.
Hi @Rocket577 , @Fact Finder ,
here is an extract from an article posted by @Fullmoonfever discussing potential interworking of Akida and Quadric.
#10,930
What people have found is that the existing processors from ARM or RISC-V do not address the power performance requirements of the AI industry. There are some low-end cases that can be handled with software on these embedded processors. In general, people are looking for either accelerators to pair with those processors, or completely new processors, that would replace the embedded processor and AI into a much higher performance functionality.
In this case, MegaChips’ partner, BrainChip, is an example of an accelerator that would be combined with the existing embedded processors. In the case of its other IP partner, Quadric, they could be either used as an accelerator, or even supersede the need for an embedded processo
That’s where I read it lol, going to school and remember anything I was told, wasn’t my best skill
Hi @DiogeneseHi @Rocket577 , @Fact Finder ,
here is an extract from an article posted by @Fullmoonfever discussing potential interworking of Akida and Quadric.
#10,930
What people have found is that the existing processors from ARM or RISC-V do not address the power performance requirements of the AI industry. There are some low-end cases that can be handled with software on these embedded processors. In general, people are looking for either accelerators to pair with those processors, or completely new processors, that would replace the embedded processor and AI into a much higher performance functionality.
In this case, MegaChips’ partner, BrainChip, is an example of an accelerator that would be combined with the existing embedded processors. In the case of its other IP partner, Quadric, they could be either used as an accelerator, or even supersede the need for an embedded processor.
Determining success
Now, there have been attempts from some others, but not with much success. How can MegaChips determine its path?
megachips-logo-200x40-1.png
According to Fairbairn, we see this as an emerging market. Those who tried to enter with volume production capabilities up until now were too early to the party. It’s only now that people are reaching the point where they are in need of volume production opportunities.
There have been many obstacles to the adoption of AI, and adoption has been relatively slow. MegaChips realized that, and partnered with a couple of IP vendors that already had some significant traction, but also needed the muscle of pairing up with a silicon vendor to actually provide a complete solution to the customer.
By combining forces and offering that complete solution, and with the ability to help the customer determine which solution is best to integrate into a single chip or module, we can help overcome those things. We are investing heavily in internal capability to address this very need. We believe that we’re hitting the market at an ideal time to be involved with some designs that can go into production in the near future.
Now I'm not quite sure if they are suggesting:
A) a combination of Akida IP and Quadric IP, perhaps replacing the Quadric MACs (114) and ALUs (118) with Akida NPUs, and using Quadric's reconfigurable interconnexion architecture (120, 122) which I would see as a "coals to Newcastle" solution as far as Akida is concerned because Akida's NPU/core interconnect architecture is already highly flexible, and because the additional IC redesign work would be prohibitive, or
B) using Akida as an accelerator for Quadric, which would seem to be redundant, or
C) simply offering them for different tasks as FF suggests. FF's suggestion seems most probable from " the ability to help the customer determine which solution is best to integrate into a single chip or module", as clearly MegaChips sees them as complementary solutions.
Far be it from me to suggest that one of these makes the other redundant, but I'd like to see the evidence showing that Quadric is better than Akida with a CPU or GPU co-processor.
View attachment 6915
![]()
Ford-backed Argo AI launches driverless testing in Miami, Austin
Argo AI, the autonomous vehicle technology company backed by Ford and Volkswagen, is launching driverless testing operations in Miami and Austin, atechcrunch.com
Did u call it Akida?Well I got a new dog yesterday, just don’t get to see it until Monday. She was trying to hide from my fat staffy View attachment 6916
United States Patent Application 20220147797 Kind Code A1 MCLELLAND; Douglas ; et al. May 12, 2022
EVENT-BASED EXTRACTION OF FEATURES IN A CONVOLUTIONAL SPIKING NEURAL NETWORK
Abstract
A system is described that comprises a memory for storing data representative of at least one kernel, a plurality of spiking neuron circuits, and an input module for receiving spikes related to digital data. Each spike is relevant to a spiking neuron circuit and each spike has an associated spatial coordinate corresponding to a location in an input spike array. The system also comprises a transformation module configured to transform a kernel to produce a transformed kernel having an increased resolution relative to the kernel, and/or transform the input spike array to produce a transformed input spike array having an increased resolution relative to the input spike array. The system also comprises a packet collection module configured to collect spikes until a predetermined number of spikes relevant to the input spike array have been collected in a packet in memory, and to organize the collected relevant spikes in the packet based on the spatial coordinates of the spikes, and a convolutional neural processor configured to perform event-based convolution using memory and at least one of the transformed input spike array and the transformed kernel.
Inventors: MCLELLAND; Douglas; (Laguna Hills, CA) ; CARLSON; Kristofor D.; (Laguna Hills, CA) ; PATEL; Harshil K.; (Laguna Hills, CA) ; VANARSE; Anup A.; (Laguna Hills, CA) ; JOSHI; Milind; (Perth, AU)
Applicant:
Name City State Country Type
BrainChip, Inc.
Laguna Hills
CA
US Assignee: BrainChip, Inc.
Laguna Hills
CA Family ID: 1000006135263 Appl. No.: 17/583640 Filed: January 25, 2022
and
United States Patent Application 20220138543 Kind Code A1 VAN DER MADE; Peter AJ ; et al. May 5, 2022
EVENT-BASED CLASSIFICATION OF FEATURES IN A RECONFIGURABLE AND TEMPORALLY CODED CONVOLUTIONAL SPIKING NEURAL NETWORK
Abstract
Embodiments of the present invention provides a system and method of learning and classifying features to identify objects in images using a temporally coded deep spiking neural network, a classifying method by using a reconfigurable spiking neural network device or software comprising configuration logic, a plurality of reconfigurable spiking neurons and a second plurality of synapses. The spiking neural network device or software further comprises a plurality of user-selectable convolution and pooling engines. Each fully connected and convolution engine is capable of learning features, thus producing a plurality of feature map layers corresponding to a plurality of regions respectively, each of the convolution engines being used for obtaining a response of a neuron in the corresponding region. The neurons are modeled as Integrate and Fire neurons with a non-linear time constant, forming individual integrating threshold units with a spike output, eliminating the need for multiplication and addition of floating-point numbers.
Inventors: VAN DER MADE; Peter AJ; (Nedlands, AU) ; MANKAR; Anil S.; (Laguna Hills, CA) ; CARLSON; Kristofor D.; (Laguna Hills, CA) ; CHENG; Marco; (Laguna Hills, CA)
Applicant:
Name City State Country Type
BrainChip, Inc.
Laguna Hills
CA
US Assignee: BrainChip, Inc.
Laguna Hills
CA Appl. No.: 17/576103 Filed: January 14, 2022
Both filed within a week and half of each other.
The boys have been very busy.
Hi Tech,Patent History
Publication number: 20220147797
Type: Application
Filed: Jan 25, 2022
Publication Date: May 12, 2022
Applicant: BrainChip, Inc. (Laguna Hills, CA)
Inventors: Douglas MCLELLAND (Laguna Hills, CA), Kristofor D. CARLSON (Laguna Hills, CA), Harshil K. PATEL (Laguna Hills, CA), Anup A. VANARSE (Laguna Hills, CA), Milind JOSHI (Perth)
Application Number: 17/583,640
Is this a sign of the changing of the guard/s...I don't think so...BUT...check out the 3 Perth based "Dream Team" getting to put their inventors hats on....I'm personally really pleased for Anup and Harshil with whom I've had the pleasure to talk with in person.
This was obviously only published 5/6 days ago, so if this has already been posted, excuse me, as I can't keep up with all the brilliant articles being posted, I'm a slow reader
Good morning from Australia's Brainchip HQ.....Perth![]()