BRN Discussion Ongoing

[cosors]

I would have expected better from nvidia and of this is anything to go by I doubt nvidia are using Akida

I have a last one here too, then off to bed and off the eyes!

 

[supersonic001]

New branding on display, this looks fab, go chippers !!

 

[MDhere]

I would have expected better from nvidia and of this is anything to go by I doubt nvidia are using Akida

lololol i love that guys voice and humour! lol

 

[chapman89]

So Intel shareholders reject Intels CEO’s pay and other executives, now what’s going to happen when Brainchip become the industry standard by 2025 and akida has “saturated the market” because despite all the huffing and puffing by the CEO of Intel meeting with the US President and claiming to have the best of the best, he and the Intel shareholders will soon realise that Brainchip have the best of the best and when mainstream US media start talking about Brainchip and it’s potential to change the way we process data, this will be IMO a exponential rise in the share price from US investors and we will all have to hold on to our shares very tightly.

Shareholders reject Intel CEO pay | LinkedIn

While the vote is advisory and won’t immediately go into effect, it nonetheless indicates some investors might not be onboard with the company's turnaround plan.

www.linkedin.com

 

[Baisyet]

Here we go

 

[Rise from the ashes]

 

[Stable Genius]

Here we go

To reminisce. The conversations that raged for a week over that crinkled tablecloth!

I was in stitches over some of it!

Seems so long ago… and look how far they’ve come now!

Immaculately pressed and Hollywood lights.

Forwards and conquer!

 

[Bloodsy]

Morning all!

Found this article on twitter from a company called Ready robotics, was akida here?

https://labs.ready-robotics.com/art...XsZgEx6h207NH6obhfqsa-XddfYDqZdTIWqMSHzH8-CYU

They worked with Edge impulse to test for Anomaly detection for predictive maintenance...... sounds familiar....... They were able to train a neural network classifier "After a minute or so" Akida is a fast learner right.....

"At around 20 kilobytes in size, the ML model was extremely lightweight so could easily be deployed to the same machine controlling the robot with Forge/OS for low-latency predictive maintenance without requiring Internet connectivity."

The above excerpt is particularly interesting considering we know Akida can operate without internet connectivity!!

What do we think?

 

[SharesForBrekky]

To reminisce. The conversations that raged for a week over that crinkled tablecloth!

I was in stitches over some of it!

Seems so long ago… and look how far they’ve come now!

Immaculately pressed and Hollywood lights.

Forwards and conquer!

Now that's dedication for you. Jerome must have been up all night ironing that tablecloth. Love his work.

 

[nannapat]

So Intel shareholders reject Intels CEO’s pay and other executives, now what’s going to happen when Brainchip become the industry standard by 2025 and akida has “saturated the market” because despite all the huffing and puffing by the CEO of Intel meeting with the US President and claiming to have the best of the best, he and the Intel shareholders will soon realise that Brainchip have the best of the best and when mainstream US media start talking about Brainchip and it’s potential to change the way we process data, this will be IMO a exponential rise in the share price from US investors and we will all have to hold on to our shares very tightly.

Shareholders reject Intel CEO pay | LinkedIn

While the vote is advisory and won’t immediately go into effect, it nonetheless indicates some investors might not be onboard with the company's turnaround plan.

www.linkedin.com

Hi @chapman89 ,

Reading your attachment, shows how out of touch the CEO is including the board and his closed tight hip full of dollar bulging pocketed allies.

As a shareholder , I want to see every single employee benefit and be justly rewarded for their hard work and efforts = team effort… not ones sitting at the top of the helm, does not = team…. (Every single person is as important as their next working colleague, no matter what title one may hold)

Nan. xxx

 

[Quiltman]

Here we go

I notice MegaChips is setup next to our stand. A one stop shop for prospective end user edge customers. Sounds trite, but this indicates to me excellent communication between sales & marketing teams in respective organisations and bodes well.

 

[Deleted member 118]

Plenty of jobs in both Snn and edge now popping up online

https://scholarshipdb.net/scholarships?q=Edge+ai+&l=

https://scholarshipdb.net/spiking-neural-network-scholarships?page=1

https://www.ziprecruiter.com/Jobs/Edge-Computing

I did see Cisco adverting in the link

 

[db1969oz]

Hi @Rise from the ashes ,

Simples from Simple so called experts that have not done their due diligence nor any homework within their caveperson homework’s.

Whats a Neuromorpic chip anyway…

WANCA


(cant remember whom appointed the acronym, however what an absolute bloody legend , one to put in the BRN hall of fame)


Nan. xxx

Ahhh, thanks, I had missed it too.

 

[buena suerte :-)]

Another Great positive day/night and hopefully a Green day ahead for us!​

World Markets​

Japan NIKKEI 225​

+0.42%26,659.75+113.18

Hong Kong HANG SENG​

+3.27%20,602.52+673.64

London FTSE 100​

+0.72%7,518.35+53.93

Germany DAX​

+1.59%14,185.94+225.08
Updated: 11:55am ET

• SYMBOL	PRICE	CHANGE	%CHANGE
  DJIA	32,654.59	+431.17	+1.34
  NASDAQ	11,984.52	+321.73	+2.76
  S&P 500	4,088.85	+80.84	+2.02

​

​

BRCHF​

​

Brainchip Holdings Ltd.​

Ordinary Shares​

​

0.81​

0.02​

2.53%+​

0.7682 / 0.81 (1000 x 1000)​

​

​

BCHPY​

​

Brainchip Holdings Ltd.​

Sponsored ADR (1 ADS : 40 Ordinary)​

​

31.82​

0.68​

2.18%+​

31.34 / 33.58 (200 x 200)​

​

BRAINCHIP HOLDINGS LTD​

ISIN: AU000000BRN8 | WKN: A14Z7W | Symbol: 24Y | Type: Equity
OverviewChartsNewsKey DataPrice HistorySustainability
Frankfurt
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DayWeek1 Month6 Months1 Year3 YearsMax.

► Chart analyses

	17/05/22 10:08:53
Last price	0.7525
Change to prev. day	+4.51%

 

[DJM263]

I notice MegaChips is setup next to our stand. A one stop shop for prospective end user edge customers. Sounds trite, but this indicates to me excellent communication between sales & marketing teams in respective organisations and bodes well.

Nice Spotting @Quiltman, proving once again the 1,000 eyes are always looking

 

[Deleted member 118]

Another Great positive day/night and hopefully a Green day ahead.​

World Markets​

Japan NIKKEI 225​

+0.42%26,659.75+113.18

Hong Kong HANG SENG​

+3.27%20,602.52+673.64

London FTSE 100​

+0.72%7,518.35+53.93

Germany DAX​

+1.59%14,185.94+225.08
Updated: 11:55am ET

• SYMBOL	PRICE	CHANGE	%CHANGE
  DJIA	32,654.59	+431.17	+1.34
  NASDAQ	11,984.52	+321.73	+2.76
  S&P 500	4,088.85	+80.84	+2.02

​

​

BRCHF​

​

Brainchip Holdings Ltd.​

Ordinary Shares​

​

0.81​

0.02​

2.53%+​

0.7682 / 0.81 (1000 x 1000)​

​

​

BCHPY​

​

Brainchip Holdings Ltd.​

Sponsored ADR (1 ADS : 40 Ordinary)​

​

31.82​

0.68​

2.18%+​

31.34 / 33.58 (200 x 200)​

​

​

• https://money.cnn.com/quote/quote.html?symb=FCX

All I see is red at the end of the day

 

[Dhm]

Infrastructure bill mandates that new cars monitor drivers for signs of impairment

The $1.2 trillion infrastructure bill passed by Congress last week includes a mandate that carmakers include technology in new vehicles that monitors drivers for impaired driving

www.foxbusiness.com

Infrastructure bill mandates that new cars monitor drivers for signs of impairment

The $1.2 trillion infrastructure passed by Congress last week is headed to President Joe Biden's desk for signing, and included in the 2,700-page legislation is a mandate that all new cars will soon need to be outfitted with monitors aimed at detecting whether a driver is impaired and to shut down when unusual activity is flagged.

The new regulation requires that "monitoring systems to stop intoxicated drivers would roll out in all new vehicles as early as 2026, after the Transportation Department assesses the best form of technology to install in millions of vehicles and automakers are given time to comply."

Systems under consideration for the requirement include technology for monitoring a driver's breath, eye movements, or sweat, and if unusual activity is detected, the car "will either not start, not move, or will pull itself over," according Otte. She told the AP that "it will virtually eliminate the No. 1 killer on America's roads."

But some experts are pointing to privacy concerns over having drivers monitored by their own cars – and who would have access to that information.


---

when the systems are running locally, free from the cloud, privacy is less of a concern

If I could be able to give 10 upvotes to this post I would do so, and then re register and give 10 more! I know nothing in life is certain, but with help from you guys, the 1000 eyes, we have demonstrated that we could fulfil the prerequisites detailed in the papers. We most probably do this now with one hand tied behind our back. Lets hope our partners are front and centre with this.

It would make a great question for the forthcoming AGM.

 

[Boab]

Plenty of jobs in both Snn and edge now popping up online

https://scholarshipdb.net/scholarships?q=Edge+ai+&l=

https://scholarshipdb.net/spiking-neural-network-scholarships?page=1

Let the poaching commence. Going to get expensive to find the right people.

 

[Fact Finder]

We have been tracking Quadric since February on TSE. Given that we are co-partners with MegaChips it behoves us to keep a weather eye on them.

I find it useful to look at the problem a patent addresses. This one seeks to overcome the deficiencies of GPUs in performing NN tasks.

Basically they have designed a reconfigurable array of processors, much like a GPU, but have eliminated some redundant processing steps such as the addition of padding bits where the sensor data is absent.

The Quadric arrangement relies on synchronous operation and data inputs, whereas Akida has utilizes asynchronous data inputs, a particularly sweet adaptation for LiDaR.

For those who don't wish to know the score, turn away now.

US10474398B2 Machine perception and dense algorithm integrated circuit

Autonomous vehicles have been implemented with advanced sensor suites that provide a fusion of sensor data that enable route or path planning for autonomous vehicles. But, modern GPUs are not constructed for handling these additional high computation tasks.

[0006] At best, to enable a GPU or similar processing circuitry to handle additional sensor processing needs including path planning, sensor fusion, and the like, additional and/or disparate circuitry may be assembled to a traditional GPU. This fragmented and piecemeal approach to handling the additional perception processing needs of robotics and autonomous machines results in a number of inefficiencies in performing computations including inefficiencies in sensor signal processing.

1. An integrated circuit comprising:
a plurality of processing cores,
each processing core of the plurality of processing cores comprising:
at least one processing circuit; and
at least one memory circuit;
a plurality of peripheral cores,
each peripheral core of the plurality of peripheral cores comprising:
at least one memory circuit,
wherein:
at least a subset of the plurality of peripheral cores is arranged along a periphery of a first subset of the plurality of processing cores; and
[ii] a combination of the plurality of processing cores and the plurality of peripheral cores define an integrated circuit array;
a dispatch controller that provides data movement instructions, wherein the data movement instructions comprise a data flow schedule that:
defines an automatic movement of data within the integrated circuit array; and
sets one or more peripheral cores of the plurality of peripheral cores to a predetermined constant value if no data is provided to the one or more peripheral cores according to the predetermined data flow schedule.



View attachment 6877


130 = dispatch controller
140, 150 = periphery controllers
149, 159 = FIFO registers
160 = sensor data memory
View attachment 6883


112 = register file
122 = register file
114 = MAC
118 = ALU

[0039] An array core 110 may, additionally or alternatively, include a plurality of multiplier (multiply) accumulators (MACs) 114 or any suitable logic devices or digital circuits that may be capable of performing multiply and summation functions. In a preferred embodiment, each array core 110 includes four (4) MACs and each MAC 114 may be arranged at or near a specific side of a rectangular shaped array core 110 , as shown by way of example in FIG. 2.

[0035] An array core 110 preferably functions as a data or signal processing node (e.g., a small microprocessor) or processing circuit and preferably, includes a register file 112 having a large data storage capacity (e.g., 4 kilobyte (KB) or greater, etc.) and an arithmetic logic unit (ALU) 118 or any suitable digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. In a preferred embodiment, the register file 112 of an array core 110 may be the only memory element that the processing circuits of an array core no may have direct access to. An array core no may have indirect access to memory outside of the array core and/or the integrated circuit array 105 (i.e., core mesh) defined by the plurality of border cores 120 and the plurality of array cores 110 .

[0036] The register file 112 of an array core no may be any suitable memory element or device, but preferably comprises one or more static random-access memories (SRAMs). The register file 112 may include a large number of registers, such as 1024 registers, that enables the storage of a sufficiently large data set for processing by the array core no. Accordingly, a technical benefit achieved by an arrangement of the large register file 112 within each array core 110 is that the large register file 112 reduces a need by an array core 110 to fetch and load data into its register file 112 for processing. As a result, a number of clock cycles required by the array core 112 to push data into and pull data out of memory is significantly reduced or eliminated altogether.

[0044] In a traditional integrated circuit (e.g., a GPU or the like), when input image data (or any other suitable sensor data) received for processing compute-intensive application (e.g., neural network algorithm) within such a circuit, it may be necessary to issue padding requests to areas within the circuit which do not include image values (e.g., pixel values) based on the input image data. That is, during image processing or the like, the traditional integrated circuit may function to perform image processing from a memory element that does not contain any image data value. In such instances, the traditional integrated circuit may function to request that a padding value, such as zero, be added to the memory element to avoid subsequent image processing efforts at the memory element without an image data value. A consequence of this typical image data processing by the traditional integrated circuit results in a number of clock cycles spent identifying the blank memory element and adding a computable value to the memory element for image processing or the like by the traditional integrated circuit.

Autonomous vehicles have been implemented with advanced sensor suites that provide a fusion of sensor data that enable route or path planning for autonomous vehicles. But, modern GPUs are not constructed for handling these additional high computation tasks.

[0006] At best, to enable a GPU or similar processing circuitry to handle additional sensor processing needs including path planning, sensor fusion, and the like, additional and/or disparate circuitry may be assembled to a traditional GPU. This fragmented and piecemeal approach to handling the additional perception processing needs of robotics and autonomous machines results in a number of inefficiencies in performing computations including inefficiencies in sensor signal processing.

1. An integrated circuit comprising:
a plurality of processing cores,
each processing core of the plurality of processing cores comprising:
at least one processing circuit; and
at least one memory circuit;
a plurality of peripheral cores,
each peripheral core of the plurality of peripheral cores comprising:
at least one memory circuit,
wherein:
at least a subset of the plurality of peripheral cores is arranged along a periphery of a first subset of the plurality of processing cores; and
[ii] a combination of the plurality of processing cores and the plurality of peripheral cores define an integrated circuit array;
a dispatch controller that provides data movement instructions, wherein the data movement instructions comprise a data flow schedule that:
defines an automatic movement of data within the integrated circuit array; and
sets one or more peripheral cores of the plurality of peripheral cores to a predetermined constant value if no data is provided to the one or more peripheral cores according to the predetermined data flow schedule.

Brilliant!

Hi @Diogenese

When I first read about Quadric I thought about the fact that there is yet to be a single agreed definition of the Edge and where it actually is in a system.

It struck me then that AKIDA at the far Edge with its mum saying be careful you should not be that close and Quadric at a safer place back from the Edge with its mum saying AKIDA come back and stand with your cousin Quadric was why MegaChips have both solutions.

The following which I extracted from the group of words you posted seems to fit this scenario with AKIDA making all the sensors intelligent and a Quadric processing the AKIDA made relevant data:

“Autonomous vehicles have been implemented with advanced sensor suites that provide a fusion of sensor data that enable route or path planning for autonomous vehicles. But, modern GPUs are not constructed for handling these additional high computation tasks.

[0006] At best, to enable a GPU or similar processing circuitry to handle additional sensor processing needs including path planning, sensor fusion, and the like, additional and/or disparate circuitry may be assembled to a traditional GPU”

If you generally agree then I can allow the rest of the technological differences to happily go over my head?

My opinion only DYOR
FF

AKIDA BALLISTA

 

[Deleted member 118]

Hi @Diogenese

When I first read about Quadric I thought about the fact that there is yet to be a single agreed definition of the Edge and where it actually is in a system.

It struck me then that AKIDA at the far Edge with its mum saying be careful you should not be that close and Quadric at a safer place back from the Edge with its mum saying AKIDA come back and stand with your cousin Quadric was why MefaChips have both solutions.

The following which I extracted from the group of words you posted seems to fit this scenario with AKIDA making all the sensors intelligent and a Quadric processing the AKIDA made relevant data:

“Autonomous vehicles have been implemented with advanced sensor suites that provide a fusion of sensor data that enable route or path planning for autonomous vehicles. But, modern GPUs are not constructed for handling these additional high computation tasks.

[0006] At best, to enable a GPU or similar processing circuitry to handle additional sensor processing needs including path planning, sensor fusion, and the like, additional and/or disparate circuitry may be assembled to a traditional GPU”

If you generally agree then I can allow the rest of the technological differences to happily go over my head?

My opinion only DYOR
FF

AKIDA BALLISTA

I did read a good article on how both these companies technology will work hand in hand together, I’ll try and find it again.