BRN Discussion Ongoing

[Dallas]

Paul-François Fournier on LinkedIn: PROPHESEE

💥 PROPHESEE investit 15 millions d'euros pour le développement de l’IA neuromorphique « Made in France ». Le projet vise au développement d’une nouvelle…

www.linkedin.com

 

[IloveLamp]

BrainChip on LinkedIn: #ai #ml #healthcare #akida

The integration of #AI and #ML is transforming #healthcare by enabling more effective and portable solutions for vital signs analysis and diagnostics…

www.linkedin.com

 

[DK6161]

Hey Esq gay or straight I'm not the one to judge peoples life style.

But the trading well until there is some activity or interest in new money they will keep playing this game they do.

It's a left hand to right hand when they stop its usually cause they need to wait out and catch some shares from sellers to balance any deficit. I mean we can't trade at 1/4 a cent but they can. Why can't we do that.

If there was more net buyers then sellers then you would see the price move north then again they do these pump and dumps too but usually that is because there is a party taking a position.

Like last time word was a buyer did take a position over January so yeah that activity excites people and they buy driving the price up with the computer programs still.

Really if you broken-hearted trades down if your tracking them Esq I bet the days you see predominantly the 1/4 cent trades they are red days the 1/2 cent day which is normal you would see a net positive day for the most part. Imo

 

[IloveLamp]

https://www.eetimes.com/unleashing-the-potential-of-alternative-deep-learning-hardware/

 

[supersonic001]

BrainChip on LinkedIn: #ai #ml #healthcare #akida

The integration of #AI and #ML is transforming #healthcare by enabling more effective and portable solutions for vital signs analysis and diagnostics…

www.linkedin.com

 

[7für7]

BrainChip on LinkedIn: #ai #ml #healthcare #akida

The integration of #AI and #ML is transforming #healthcare by enabling more effective and portable solutions for vital signs analysis and diagnostics…

www.linkedin.com

View attachment 66417

This was already posted by @Dallas .. I postet it too and deleted it.

 

[GDJR69]

Hmmmm ...

What we need to take into consideration is the crucial fact that the product has been in a state of ongoing development for quite a while and this would have played a major part in management's selection of the business model.

For more than 2 years, the company was aware that Akida 2 with TeNNs was in the pipeline, and they would have understood that this would influence the EAPs. The company would have been anxious not to lumber the EAPs with large numbers of "superceded" chips, or at least to give them the choice.

While TeNNs is still not available in silicon, simulation software would have been available for EAPs from the time the patent application was filed, and that would have been undergoing continual improvement. Our partner EAPs would have been in on the secret. EAPs like Valeo and Mercedes have competitive pressures which would have weighed against waiting for Akida 2 SoC, which is one of the reasons why I suspect they have gone ahead with the simulation software as an interim measure. The software was immediately available and readily adaptable as product development progressed.

The development must have been finished, or at least reached a set benchmark, when Anil announced tapeout (about 6 months ago?), but this was then superceded by an overriding announcement that a masked stranger was about to do us a power of good and take over the chip production - since then, not a sausage.

So my Hail Mary speculation is that we are running a parallel software licensing program in parallel with, or in advance of the IP licensing program. Given that this would be in the context of joint developments, the details would be commercial-in-confidence.

All this is derived from my reading of the tea leaves (the crystal ball is being fitted with Gen AI LLMs as we speak).

The Edge Box has sold out, so, with the hindsight of the development of TeNNs, I am reluctant to call it a mistake, or even a tactical error, but it would have been nice to have had more chips for sale.

Gosh - I didn't know I knew that many words!

Thanks Diogenese, that's a great post with a lot of insight.

I think another way of viewing the situation is that perhaps the company had no practical choice but to pursue an IP model (because of all the factors you have identified and one additional factor I would add - the capital required to produce the chips) .

The idea of a 'parallel software licensing program' has also occurred to me too. It seems unlikely that we are providing the software to partners without protections around the IP. Some may recall I asked Tony some time ago if there is a partnership agreement in place for these partnerships and he said yes. I'd be surprised if there weren't terms in the agreements effectively licensing, and at least regulating, the use of the IP. We can only hope that these arrangements turn into profitable ones in due course. I've always viewed these partnerships as JV's to develop the product.

Yours Yoda

 

[Bravo]

July 22 Deadline for ASCR Call for Papers: Workshop on Neuromorphic Computing for Science​

July 10, 2024 by staff Leave a Comment

July 10, 2024 — The U.S. Department of Energy’s Advanced Scientific Computing Research (ASCR) program has announced a Monday July 22 deadline (11:59 pm ET) for position papers for a workship on neuromorphic computing for science.
The workshop website can be found here. Notification of position acceptance will be issues on Friday, Aug. 2. For meeting technical questions, please contact: Todd Munson, Todd.Munson@science.doe.gov
The 2024 Workshop on Basic Research Needs for Neuromorphic Computing, to be held Thursday and Friday, Sept. 12-13 in the greater Washington, DC area, will inform and draft a set of grand challenges for advancing the field of neuromorphic computing and developing proof of principle neuromorphic circuits applicable for High Performance Computer (HPC) acceleration for scientific discovery, and brainstorm ideas needed for a successful, robust, and world leading basic research program.
​

Engineering novel neuromorphic computing systems with functionalities, capabilities, and energy efficiency similar to biological brains is one of the most exciting and challenging scientific endeavors of our time. This workshop aims to identify key research needs, challenges, and next steps necessary to develop biologically-realistic neuromorphic circuits primitives that capture the functionality of neural systems found in nature. Moreover, simulating neuromorphic computing primitives integrated into networks will be key to understanding their behavior at scale, particularly for those computing architectures where full-scale commercial fabrication is not yet readily accessible. Appropriate neuroscience datasets and metrics will have to be established to vet proposed neuromorphic circuits.

In the development of new circuits and methodologies for neuromorphic computing, it is critical that there is close collaboration among circuit designers, computer engineers, computational neuroscientists, and algorithms and simulation researchers. This workshop aims to bring together a diverse range of experts across three complementary technical areas.
Submit position paper to the technical areas below:

1. Neuroscience algorithms and translation to neuromorphic analog circuits
   This technical area is driven by the fundamental question “What are the key neuromorphic circuit primitives that are needed to capture the full functionality of critical biological computing mechanisms?”. The goal of the activities in this space is to understand what principles and circuit structures of brain organization and dynamics underpin its functionality and robustness capabilities and how these principles can be translated into functionally-equivalent neuromorphic circuits and systems that could be practically implemented (with available technology?). Ideas related to neuromorphic computing principles inspired from brain regions/functions (cortical, hippocampus, thalamus, sensing, motor control, etc.) are sought after. Topics related to neuromorphic approaches and emulations of small invertebrate brains are also of interest.
2. Technologies and prototyping of neuromorphic analog primitives
   This technical effort is driven by the fundamental question “What are the technologies needed to demonstrate and prototype key neuromorphic circuit primitives?” Ideas related to novel neuromorphic circuits based on new devices and designs, and new principles guided by neuroscience-inspired functionality are of interest. Ideas related to emerging analog technologies that provide orders of magnitude in performance, parallelism, energy efficiency, tunability range, temporal delays, etc., and that mimic the biological behavior and robustness of key primitives are welcomed. Also of interest are topics related to high neuromorphic connectivity capabilities, e.g. optoelectronic technologies and photonic interconnects.
3. Scalable integration for neuromorphic computing modeling
   The fundamental question driving this technical area is “What are the critical characteristics for effective large-scale simulation of neuromorphic circuits and systems?” New approaches are needed to create simulations of large-scale biologically-realistic neural networks, diverse synapse connectivity, and sophisticated network activity. Of interest are ideas related to novel methods to integrate and to scale up the simulation of the neuromorphic circuit primitives using high-performance computing in order to understand their interactions in the context of hundreds of millions of neurons and synapses. Also welcomed are novel methodologies for the efficient exploration of the large co-design space between neuromorphic algorithms and circuit technologies.

When discussing the technical idea and how it fits in the technical area(s) and the overall vision of the workshop, include a discussion on the benchmarks, metrics, and/or datasets requirements for neuromorphic computing for your proposed implementation.
Submission Guidelines
The structure for the ideal position paper may include several of the below themes:

1. Neuroscience-inspired computing principles
2. Translation to analog microelectronic circuits
3. Modeling and simulation approaches
4. Performance metrics, data requirements, and energy efficiency

The position paper should be an individual submission, one paper per investigator. The format is one page (plus one extra page for figures, captions and references only) with an 11-point font, submitted in a Word or PDF document. The primary theme should be mentioned during the submission, a secondary theme is optional.

Accepted position papers will be made public.
The following information is being collected during the submission process:

1. Author email
2. Author first name
3. Author last name
4. Author organization
5. Position paper title
6. Position paper theme(s)
7. Position paper abstract
8. Position paper file

Submissions will be reviewed by the workshop’s organizing committee using criteria of overall quality, relevance, likelihood of stimulating constructive discussion, and ability to contribute to an informative workshop report. Unique positions that are well presented and emphasize potentially transformative research directions will be given preference.
Workshop Organizers
Co-Chairs

• Gina Adam, George Washington University
• Garrett Kenyon, Los Alamos National Laboratory
• Thomas Potok, Oak Ridge National Laboratory

Organizing Committee

• Giorgio Ascoli, George Mason University
• Frances Chance, Sandia National Laboratory
• Yiran Chen, Duke University
• Joseph Friedman, University of Texas at Dallas
• Cory Merkel, Rochester Institute of Technology
• Maryam Parsa, George Mason University
• Midya Parto, University of Central Florida
• Catherine Schuman, University of Tennessee Knoxville
• Shinjae Yoo, Brookhaven National Laboratory
• Yuping Zeng, University of Delaware

July 22 Deadline for ASCR Call for Papers: Workshop on Neuromorphic Computing for Science - High-Performance Computing News Analysis | insideHPC

July 10, 2024 — The U.S. Department of Energy’s Advanced Scientific Computing Research (ASCR) program has announced a Monday July 22 deadline (11:59 pm ET) for position papers for a workship on neuromorphic computing for science. The workshop website can be found here. Notification of position...

insidehpc.com

 

[7für7]

How ironic… while the western hemisphere is afraid of AI and make apocalyptic scenarios (terminator, matrix, etc) the rest of the world don’t give a f…

Researchers create a robot which is controlled by real human brain cells, and it is more intelligent than AI

Researchers at Tianjin University in China have developed a humanoid robot that operates using human brain cells. The robot learns and adapts to its environment through electrical signals and sensory inputs, bypassing the need for pre-programmed instructions.

www.indiatoday.in

 

[MadMayHam | 合氣道]

Well, even (supposedly struggling) AI chip co Graphcore got bought up... by Softbank no less (undisclosed amount). The logical assumption is also that ARM would be working closely with them for AI capability.

https://www.reuters.com/technology/artificial-intelligence/japans-softbank-acquires-british-ai-chipmaker-graphcore-2024-07-11/

 

[Bravo]

SoftBank buys UK chipmaker Graphcore in AI push

Deal will give Bristol-based company a resource boost while advancing the ‘next big bet’ of Masayoshi Son’s group

Graphcore’s founders Simon Knowles, left, and Nigel Toon, right, will stay on following SoftBank’s acquisition of the AI chipmaker © Gareth Iwan Jones/FT

David Keohane in Tokyo, Tim Bradshaw and Ivan Levingston in London2 HOURS AGO



SoftBank has bought UK-based chipmaker Graphcore, as the Japanese tech group founded by Masayoshi Son accelerates its multibillion-dollar push into artificial intelligence.

Graphcore, an AI-focused start-up that was founded by UK semiconductor industry veterans in 2016, will sit alongside chip designer Arm in SoftBank’s portfolio, as Son readies his “next big bet” in the tech industry.

“Graphcore will join SoftBank Group to build the next generation of AI compute,” said Nigel Toon, chief executive and co-founder of Graphcore. He said he had conversations with all levels of SoftBank before the deal was agreed: “We are part of the delivery behind a very grand vision.”

The money to buy Graphcore is coming from SoftBank Group itself, rather than its Vision Funds, reflecting the strategic nature of the investment.

“With the advent and the acceleration of AI, what’s going to be critical is the foundation layers — not just the models but all the infrastructure around it, including on the semiconductor and systems side,” said Vikas Parekh, a San Francisco-based SoftBank executive who led the investment.

“The profit pools will grow longer term, and we expect that lots of players will develop solutions and participate in that pool,” Parekh added.

Pitched as a rival to Nvidia, which dominates the market for high-performance AI chips, Graphcore’s “intelligence processing units” are designed for the specialised requirements of AI applications.

But it has struggled to commercialise its technology, generating just $2.7mn in sales and $205mn in pre-tax losses in 2022, the most recent year for which Graphcore’s accounts are publicly available. The company warned last October that it needed to raise new capital within months.

Neither SoftBank nor Graphcore would confirm the value of the deal. Two people familiar with the matter said it was just above $600mn, less than the roughly $700mn that the company had raised in venture capital.

That would be an anticlimax for Graphcore’s investors, who had valued it at around $2.5bn in 2020. Backers include Microsoft, OpenAI’s co-founder Ilya Sutskever, Molten Ventures, Atomico and Baillie Gifford.

Toon — who along with his co-founder and chief technology officer, Simon Knowles, is staying on after the deal — said that the company’s biggest issue was a lack of scale and capital.

SoftBank will provide Graphcore with a “huge amount of resources” to take on US chipmaking giants Nvidia and AMD, he said, adding “quite significantly” to its UK headcount. Its headquarters will remain in Bristol.

Armed with billions of dollars, Son wants to position SoftBank at the centre of what he considers to be humanity’s next evolutionary stage and support its crown jewel, Arm.

Arm, the UK-based chip designer in which SoftBank holds a roughly 90 per cent stake, has more than tripled in value since its initial public offering last September, as investors see it taking a more central role in the AI boom.

“We will be co-operating across the whole SoftBank family,” Toon said, without giving details of any potential collaboration with Arm. It declined to comment.

The deal closed after receiving the required regulatory approvals in the UK and US, as well as national security clearance from the British government, Toon said.

Ahead of the deal, Graphcore decided to exit its China business — where it had worked with companies including Baidu — after US export controls on AI chips had made working there “very difficult”, Toon said. Graphcore and SoftBank will now focus on AI customers in the US and Europe.

Last month, Son told shareholders that investments SoftBank had made in the past — including some high-profile losses, such as desk sharing start-up WeWork — were “just a warm-up” for his grand ambition to create an era of AI.

Dealmaking is also picking up. SoftBank in May led an investment of more than $1bn in UK self-driving car start-up Wayve, marking Europe’s largest AI deal to date.

SoftBank buys UK chipmaker Graphcore in AI push

Deal will give Bristol-based company a resource boost while advancing the ‘next big bet’ of Masayoshi Son’s group

www.ft.com

 

[Bravo]

 

[Bravo]

Microchip's new PIC64-HPSC is expected to see widespread adoption in air, land and sea applications. Samples will be available to Microchip’s early access partners in 2025.

As posted previously, I expect we will be incorporated into the HPSC at some point in the nearish future.

Microchip launches space-grade processors for AI applications​

EditorAhmed Abdulazez Abdulkadir
Company News
Published 07/09/2024, 08:22 AM

Microchip launches space-grade processors for AI applications By Investing.com

Microchip launches space-grade processors for AI applications

www.investing.com

 

[Diogenese]

July 22 Deadline for ASCR Call for Papers: Workshop on Neuromorphic Computing for Science​

July 10, 2024 by staff Leave a Comment

July 10, 2024 — The U.S. Department of Energy’s Advanced Scientific Computing Research (ASCR) program has announced a Monday July 22 deadline (11:59 pm ET) for position papers for a workship on neuromorphic computing for science.
The workshop website can be found here. Notification of position acceptance will be issues on Friday, Aug. 2. For meeting technical questions, please contact: Todd Munson, Todd.Munson@science.doe.gov
The 2024 Workshop on Basic Research Needs for Neuromorphic Computing, to be held Thursday and Friday, Sept. 12-13 in the greater Washington, DC area, will inform and draft a set of grand challenges for advancing the field of neuromorphic computing and developing proof of principle neuromorphic circuits applicable for High Performance Computer (HPC) acceleration for scientific discovery, and brainstorm ideas needed for a successful, robust, and world leading basic research program.
​

Engineering novel neuromorphic computing systems with functionalities, capabilities, and energy efficiency similar to biological brains is one of the most exciting and challenging scientific endeavors of our time. This workshop aims to identify key research needs, challenges, and next steps necessary to develop biologically-realistic neuromorphic circuits primitives that capture the functionality of neural systems found in nature. Moreover, simulating neuromorphic computing primitives integrated into networks will be key to understanding their behavior at scale, particularly for those computing architectures where full-scale commercial fabrication is not yet readily accessible. Appropriate neuroscience datasets and metrics will have to be established to vet proposed neuromorphic circuits.

In the development of new circuits and methodologies for neuromorphic computing, it is critical that there is close collaboration among circuit designers, computer engineers, computational neuroscientists, and algorithms and simulation researchers. This workshop aims to bring together a diverse range of experts across three complementary technical areas.
Submit position paper to the technical areas below:

1. Neuroscience algorithms and translation to neuromorphic analog circuits
   This technical area is driven by the fundamental question “What are the key neuromorphic circuit primitives that are needed to capture the full functionality of critical biological computing mechanisms?”. The goal of the activities in this space is to understand what principles and circuit structures of brain organization and dynamics underpin its functionality and robustness capabilities and how these principles can be translated into functionally-equivalent neuromorphic circuits and systems that could be practically implemented (with available technology?). Ideas related to neuromorphic computing principles inspired from brain regions/functions (cortical, hippocampus, thalamus, sensing, motor control, etc.) are sought after. Topics related to neuromorphic approaches and emulations of small invertebrate brains are also of interest.
2. Technologies and prototyping of neuromorphic analog primitives
   This technical effort is driven by the fundamental question “What are the technologies needed to demonstrate and prototype key neuromorphic circuit primitives?” Ideas related to novel neuromorphic circuits based on new devices and designs, and new principles guided by neuroscience-inspired functionality are of interest. Ideas related to emerging analog technologies that provide orders of magnitude in performance, parallelism, energy efficiency, tunability range, temporal delays, etc., and that mimic the biological behavior and robustness of key primitives are welcomed. Also of interest are topics related to high neuromorphic connectivity capabilities, e.g. optoelectronic technologies and photonic interconnects.
3. Scalable integration for neuromorphic computing modeling
   The fundamental question driving this technical area is “What are the critical characteristics for effective large-scale simulation of neuromorphic circuits and systems?” New approaches are needed to create simulations of large-scale biologically-realistic neural networks, diverse synapse connectivity, and sophisticated network activity. Of interest are ideas related to novel methods to integrate and to scale up the simulation of the neuromorphic circuit primitives using high-performance computing in order to understand their interactions in the context of hundreds of millions of neurons and synapses. Also welcomed are novel methodologies for the efficient exploration of the large co-design space between neuromorphic algorithms and circuit technologies.

When discussing the technical idea and how it fits in the technical area(s) and the overall vision of the workshop, include a discussion on the benchmarks, metrics, and/or datasets requirements for neuromorphic computing for your proposed implementation.
Submission Guidelines
The structure for the ideal position paper may include several of the below themes:

1. Neuroscience-inspired computing principles
2. Translation to analog microelectronic circuits
3. Modeling and simulation approaches
4. Performance metrics, data requirements, and energy efficiency

The position paper should be an individual submission, one paper per investigator. The format is one page (plus one extra page for figures, captions and references only) with an 11-point font, submitted in a Word or PDF document. The primary theme should be mentioned during the submission, a secondary theme is optional.

Accepted position papers will be made public.
The following information is being collected during the submission process:

1. Author email
2. Author first name
3. Author last name
4. Author organization
5. Position paper title
6. Position paper theme(s)
7. Position paper abstract
8. Position paper file

Submissions will be reviewed by the workshop’s organizing committee using criteria of overall quality, relevance, likelihood of stimulating constructive discussion, and ability to contribute to an informative workshop report. Unique positions that are well presented and emphasize potentially transformative research directions will be given preference.
Workshop Organizers
Co-Chairs

• Gina Adam, George Washington University
• Garrett Kenyon, Los Alamos National Laboratory
• Thomas Potok, Oak Ridge National Laboratory

Organizing Committee

• Giorgio Ascoli, George Mason University
• Frances Chance, Sandia National Laboratory
• Yiran Chen, Duke University
• Joseph Friedman, University of Texas at Dallas
• Cory Merkel, Rochester Institute of Technology
• Maryam Parsa, George Mason University
• Midya Parto, University of Central Florida
• Catherine Schuman, University of Tennessee Knoxville
• Shinjae Yoo, Brookhaven National Laboratory
• Yuping Zeng, University of Delaware

July 22 Deadline for ASCR Call for Papers: Workshop on Neuromorphic Computing for Science - High-Performance Computing News Analysis | insideHPC

July 10, 2024 — The U.S. Department of Energy’s Advanced Scientific Computing Research (ASCR) program has announced a Monday July 22 deadline (11:59 pm ET) for position papers for a workship on neuromorphic computing for science. The workshop website can be found here. Notification of position...

insidehpc.com

... and the next thing we want to invent is a round rotatable thing with applications in transport.

 

[Diogenese]

Microchip's new PIC64-HPSC is expected to see widespread adoption in air, land and sea applications. Samples will be available to Microchip’s early access partners in 2025.

As posted previously, I expect we will be incorporated into the HPSC at some point in the nearish future.

Microchip launches space-grade processors for AI applications​

EditorAhmed Abdulazez Abdulkadir
Company News
Published 07/09/2024, 08:22 AM

View attachment 66428

Microchip launches space-grade processors for AI applications By Investing.com

Microchip launches space-grade processors for AI applications

www.investing.com

Hi Bravo,

I've just realized that SNNs are inherently more transient radiation error (glitch) tolerant than von Neumann.

vN relies on mathematical precision, so a one-bit error always results in an output error. The magnitude of the error would be influenced by the rank of the bit corrupted, from LSB (least significant bit) to MSB.

On the other hand, SNNs rely not on mathematical precision, but on probability based on thousands of "events", so a single error is lost in the noise.

...

Meanwhile, back at the workshop:

"if I just keep cutting off the corners of this square ..."

 

[Pom down under]

Microchip's new PIC64-HPSC is expected to see widespread adoption in air, land and sea applications. Samples will be available to Microchip’s early access partners in 2025.

As posted previously, I expect we will be incorporated into the HPSC at some point in the nearish future.

Microchip launches space-grade processors for AI applications​

EditorAhmed Abdulazez Abdulkadir
Company News
Published 07/09/2024, 08:22 AM

View attachment 66428

Microchip launches space-grade processors for AI applications By Investing.com

Microchip launches space-grade processors for AI applications

www.investing.com

Samples available for EAP in 2025 and even if we were involved we could see some income from royalties maybe 3-5 years later

 

[Bravo]

Samples available for EAP in 2025 and even if we were involved we could see some income from royalties maybe 3-5 years later

 

[Esq.111]

Thought this was rather funny....

Regards ,
Esq.

 

[Pom down under]

View attachment 66443

 

[HopalongPetrovski]

View attachment 66449

Buck up Buddy.
Every self made millionaire had days like these, before their ship came in.