Smoothsailing
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There is something about these chiplets that will become ubiquitous imo
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PROPHESEE on LinkedIn: EventPS: Real-Time Photometric Stereo Using an Event Camera
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Frangipani
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Baya Systems, the company our former CMO Nandan Nayampally now works for as CCO, emerged from stealth mode today.
Chairman of the Board is Tenstorrent’s CEO Jim Keller.
www.eenewseurope.com
By Nick Flaherty
The company has executive from Intel, Netspeed Systems, ARM, Brainchip, AMD and Nuvia and is chaired by microprocessor expert Jim Keller, who is also CEO of AI chip developer Tenstorrent. It is backed by Matrix and Intel Capital.
“We focus on the data driven generation of IP with both static and dynamic microarchitectural analysis at runtime,” said Nayampally. “When you do complex systems, the devil is in the detail and system fabric is not that easy.”
The WeaveIP provides components to build a unified fabric that has an efficient, scalable transport architecture that maximizes performance and throughput, while minimizing latency, silicon footprint and power. This supports standard protocols such as CHI, ACE5-Lite, AXI5 and extendable to others including CXL.
The WeaverPro tool supports the SoC designer from initial specification all the way to post-silicon tuning. This uses the WeaveIP to produce a unified mesh fabric approach to generating layer protocols on top of the fabric without the need for gaskets that translate the protocols and the bottlenecks that come with this and slow down the performance.
“The transport is common so you can customise that for the QoS or debug protocols and build protocols on top.”
This comes from the software-driven analysis of the design that can configure up to eight virtual channels across the chip at runtime.
“What we do with our software is very efficient cache memory analysis, get accurate partitioning and caching, and a fabric component that generates a correct by construction physical design. We have two main flavours, where you can define your own protocol and one with multicast for AI designs,” he said.
“We can optimise the bandwidth and reduce the wires and logic to use those wires efficiently for optimising for latency and bandwidth, with up to 3GHz in a 4nm process.”
The fabric is customisable at runtime with APIs so you can tune the parameters for efficiency. “In general the flexibility we have put in helps overall with the reduction in silicon footprint and power and that comes from having an accurate understanding of the data movement,” he said.
The fabric is designed for inside the chip and the chiplet, and Baya will work with interconnect schemes such as Eliyan’s Bunch of Wires and UCIe.
“We stop at the die boundaries but what we end up doing outside of that is the software understands chiplet boundaries and can optimise across chiplet boundaries. So it’s a chiplet-ready network, as various things need to be built into the network to make it easier to use in chiplets,” he said.
“Our first partner is Blue Cheetah. They do the link layers, and once we understand their wires we can optimise and allow API tuning in the future as well,” said Nayampally
“The semiconductor industry is at an inflection point in how to overcome the widening gap between memory performance and the processing needs of AI,” said Dr. Sailesh Kumar, CEO at Baya Systems.
“These challenges are overwhelming the industry with design complexity, energy costs, and systems that are obsolete by the time they hit the market. Baya Systems is resolute in delivering foundational software, an industry-first, grounds-up fabric solution for future-proof multi-cluster and multi-chiplet designs, and a methodology that takes out the guesswork. I firmly believe that Baya unlocks the merchant chiplet market that is expected to grow to $107 billion by 2033.”
www.bayasystems.com
bayasystems.com
Go to...
Software and IP addresses system design complexity, performance, scalability and Time to Market of SoCs and chiplets for emerging applications.
Santa Clara, CALIF. – June 20, 2024 – Baya Systems today emerged from stealth mode to announce its software-driven IP technology portfolio designed to accelerate complex single-die and multi-die SoC designs. These innovations bolster the emerging chiplet economy and enable unprecedented scale for large-scale compute and AI processing.
Baya Systems technology simplifies the development process and reduces the risk, empowering designers to rapidly analyze, develop, optimize and deploy these complex systems. This enables highly energy-efficient data movement in single-die designs that can support over 4 terabyte/second throughput in a complex CPU cluster, culminating in multi-petabyte/second throughput in multi-chiplet designs for high-end AI installations.
With the exponential growth of computing requirements for artificial intelligence, best-in-class silicon vendors have consistently tried to scale performance efficiently by integrating various processors, including CPUs, GPUs, and neural network accelerators, into intelligent compute systems. This has led to a substantial challenge of efficient data movement across these different processors, and increasingly complex system and application software development. Baya Systems focuses on delivering hyper-efficient data movement that can be customized with efficient hardware-based coherency, correctness, and robustness to accelerate these platforms for applications across industries such as AI acceleration, data center, networking infrastructure, automotive and IoT.
“The rapid scaling in compute needed to support AI is bottlenecked by scaling silicon, memory, storage, and the increasingly huge amounts of data; requiring increasingly complex SoCs and chiplets,” said Kevin Krewell, Principal Analyst at TIRIAS Research. “The industry desperately needs a holistic way to design, analyze, and build intelligent fabrics to address this, and Baya seems to have the right ingredients to really drive the market forward.”
Baya Systems tackles the challenges of system design complexity, performance guarantees, high costs, and shrinking market windows in the SoC and chiplet industries. Its WeaverPro™ software platform supports the SoC designer from initial specification all the way to post-silicon tuning. Its WeaveIP™ provides components to build a unified fabric that has an extremely efficient, scalable transport architecture that maximizes performance and throughput, while minimizing latency, silicon footprint and power. Combined with advanced features for reliability and safety, this empowers designers to analyze, architect, customize, optimize and deploy complex SoCs and chiplets.
Baya’s solution is unique for the following reasons:
“The semiconductor industry is at an inflection point in how to overcome the widening gap between memory performance and the processing needs of AI,” said Dr. Sailesh Kumar, CEO at Baya Systems. “These challenges are overwhelming the industry with design complexity, energy costs, and systems that are obsolete by the time they hit the market. Baya Systems is resolute in delivering foundational software, an industry-first, grounds-up fabric solution for future-proof multi-cluster and multi-chiplet designs, and a methodology that takes out the guesswork. I firmly believe that Baya unlocks the merchant chiplet market that is expected to grow to $107 billion by 2033.”
Baya Systems was founded by Kumar, an ex-Intel Fellow and former founder of Netspeed Systems; Dr. Eric Norige, and Joji Philip, who were also key contributors at Netspeed Systems. It is backed by leading investors Matrix and Intel Capital, and is led by Silicon Valley semiconductor veterans with extensive experience in processing and systems, who have driven important initiatives at AMD, ARM, Apple, Intel, Meta, and other leading processor companies.
“When we invest, we look for key market gaps, disruptive technologies that address them, and teams that have a compelling vision and execution muscle and the hunger to achieve it,” said Stan Reiss, general partner, Matrix Partners. “Baya tops all of them for a market that is desperate for solving the scale and chiplet problem with a technology that not just fills the gap but unleashes disruptive innovation, and a proven team that has had a consistent out-sized success in entrepreneurial and high-growth settings.”
The company makes its public debut at DAC 2024, Booth No. 2446, at Moscone West in San Francisco June 23-27.
About Baya Systems
Baya Systems is accelerating the next wave of foundational chiplet-based, high-performance and modular semiconductor systems technologies to accelerate intelligent compute everywhere. Baya Systems was named for the Baya bird, aka the weaver, renowned for constructing cohesive nests from various materials. This approach mirrors Baya Systems’ integrated and efficient solutions from diverse components, and its mission to allow best-of-breed compute, communication and I/O components to be used together with the promise of improving performance, yield, reusability/composability and cost of development. Baya Systems is backed by leading investors Matrix Partners and Intel Capital. For more information visit https://bayasystems.com.
Chairman of the Board is Tenstorrent’s CEO Jim Keller.
Baya Systems emerges from stealth with chiplet interconnect - update
Baya Systems has emerged from stealth with an interconnect tool for chiplet and complex system on chip (SoC) designs.
www.eenewseurope.com
Baya Systems emerges from stealth with chiplet interconnect
Technology News | June 20, 2024By Nick Flaherty
Baya Systems has emerged from stealth with an interconnect tool for chiplet and complex system on chip (SoC) designs.
“What we feel we bring to the table is a more software driven development process,” Nandan Nayampally, chief commercial officer of Baya Systems tells eeNews Europe. “We consider this to be the first really focussed fabric for AI.”The company has executive from Intel, Netspeed Systems, ARM, Brainchip, AMD and Nuvia and is chaired by microprocessor expert Jim Keller, who is also CEO of AI chip developer Tenstorrent. It is backed by Matrix and Intel Capital.
“We focus on the data driven generation of IP with both static and dynamic microarchitectural analysis at runtime,” said Nayampally. “When you do complex systems, the devil is in the detail and system fabric is not that easy.”
The WeaveIP provides components to build a unified fabric that has an efficient, scalable transport architecture that maximizes performance and throughput, while minimizing latency, silicon footprint and power. This supports standard protocols such as CHI, ACE5-Lite, AXI5 and extendable to others including CXL.
The WeaverPro tool supports the SoC designer from initial specification all the way to post-silicon tuning. This uses the WeaveIP to produce a unified mesh fabric approach to generating layer protocols on top of the fabric without the need for gaskets that translate the protocols and the bottlenecks that come with this and slow down the performance.
“The transport is common so you can customise that for the QoS or debug protocols and build protocols on top.”
This comes from the software-driven analysis of the design that can configure up to eight virtual channels across the chip at runtime.
“What we do with our software is very efficient cache memory analysis, get accurate partitioning and caching, and a fabric component that generates a correct by construction physical design. We have two main flavours, where you can define your own protocol and one with multicast for AI designs,” he said.
“We can optimise the bandwidth and reduce the wires and logic to use those wires efficiently for optimising for latency and bandwidth, with up to 3GHz in a 4nm process.”
The fabric is customisable at runtime with APIs so you can tune the parameters for efficiency. “In general the flexibility we have put in helps overall with the reduction in silicon footprint and power and that comes from having an accurate understanding of the data movement,” he said.
The fabric is designed for inside the chip and the chiplet, and Baya will work with interconnect schemes such as Eliyan’s Bunch of Wires and UCIe.
“We stop at the die boundaries but what we end up doing outside of that is the software understands chiplet boundaries and can optimise across chiplet boundaries. So it’s a chiplet-ready network, as various things need to be built into the network to make it easier to use in chiplets,” he said.
“Our first partner is Blue Cheetah. They do the link layers, and once we understand their wires we can optimise and allow API tuning in the future as well,” said Nayampally
“The semiconductor industry is at an inflection point in how to overcome the widening gap between memory performance and the processing needs of AI,” said Dr. Sailesh Kumar, CEO at Baya Systems.
“These challenges are overwhelming the industry with design complexity, energy costs, and systems that are obsolete by the time they hit the market. Baya Systems is resolute in delivering foundational software, an industry-first, grounds-up fabric solution for future-proof multi-cluster and multi-chiplet designs, and a methodology that takes out the guesswork. I firmly believe that Baya unlocks the merchant chiplet market that is expected to grow to $107 billion by 2033.”
www.bayasystems.com
Baya Systems Introduces New Technology to Transform and Accelerate Intelligent Computing
Baya Systems Introduces New Technology to Transform and Accelerate Intelligent Computing Software and IP addresses system design complexity, performance, scalability and Time to Market of SoCs and chiplets for emerging applications. Santa Clara, CALIF. – June 20, 2024 – Baya Systems today...
bayasystems.com
Go to...
Baya Systems Introduces New Technology to Transform and Accelerate Intelligent Computing
Software and IP addresses system design complexity, performance, scalability and Time to Market of SoCs and chiplets for emerging applications.
Santa Clara, CALIF. – June 20, 2024 – Baya Systems today emerged from stealth mode to announce its software-driven IP technology portfolio designed to accelerate complex single-die and multi-die SoC designs. These innovations bolster the emerging chiplet economy and enable unprecedented scale for large-scale compute and AI processing.
Baya Systems technology simplifies the development process and reduces the risk, empowering designers to rapidly analyze, develop, optimize and deploy these complex systems. This enables highly energy-efficient data movement in single-die designs that can support over 4 terabyte/second throughput in a complex CPU cluster, culminating in multi-petabyte/second throughput in multi-chiplet designs for high-end AI installations.
With the exponential growth of computing requirements for artificial intelligence, best-in-class silicon vendors have consistently tried to scale performance efficiently by integrating various processors, including CPUs, GPUs, and neural network accelerators, into intelligent compute systems. This has led to a substantial challenge of efficient data movement across these different processors, and increasingly complex system and application software development. Baya Systems focuses on delivering hyper-efficient data movement that can be customized with efficient hardware-based coherency, correctness, and robustness to accelerate these platforms for applications across industries such as AI acceleration, data center, networking infrastructure, automotive and IoT.
“The rapid scaling in compute needed to support AI is bottlenecked by scaling silicon, memory, storage, and the increasingly huge amounts of data; requiring increasingly complex SoCs and chiplets,” said Kevin Krewell, Principal Analyst at TIRIAS Research. “The industry desperately needs a holistic way to design, analyze, and build intelligent fabrics to address this, and Baya seems to have the right ingredients to really drive the market forward.”
Baya Systems tackles the challenges of system design complexity, performance guarantees, high costs, and shrinking market windows in the SoC and chiplet industries. Its WeaverPro™ software platform supports the SoC designer from initial specification all the way to post-silicon tuning. Its WeaveIP™ provides components to build a unified fabric that has an extremely efficient, scalable transport architecture that maximizes performance and throughput, while minimizing latency, silicon footprint and power. Combined with advanced features for reliability and safety, this empowers designers to analyze, architect, customize, optimize and deploy complex SoCs and chiplets.
Baya’s solution is unique for the following reasons:
- Software-driven architecture exploration helps optimize design to achieve performance guarantees based on built-simulator.
- Engine to generate representative workloads from traffic specification.
- Best-in-class, flexible network that can achieve 3GHz in a 4-nanometer process technology.
- Algorithmic optimization that supports reuse and minimizes silicon and power footprints without compromising performance.
- Industry’s first IP to offer multi-level cache coherency for single/multi-die systems, radically reducing costs of coherency across these large-scale systems.
- Customizable protocol and multicast capabilities for advanced AI and CPU acceleration that support petabyte-level throughput.
- Correct-by-construction design generation that radically reduces risk of failure.
- WeaveIP supports standard protocols such as CHI, ACE5-Lite, AXI5 and extendable to others including CXL.
- Physically aware flow with modularity and tiling support for ease of implementation
“The semiconductor industry is at an inflection point in how to overcome the widening gap between memory performance and the processing needs of AI,” said Dr. Sailesh Kumar, CEO at Baya Systems. “These challenges are overwhelming the industry with design complexity, energy costs, and systems that are obsolete by the time they hit the market. Baya Systems is resolute in delivering foundational software, an industry-first, grounds-up fabric solution for future-proof multi-cluster and multi-chiplet designs, and a methodology that takes out the guesswork. I firmly believe that Baya unlocks the merchant chiplet market that is expected to grow to $107 billion by 2033.”
Baya Systems was founded by Kumar, an ex-Intel Fellow and former founder of Netspeed Systems; Dr. Eric Norige, and Joji Philip, who were also key contributors at Netspeed Systems. It is backed by leading investors Matrix and Intel Capital, and is led by Silicon Valley semiconductor veterans with extensive experience in processing and systems, who have driven important initiatives at AMD, ARM, Apple, Intel, Meta, and other leading processor companies.
“When we invest, we look for key market gaps, disruptive technologies that address them, and teams that have a compelling vision and execution muscle and the hunger to achieve it,” said Stan Reiss, general partner, Matrix Partners. “Baya tops all of them for a market that is desperate for solving the scale and chiplet problem with a technology that not just fills the gap but unleashes disruptive innovation, and a proven team that has had a consistent out-sized success in entrepreneurial and high-growth settings.”
The company makes its public debut at DAC 2024, Booth No. 2446, at Moscone West in San Francisco June 23-27.
About Baya Systems
Baya Systems is accelerating the next wave of foundational chiplet-based, high-performance and modular semiconductor systems technologies to accelerate intelligent compute everywhere. Baya Systems was named for the Baya bird, aka the weaver, renowned for constructing cohesive nests from various materials. This approach mirrors Baya Systems’ integrated and efficient solutions from diverse components, and its mission to allow best-of-breed compute, communication and I/O components to be used together with the promise of improving performance, yield, reusability/composability and cost of development. Baya Systems is backed by leading investors Matrix Partners and Intel Capital. For more information visit https://bayasystems.com.
AARONASX
Holding onto what I've got
Here is hoping!
9to5google.com
Report: Google's switch to TSMC with Tensor G5 will unsurprisingly bring 3nm to Pixel
After a few generations with Samsung, Google is set to switch to TSMC for Tensor in 2025. Unsurprisingly, a new...
9to5google.com
Obviously it is a mistake!
SharesForBrekky
Regular
Even Brainchip's HQ has entered stealth mode
Who says they don't play hardball:
https://news.bloomberglaw.com/ip-law/google-settles-ai-chip-design-suit-that-had-sought-billions
Google Settles AI-Chip Suit That Had Sought Over $5 Billion
20240125https://news.bloomberglaw.com/ip-law/google-settles-ai-chip-design-suit-that-had-sought-billions
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Space Cadet
Regular
Happens every quarter prior to quarterly. No significant revenue it goes back down. Just waiting for the quarterly that brings in the revenue so can head higher.
SC
JoMo68
Regular
Have we ever established (or discussed) whether we have a relationship with MediaTek?
Bravo
If ARM was an arm, BRN would be its biceps💪!
Chiplets, chiplets everywhere!
And today Alphawave Semi just announced the successful tape-out of the industry's first off-the-shelf multi-protocol I/O connectivity chiplet on TSMC's 7nm process.
www.electropages.com
What I find interesting is that in an article I posted previously #83,885 on neuromorphic engineering, Tony Chan Carusone, CTO at of Alphawave Semi comments on how good neuromorphic computing is at performing computations so efficiently.
One wonders if this leaves room for AKIDA to be incorporated in their chiplets?
Oh, and here's a screen-shot from their website!
awavesemi.com
Rob Telson also "liked" this AlpaWave Semi post about chiplets in April 2023.
And today Alphawave Semi just announced the successful tape-out of the industry's first off-the-shelf multi-protocol I/O connectivity chiplet on TSMC's 7nm process.
Off-the-shelf chiplet for HPC and AI iinfrastructure
Latest News from the Electronics Industry - Electropages
What I find interesting is that in an article I posted previously #83,885 on neuromorphic engineering, Tony Chan Carusone, CTO at of Alphawave Semi comments on how good neuromorphic computing is at performing computations so efficiently.
One wonders if this leaves room for AKIDA to be incorporated in their chiplets?
Oh, and here's a screen-shot from their website!
The Era of Specialized Silicon - Alphawave Semi
Alphawave Semi Custom Silicon has custom designed products to fit a wide variety of industry needs. .
awavesemi.com
Rob Telson also "liked" this AlpaWave Semi post about chiplets in April 2023.
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Chiplets, chiplets everywhere!
And today Alphawave Semi just announced the successful tape-out of the industry's first off-the-shelf multi-protocol I/O connectivity chiplet on TSMC's 7nm process.
Off-the-shelf chiplet for HPC and AI iinfrastructure
Latest News from the Electronics Industry - Electropages
What I find interesting is that in an article I posted previously #83,885 on neuromorphic engineering, Tony Chan Carusone, CTO at of Alphawave Semi comments on how good neuromorphic computing is at performing computations so efficiently.
One wonders if this leaves room for AKIDA to be incorporated in their chiplets?
View attachment 65177
Oh, and here's a screen-shot from their website!
View attachment 65180
The Era of Specialized Silicon - Alphawave Semi
Alphawave Semi Custom Silicon has custom designed products to fit a wide variety of industry needs. .
View attachment 65181
View attachment 65184
Rob Telson also "liked" this AlpaWave Semi post about April 2023.
View attachment 65185
... and Akida is compatible across the range of ARM processors:
https://awavesemi.com/chiplets/
The Benefits of Chiplets
Chiplets reduce the total die cost at the tradeoff of more complete packaging and manufacturing. Chiplets are at their most cost effective for large die with little redundancy, making favorable heterogenous integrations of application-specific chiplets. On next generation processes, the cost savings will continue to increase; chiplets can save up to 35% of cost of the larger die.Arm Compute Chiplet
High-performance Arm® Neoverse™ Compute Cluster – high-performance compute chiplet for artificial intelligence/machine learning (AI/ML), high-performance compute (HPC), data center and 5G/6G networking infrastructure applications- Arm Neoverse Class Compute Cluster
- High-speed PCIe links
- UCIe Die-to-Die interconnect
- High-performance memory
They are a rather large partner of arm and Nvidia.
MediaTek Reinvents The Smart Car, With Help From Partner Nvidia
Last year, MediaTek announced it is collaborating with Nvidia to incorporate the AI leader’s technology into the next-gen automotive.
www.forbes.com
MediaTek
MediaTek is the market leader in developing innovative systems-on-chip (SoC) for mobile devices, home entertainment, connectivity, and IoT products.
www.arm.com
In addition to that, they stand to lose a lot of business to us, once we find our commercialisation feet, probably as much as Nvidia.
Also, there have been multiple likes from Rob on Mediatek posts over the past 3 years. That's about the extent of it as far as i know
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Bravo
If ARM was an arm, BRN would be its biceps💪!
Alphawave Semi was in the process of acquiring SiFive's business unit (OpenFive) around the same time we partnered with SiFive. May also be something of interest or maybe nothing.
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Bravo
If ARM was an arm, BRN would be its biceps💪!
Chiplets, chiplets everywhere!
And today Alphawave Semi just announced the successful tape-out of the industry's first off-the-shelf multi-protocol I/O connectivity chiplet on TSMC's 7nm process.
Off-the-shelf chiplet for HPC and AI iinfrastructure
Latest News from the Electronics Industry - Electropages
What I find interesting is that in an article I posted previously #83,885 on neuromorphic engineering, Tony Chan Carusone, CTO at of Alphawave Semi comments on how good neuromorphic computing is at performing computations so efficiently.
One wonders if this leaves room for AKIDA to be incorporated in their chiplets?
View attachment 65177
Oh, and here's a screen-shot from their website!
View attachment 65180
The Era of Specialized Silicon - Alphawave Semi
Alphawave Semi Custom Silicon has custom designed products to fit a wide variety of industry needs. .
View attachment 65181
View attachment 65184
Rob Telson also "liked" this AlpaWave Semi post about chiplets in April 2023.
View attachment 65185
This chap, Tony Chan Carusone (CTO at of Alphawave Semi) who commented above on how good neuromorphic computing is, also commented on a recent announcement of an expanded collaboration between Samsung and Alphawave.
No mention of neuromorphic computing in the Samsung announcement below however, it's interesting to note the partnership between the two companies.
Alphawave Semi Expands Partnership with Samsung Foundry to Further Drive Innovation at Advanced Semiconductor Nodes - Alphawave Semi
Accomplished executive brings depth of experience in semiconductor operations and financial governance
awavesemi.com
I think it's also pretty interesting that Alphawave Semi identifies "neuromorphic computing" on their Key Technologies chart, however they do not appear, unless I'm mistaken, to have any IP partners currently offering neuromorphic technology. Yet.
Partnerships - Alphawave Semi
Our partnerships include Manufacturing and EDA Partners, Ecosystem Partners, IP Partners, SW Tools & OS Partners, Cloud Partners, and Foundry Partners.
awavesemi.com
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