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M_C

Founding Member
@Diogenese can I get an opinion on this pretty please?


In traditional computing systems, calculations are usually performed by constantly transferring data between off-chip memory and processors. For AI workloads, though, there’s a far higher computational requirement, as they generally require large amounts of data. The more AI is infused into application workloads, the more critical it is to have an efficient system where both the general-purpose CPU cores and AI cores are tightly integrated on the same chip.
 
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The other thing I wondered was what would NASA be worth in $$$ to us, it's not like they're going to need millions of chips are they?
It will be hard to quantify. The value sits not so much in the units sold but more in the absolute validation it brings. What higher level of approval could you hope for than having your new disruptive tech being adopted by NASA. The critical risks and harsh environment NASA works within demand nothing but the absolute best in terms of technology, reliability and functionality. I cant think of another company or brand that is more well know for pushing the limits of technology and humankind.
 
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Build-it

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The other thing I wondered was what would NASA be worth in $$$ to us, it's not like they're going to need millions of chips are they?

It would look good on our logo board to start with and a household name.

The post from FF re nasa & Sifive makes sense, the more I read re Sifive the more I like even blind Freddy can see that.

Edge Compute.
 

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I'll agree on the kudos element...but recon space x and Elon would do better for kudos in this day and age.
Wtf nasar doing for 'humanity' they going to grow vegies in space to feed the needy ? 🤔
Perhaps you misinterpreted what I was trying to say, my point was with regards to "pushing the limits of humankind" by this I mean redefining what is possible by us as a species. That coupled with the harsh environment and extreme conditions of space travel demands the harshest of testing and highest level of conformity of any material or technology prior to adoption.

In saying all that, I dont disagree that Tesla would bring its own level of Kudos. So why settle for one... I would be more than happy to have both join us!
 
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Esq.111

Fascinatingly Intuitive.
As a reward for our good behaviour I have just brought over from the NASA thread the following extracts from an SBIR software contract which Rocket had linked and challenged me to highlight anything of interest. Well the following is my take on what was interesting about this SBIR.

It is in my opinion pretty amazing stuff when you consider they mention Loihi and True North in the full knowledge that they cannot meet the specified requirements under COTS and SWaP. (PS: Somewhere I read something about Brainchip and open sourced hardware recently.) The link to the full document is at the end.
My opinion only DYOR
FF

AKIDA BALLISTA

DESCRIPTION: Conventional computing architectures are running up against a quantum limit in terms of transistor size and efficiency, sometimes referred to as the end of Moore’s Law. To regain our competitive edge, we need to find a way around this limit. This is especially relevant for small size, weight, and power (SWaP)-constrained platforms. For these systems, scaling Von Neumann computing becomes prohibitively expensive in terms of power and/or SWaP.Biologically inspired neural networks provide the basis for modern signal processing and classification algorithms.

Implementation of these algorithms on conventional computing hardware requires significant compromises in efficiency and latency due to fundamental design differences. A new class of hardware is emerging that more closely resembles the biological neuron model, also known as a spiking neuron model; mathematically describing the systems found in nature and may solve some of these limitations and bottlenecks. Recent work has demonstrated performance gains using these new hardware architectures and have shown equivalence to converge on a solution with the same accuracy [Ref 1].The most promising of the new class are based on Spiking Neural Networks (SNN) and analog Processing in Memory (PiM) where information is spatially and temporally encoded onto the network. It can be shown that a simple spiking network can reproduce the complex behavior found in the neural cortex with significant reduction in complexity and power requirements [Ref 2]……

“It is recommended to use open source languages, software, and hardware when possible.”…

PHASE III:
Refine algorithms and test with hardware. Validate models with data provided by Naval Air Warfare Center (NAWC) Aircraft Division (AD)/Weapons Division (WD). Transition model to the warfare centers. Development of documentation, training manuals, and software maintenance may be required.Heavy commercial investments in machine learning and artificial intelligence will likely continue for the foreseeable future. Adoption of hardware that can deliver on orders of magnitude in SWaP performance for intelligent mobile machine applications is estimated to be worth 10^9-10^12 global dollars annually.) Provide the software tools needed to optimize the algorithms and hardware integration. This effort would be a significant contribution to this requirement. Industries that would benefit from successful technology development include automotive (self-driving vehicles), personal robots, and a variety of intelligent sensors.

KEYWORDS: Spiking Neural Network, Neuromorphic Computing, Modeling, Convolution Neural Network, Analog Memory, Processing in Memory

https://www.sbir.gov/node/1696107
Evening Fact Finder ,

Cheers for the highlights , I particularly liked the 10^9 to 10^12 projected market .

Would I be correct in assuming this is $10,000,000,000.00
To
$10,000,000,000,000.00
Addressable market.

The latter sounds goooooood.

Thankyou for all your work, Priceless, and great work fellow chippers & chippets with all the reasearch contributed .

I have been a little distracted of late , added 40m squared to my back garden shed. She absorbed 30 tones of cement & half of BHPs steel output .
Almost completed.

Very much looking foward to having one job , Watching the market, in real time.

Keep up the great work all.

Regards,
Esq.
 
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Diogenese

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I'm still learning but should know by now that it's definately AKIDA doing the heavy lifting.. I need to study what cortex is all about and what a MPU is.

So this merger with Si5 create a cortex to rival arms so that Arms won't be needed or does arm have over arching IP they both need.?

So the Risc-v gives up too 300x efficiency power and speed how much more will AKIDA add ?

algorithms. The table below shows power and performance boost from adding a custom extension to execute these algorithms. The boost ranges from a 20-fold performance speedup to a 300-fold power savings. The development flow to add custom extensions to achieve these performance gains is made possible by new generation of design automation tools.

With Custom ExtensionFIR FilterCRC323DES
Speedup20X>140x>300X
Power Efficiency30X>240X>300X
For the developer to profile the application, tools such as the RISC-V reference model and Simulator from Imperas Software Ltd. can be used to explore options for optimization and identify candidate instructions that could be accelerated with dedicated hardware. The developer can then use a tool such as the Andes Custom Extension (ACE) to create an instruction to accelerate the target function. Using the Imperas
Hi Alfie,

Cortex is an ARM trade mark.

RISC = Reduced Instruction Set Computer. There have been several versions of RISC.

The processor architecture for a RISC processor is arranged to implement the RISC instructions. By way of example, you can't run 64-bit programs on 32-bit processors very well.

https://en.wikipedia.org/wiki/Reduced_instruction_set_computer

In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer in order to realise a task. Unlike the instructions given to a complex instruction set computer (CISC), with a RISC computer, a task might require more instructions (code) in order to realise a task, because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular, implementing an instruction pipeline may be simpler given simpler instructions.[1]

The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a load/store architecture in which the code for the register-register instructions (for performing arithmetic and tests) are separate from the instructions that grant access to the main memory of the computer. The design of the CPU allows RISC computers few simple addressing modes[2] and predictable instruction times that simplify design of the system as a whole.

The conceptual developments of the RISC computer architecture began with the IBM 801 project in the late 1970s, but these were not immediately put into use. Designers in California picked up the 801 concepts in two seminal projects, Stanford MIPS and Berkeley RISC. These were commercialized in the 1980s as the MIPS and SPARC systems. IBM eventually produced RISC designs based on further work on the 801 concept, the IBM POWER instruction set architecture, PowerPC, and Power ISA. As the projects matured, many similar designs, produced in the late 1980s and early 1990s, created the central processing units that increased the commercial utility of the Unix workstation and of embedded processors in the laser printer, the router, and similar products
.
...
Since 2010 a new open source instruction set architecture (ISA), RISC-V, has been under development at the University of California, Berkeley, for research purposes and as a free alternative to proprietary ISAs. As of 2014, version 2 of the user space ISA is fixed.[24] The ISA is designed to be extensible from a barebones core sufficient for a small embedded processor to supercomputer and cloud computing use with standard and chip designer defined extensions and coprocessors. It has been tested in silicon design with the ROCKET SoC which is also available as an open-source processor generator in the CHISEL language.
..
Some CPUs have been specifically designed to have a very small set of instructions – but these designs are very different from classic RISC designs, so they have been given other names such as minimal instruction set computer (MISC) or transport triggered architecture (TTA).

RISC architectures have traditionally had few successes in the desktop PC and commodity server markets, where the x86-based platforms remain the dominant processor architecture. However, this may change, as ARM-based processors are being developed for higher performance systems.[36] Manufacturers including Cavium, AMD, and Qualcomm have released server processors based on the ARM architecture.[37][38] ARM is further partnered with Cray in 2017 to produce an ARM-based supercomputer.[39] On the desktop, Microsoft announced that it planned to support the PC version of Windows 10 on Qualcomm Snapdragon-based devices in 2017 as part of its partnership with Qualcomm. These devices will support Windows applications compiled for 32-bit x86 via an x86 processor emulator that translates 32-bit x86 code to ARM64 code.[40][41] Apple announced they will transition their Mac desktop and laptop computers from Intel processors to internally developed ARM64-based SoCs called Apple silicon; the first such computers, using the Apple M1 processor, were released in November 2020.[42] Macs with Apple silicon can run x86-64 binaries with Rosetta 2, an x86-64 to ARM64 translator.[43]

Outside of the desktop arena, however, the ARM RISC architecture is in widespread use in smartphones, tablets and many forms of embedded device. While early RISC designs differed significantly from contemporary CISC designs, by 2000 the highest-performing CPUs in the RISC line were almost indistinguishable from the highest-performing CPUs in the CISC line
.[44][45][46]


ARM uses RISC-4. The hardware to run RISC-4 is at present some way ahead of the RISC-V hardware of Si5 who are still in the early stages as a company. However, incorporating an Akida NN may help bridge the gap and give Si5 THE EDGE.

This slide shows Si5's plans for the use of NN acceleration in their higher end multi-core processors.

1649319549191.png

Si5 would have been in the EAP, so will have a good understanding of how Akida can be combined into their NN plans.
 
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Diogenese

Top 20
Evening Fact Finder ,

Cheers for the highlights , I particularly liked the 10^9 to 10^12 projected market .

Would I be correct in assuming this is $10,000,000,000.00
To
$10,000,000,000,000.00
Addressable market.

The latter sounds goooooood.

Thankyou for all your work, Priceless, and great work fellow chippers & chippets with all the reasearch contributed .

I have been a little distracted of late , added 40m squared to my back garden shed. She absorbed 30 tones of cement & half of BHPs steel output .
Almost completed.

Very much looking foward to having one job , Watching the market, in real time.

Keep up the great work all.

Regards,
Esq.
Hi Esq,

You are too noughty.
10^3 = 1000.
 
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Quatrojos

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Diogenese

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@Diogenese can I get an opinion on this pretty please?


In traditional computing systems, calculations are usually performed by constantly transferring data between off-chip memory and processors. For AI workloads, though, there’s a far higher computational requirement, as they generally require large amounts of data. The more AI is infused into application workloads, the more critical it is to have an efficient system where both the general-purpose CPU cores and AI cores are tightly integrated on the same chip.

I'm not a fan of the Z16
1649322631806.png
 
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Esq.111

Fascinatingly Intuitive.
Hi Esq,

You are too noughty.
10^3 = 1000.
Evening Diogenese,

Thankyou for correcting me.

so

$1,000,000,000.00 to $1,000,000,000,000.00 addressable market.

I'm a little deflated & liqured.

Cheers

Regards,
Esq .
 
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Slade

Top 20
I can’t say as a still shot of a face that features throughout does not set the scene but if you are watching it for entertainment you are in the wrong theatre. LOL

It is the underlying principles. It was actually shown as a training aid at Duntroon about fifty years ago. That is how I became aware of it initially.

FF.
You are right, moving footage is more interesting. Starring Hotcrapper
 
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AusEire

Founding Member. It's ok to say No to Dot Joining
Lol.

What a joke the crapper is

View attachment 3875
The Crapper is such a joke. My post was moderated in 30 seconds.
That's hilarious! I was able to literally abuse one of the downrampers the other day and called him a c***. It's still up 😂😂 The moderators are a joke. That place will soon be nothing. TSE is the future 🔥
 
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Diogenese

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Good to know (y)(n)
Hi FUB (nee MC),

iBM have a lot of MemRistor-type NN patents, eg:

WO2010133399A1 ELECTRONIC LEARNING SYNAPSE WITH SPIKE-TIMING DEPENDENT PLASTICITY USING PHASE CHANGE MEMORY

1649323879621.png



US2010223220A1 ELECTRONIC SYNAPSE

1649323981968.png


... but more recently they seem to have become aware of digital NNs:

WO2014080300A1 NEURAL NETWORK

1649324667121.png



Funnily enuf, IBM talk about "digital neurons', but they don't describe them in this patent.

However, there is a picture of one with accompanying description in:
US2014180987A1 TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A NEURAL NETWORK

1649325129688.png


[0010] FIG. 2 is a block diagram of a time-division multiplexed neurosynaptic module, in accordance with an embodiment of the invention;

A processor 150 that multiplexes computation and control logic for n neurons 11 is an n-way processor 150 , wherein n is an integer value. The computation circuit 170 of an n-way processor 150 is time-multiplexed n times
.


1649325246683.png
[0019] FIG. 8 illustrates an example computation circuit of a multi-way parallel processor device, in accordance with an embodiment of the invention;

This is a synchronous circuit. Akida is asynchronous.

But they continue to flirt with memRistors.

PS: The fan reference was a visual pun.
 
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Getupthere

Regular

I know this is not akida however this new facial recognition system will be in the all new Mazda cx60 which will be on sale late this year in Australia.

Mazda achieved its best year in sales since 1994, with a total of 332,756 vehicles sold in 2021.

Now Renesas will release their products with akida IP later this year.

Guess who there customers are.

Globally, Japan's Honda Group sold about 4.5 million automobiles in its 2021 fiscal year

In 2021, Nissan worldwide car sales increased by a moderate 0.9% to 4,065,014 compared to 4,029,166 vehicles sold in 2021.

Toyota captured 10.5 million sales in 2021, which represented a 10.1 per cent jump on its 2020 result.

Go BRN!
 
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alwaysgreen

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That's hilarious! I was able to literally abuse one of the downrampers the other day and called him a c***. It's still up 😂😂 The moderators are a joke. That place will soon be nothing. TSE is the future 🔥
They don't care about abuse. They only care when you show they are wrong. Clearly being manipulated by the mods (who are the ones downramping and shorting the stock).
 
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alwaysgreen

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I know this is not akida however this new facial recognition system will be in the all new Mazda cx60 which will be on sale late this year in Australia.

Mazda achieved its best year in sales since 1994, with a total of 332,756 vehicles sold in 2021.

Now Renesas will release their products with akida IP later this year.

Guess who there customers are.

Globally, Japan's Honda Group sold about 4.5 million automobiles in its 2021 fiscal year

In 2021, Nissan worldwide car sales increased by a moderate 0.9% to 4,065,014 compared to 4,029,166 vehicles sold in 2021.

Toyota captured 10.5 million sales in 2021, which represented a 10.1 per cent jump on its 2020 result.

Go BRN!
20,000,000 cars. Only 1 Akida in each at $15 = A shit tonne!
 
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What many do not take notice of is every NASA SBIR application requires the applicant to state what additional markets beyond the NASA use case they see their solution finding traction.

The Vorago application complied and put a very large number on the commercial opportunity beyond NASA for a successfully hardened AKD1000 chip.

The thing is you need to look at NASA with a stereoscope not a magnifying glass as it is a three D opportunity.

A company wins an SBIR and supplies it’s product to NASA which effectively tells the market this product has been proven and tested to the highest standard.


If you are in the market for an extreme edge revolutionary technology the comfort of NASA validation cannot be over stated.

In the interim NASA has paid the applicant to develop the product and then bought the resultant product.

If we go specifically to Brainchip it has a product that will having been assessed by NASA is already being considered by the US Military. This being a successful consideration then Brainchip’s AKIDA technology product will be needed in the 100’s of millions of use cases across all the potential offered by NASA/DARPA as well as the commercial market.

The politics surrounding this promotion of applicants by NASA is found in its historical need to continually justify to the American people the value of having a space program. The greater the economic success of a NASA applicant the better.

My opinion only DYOR
FF

AKIDA BALLISTA
 
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wilzy123

Founding Member
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wilzy123

Founding Member
Lol i just put that song in the music chsnnchsnne
Thats nice. I think hotcrapper misses you.
 
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