In this section, we give a brief summary of state-of-the-art neuromorphic processors. Several research groups from academia and industry have reported very promising implementations of neuromorphic processors. For example, a mixed-signal, multi-core neuroprocessor called dynamic neuromorphic asynchronous processor (DYNAP) was reported which combines the efficiency of analog computational circuits with the robustness of asynchronous digital logic for communications [96] and implemented in 180 nm CMOS process. Thakur et al. introduced an improved version called DYNAP with scalable and learning devices (Dynap-SEL) containing additional features implemented in a 28 nm FDSOI (Fully Depleted Silicon-On-Insulator) process [97]. There are four cores with each containing 16 × 16 analog neurons where each neuron has 64 programmable (4-bit) synapses. There is an additional fifth core containing 1 × 64 analog neurons, 64 × 128 plastic synapses (on-line learning capability), and 64 × 64 programmable synapses.
Two other famous neuroprocessors named ’SpiNNaker’ [26] and ’BrainScaleS’ [23] came out of human brain project (HBP) in Europe [98]. The SpiNNaker, developed by researchers at the University of Manchester, contains more than one million parallel ARM processors which are used to model one billion spiking neurons with biologically-realistic synaptic connections in real time [26]. On the other hand, BrainScaleS is a mixed-signal neuromorphic system at wafer-scale with upwards of 40 million synapses and 180 thousand neurons that has been developed from a research collaboration between the University of Heidelberg and the Technische Universita ̈t Dresden [23].
TrueNorth, a famous neuroprocessor from IBM [24], consists of 4096 neurosynaptic cores with 1 million digital neurons and 256 million synapses tightly interconnected by an event-driven routing infrastructure consuming 65 mW power. They also introduced a novel hybrid asynchronous–synchronous model along with new CAD tools for the design and verification. Another prominent neuroprocessor is Loihi from Intel [27] which contains 128 neuromorphic cores, three ×86 processor cores, and four communication interfaces that extend the mesh in four directions to other chips. Each neuromorphic core has 1024 primitive spiking neural units grouped into sets of neuronal trees. The mesh protocol can support up to 16,384 chips and 4096 on-chip cores using hierarchical addressing. Loihi introduced several novel features, such as hierarchical connectivity, dendritic compartments, synaptic delays, and programmable synaptic learning rules.
A family of dynamically adaptive neural processors have been developed by the TENNLab neuromorphic research group at in University of Tennessee. The first one is called DANNA (dynamic adaptive neural network array) [99] which was initially designed for FPGA and later adapted for 130 nm CMOS ASIC (application specific integrated circuit) implementation. An improved version called DANNA2 was introduced in 2018 with improved network density, achievable clock speeds, and training convergence rate [100]. In parallel, a mixed-signal extension known as memristive dynamic adaptive neural network array (mrDANNA), was later developed that utilized memristor devices in the synapses to improve the efficiency of the neuromorphic system [101] with an online learning methodology called synchronous digital long term plasticity (DLTP). Currently, TENNLAB is working on developing a convergent and flexible architecture as part of a reconfigurable and very efficient neuromorphic system or RAVENS [102].
8
Name Dynap-SEL [97] FPAA [103] BrainScaleS [23] TrueNorth [24] SpiNNaker [26] mrDANNA [101] Loihi [27]
Operation Mixed Analog Digital Digital Digital Mixed Digital
power/energy
260 pJ/spike
< 1μW
10 pJ/transmit
60 mW
100 nJ/neuron + 43 nJ/synapse
22.31 pJ/neuron/spike + 0.48 pJ/synapse/spike 81 pJ/neuron + 120 pJ/synapse
V. ALGORITHM AND ARCHITECTURE
timescale ns ms to s ns
ns
ns
ns to μs ns
on-chip learning STDP
STDP Configurable plasticity none Configurable DLTP Configurable STDP
TABLE II: State-of-the-art Neuromorphic Processors
https://arxiv.org/pdf/2310.09692.pdf
Unfortunately Brainchip not even mention in this Neuromorphic Published paper. Are they living under a rock?
However there are many familiar terms used among these other competitors. I wonder if we have something in our patent protection against these? STDP for instance…
www.eu.socionext.com
hevodata.com
chip ....... though could well help confuse us further .
www.cnbc.com
from Up Above
tealcom.io
www.synsense.ai
