BRN Discussion Ongoing

Rach2512

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Sorry if already posted
 
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Rach2512

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Spreading the word.




D&R as a Web Portal

D&R launched its industry leading web and B2B portal (www.design-reuse.com) for the IP/SoC market in 1997. Today, with 15,000 IP/SOC product descriptions updated daily and an average of 70,000 absolute unique visitors to the site per month (source: Google Analytics), plus Design & Reuse News email broadcasts enjoyed by 35,000 subscribers and its client to IP and service provider matching capabilities, the Design-Reuse.com site provides important services to the IP industry. More recently D&R launched a sister site, www.dr-embedded.com, to address the interest in resources specifically required for the Embedded design space such as software, OS’s, and platforms.
 
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charles2

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MDhere

Regular
Interest

Plumerai also vocal on LinkedIn just now about the M85 and tagging in Renesas and Arm execs
View attachment 32100

This is very significant. I've revisited the embedded conf featuring Renesas and have posted link here with special mention when he says the 1st on earth... (and we all know Brainchip is with the Cortex family including M85 combined!) and conference being held in this very topic May 9.
The Renesas guy is very excited and i don't blame him 😀😀😀 love it love it love it
 
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Another mention of Brainchip:
 
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This is very significant. I've revisited the embedded conf featuring Renesas and have posted link here with special mention when he says the 1st on earth... (and we all know Brainchip is with the Cortex family including M85 combined!) and conference being held in this very topic May 9.
The Renesas guy is very excited and i don't blame him 😀😀😀 love it love it love it

I think this is some ARM vector acceleration called Helium, he briefly mentions it in the video, sadly not Brainchip....
 
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Tothemoon24

Top 20

Now Enhanced for Safety-critical Automotive Applications​



Cortex_2D00_M23-image.jpg_2D00_2700x1518x2.jpg



Laura Armitstead
April 5, 2023


Incredible innovation is driving the technological shift in vehicles, but there is one thing that must continue to be front and center: the safety of drivers, passengers, and road users. Arm technology has been under the hood for decades and we understand that automotive technologies require processors suited to safety applications that still address the wider power, cost, area, and software considerations of our partners. In this blog, we talk about the recently updated Arm Cortex-M23 processor, which now features enhanced capabilities for automotive applications.
Arm Cortex-M processors are area and power efficient, making them a great fit for a broad range of automotive applications. They are also easy to program, as a large ecosystem of software and tools supports them, and they have a simple programmer’s model. Building safety relevant products can be costly, in both time and effort. To speed up time-to-market for automotive partners, Arm has added even more functional safety capabilities to M-profile cores and certified them with an external assessor for ISO 26262. This elevates the safety starting position for chip designers, easing their safety efforts, and allowing them to focus on other areas. With the release of the updated Cortex-M23, the full portfolio of Cortex-M processors, including Cortex-M85and Cortex-M55, now include leading-edge functional safety features.

The updated Cortex-M23​

Within all vehicles, there are small, single functions that need cost-effective compute solutions. It is in this space that achieving functional safety within the constraints of low power and area is an ongoing challenge. Cortex-M23 is Arm’s most power efficient v8-M Cortex-M CPU and has been updated to include functional safety features that elevate diagnostic coverage for safety critical applications. Examples include ultrasonic parking sensors for parking assistance, tire pressure and rain sensors, lighting and LED controllers for headlights and brake lights, to name a few. Many of these applications require ASIL B, a medium level of integrity, for which the updated Cortex-M23 could be the perfect fit with its single core safety mechanisms.

An area and power efficient solution​

ASIL B level normally requires the detection of 90 percent of single point faults, and that transient faults are addressed, if applicable. You can learn more about ASIL B in our Cortex-M55: Functional safety ready blog, where we outline the different ASIL levels defined by ISO 26262. Transient faults are tricky in that they can go easily undetected. This is because a particle could hit an area of the design and flip one bit of data, but it is not long before the next bit of data is written to that location, overwriting the flipped bit.
The updated Cortex-M23 adds transient fault protection to address this issue for applications that are constrained by area and cost where a dual-core lockstep approach would be undesirable. It also adds interface protection for the detection of faults at the boundary of the CPU, removing more work at the system level for chip designers. The use of a Software Test Library for Cortex-M23 would also provide more diagnostic coverage of permanent faults, complementing the internal core safety mechanisms. Moreover, these additional features have no impact on benchmark performance compared to the previous Cortex-M23, making adoption simpler.

Not forgetting ASIL D​

For applications where dual-core lockstep is required, Arm has now delivered a new Dual Core Lockstep application note specific to Cortex-M23. This document gives guidance on how to implement this feature on Cortex-M23 and what to watch out for when implementing it. This might also be the right solution for an ASIL B application if your design can support the additional die area and power that comes with a dual lockstep implementation.

Cortex-M23, a reminder​

Cortex-M23, which was first launched in 2016, implements the ARMv8-M architecture, bringing more instructions and system level features. Those experienced with Cortex-M0+ see many of the same energy-efficiency benefits in Cortex-M23. These benefits include deep-sleep modes and sleep-on-exit, which make it ideal for low-power applications. With more vehicles becoming electrified, Tier 1s must develop solutions that can meet the power needs of OEMs, for which Cortex-M processors are well suited.
Developers can design more robust and safer systems using the optional MPU (Memory Protection Unit). The MPU can be programmed to define regions of memory, assign certain attributes and access permissions depending on the task. When an application attempts to access a region of memory for which it has not been authorized, the MPU can trigger a fault exception.

A full functional safety portfolio​

Cortex-M23, Cortex-M55, and Cortex-M85 are a scalable collection of Cortex-M processors that can support a wide range of automotive applications, from low power consumption to high-performance needs. They share a common architecture for ease of code portability. A broad ecosystem supports them, including safety certified software and tools, to simplify development for the next generation of vehicles.
 
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AARONASX

Holding onto what I've got
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Boab

I wish I could paint like Vincent
The website is looking pretty flash these days👍👍
arm.jpg
 
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Teksun mentioned Brainchip was working with Toshiba, Cisco and (I forget the third company) but they amended their release and Brainchip said they didn't release the approved message.

Since then, Cisco has been on the radar, especially when our CEO has mentioned telecom, but not handsets or 4g, but potentially conference calling devices and networking.
All our ears are pricked for mentions of Ai and Cisco.
Don’t forget this too WebEx is in the new Mercedes OS

Post in thread 'BRN Discussion Ongoing'
https://thestockexchange.com.au/threads/brn-discussion-ongoing.1/post-280032
 
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Really good podcast by Sean.
Any key reason the podcast finished at 15min 55sec and there is 12mins of nothing beyond this point? Some editing by BRN or forgot to press the stop button? 🤪
Yes it was a SNN podcast.. There were was no activity after 15min 55secs therefore no activity.. 🤣
 
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Dhm

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IloveLamp

Top 20
Must watch.

BMWs latest promo.....looks very cool.

It is my opinion akida is one of the key enablers

Dyor


Screenshot_20230505_085531_YouTube.jpg
 
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equanimous

Norse clairvoyant shapeshifter goddess
Really good podcast by Sean.
Any key reason the podcast finished at 15min 55sec and there is 12mins of nothing beyond this point? Some editing by BRN or forgot to press the stop button? 🤪
Youtube cut it stating NDA
 
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Learning

Learning to the Top 🕵‍♂️

Technology analysis and market type, architecture, packaging, application, and industry vertical, in addition to calculations for the costs associated with leading-edge AI chips.​

The global AI chips market will grow to US$257.6 billion by 2033, with the three largest industry verticals at that time being IT & Telecoms, Banking, Financial Services and Insurance (BFSI), and Consumer Electronics. Artificial Intelligence is transforming the world as we know it; from the success of DeepMind over Go world champion Lee Sedol in 2016, to the robust predictive abilities of OpenAI’s ChatGPT, the complexity of AI training algorithms is growing at a startlingly fast pace, where the amount of compute necessary to run newly-developed training algorithms appears to be doubling roughly every four months. In order to keep pace with this growth, hardware for AI applications is needed that is not just scalable – allowing for longevity as new algorithms are introduced, while keeping operational overheads low – but is also able to handle increasingly complex models at a point close to the end-user. A two-pronged approach, to handle AI in the cloud and at the edge, is required to fully realize an effective Internet of Things.


Learning 🏖
 
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Bravo

If ARM was an arm, BRN would be its biceps💪!
This is a great example of how neuromorphic architecture can benefit society environmentally, economically, scientifically and medically. This extract was taken from Mattias Nilsson's research paper Event-Driven Architectures for Heterogeneous Neuromorphic Computing Systems.



Extract Only

Screen Shot 2023-05-05 at 9.13.27 am.png

 
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jtardif999

Regular
Exciting news from Plumerai! 🔥 You can now test Plumerai’s People Detection right here in your browser. 😱 Click below and witness the accuracy of our tiny AI model running with your webcam. Rest assured, your privacy is protected. We do not capture any images and everything stays on your PC. How does it work? Normally we compile our models for CPUs and NPUs, but here we’ve compiled them for WebAssembly, which runs in the browser. Give it a try and see for yourself what kind of accuracy we can achieve with our tiny models! 🚀

Plumerai People Detection will run locally in your browser, with no involvement from the cloud. This is how we preserve your privacy.
Your videos or images are not transmitted, not stored, and not shared with Plumerai. For full details, see our privacy policy.

This exact same AI model runs on tiny chips.​

And that’s why we can deploy AI in devices where others can’t.
We are running an extremely tiny AI model in your browser. There’s no involvement from the cloud, so preserving your privacy. It’s so small and so efficient that we can run the exact same AI model on tiny and low-cost chips. That’s how we enable our customers to run Plumerai People Detection on nearly any device, while providing the same highly-accurate detections that you are seeing here in your browser.

SINGLE CORE ARM CORTEX-A72 @ 1.5 GHz​

29 frames⁄s

WITH A TINY FOOTPRINT​

2.3 MB
Plumerai People Detection runs on Arm Cortex-A, x86, and RISC-V CPUs and on $1 Arm Cortex-M and ESP32-S3 microcontrollers. It can also easily be adapted to leverage AI accelerators.

View attachment 35627
Unfortunately this tech will work against BRNs success with this particular use case (depending on how effective it actually is when used with CPUs). Since it’s software based my guess is it would be easy and cheap to deploy without the costs of upgrading equipment etc. It would obviously be optimal if it were used with Akida, but companies would be less likely to spend the money on embedding Akida when they don’t have to in this instance. But on the other hand, a company like Renesas that already has a two node Akida implementation could be the real winner here. 😎
 
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Taproot

Regular
Teksun mentioned Brainchip was working with Toshiba, Cisco and (I forget the third company) but they amended their release and Brainchip said they didn't release the approved message.

Since then, Cisco has been on the radar, especially when our CEO has mentioned telecom, but not handsets or 4g, but potentially conference calling devices and networking.
All our ears are pricked for mentions of Ai and Cisco.
Linaro
( Think Linux )
Linaro co-maintains the ARM Ecosystem
 
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