Probably posted before , my apologies for spreading more SPAM
Cortex-M85: Enabling safety and boosting flexibility and performance even higher
Dimos Rossidis
7 minute read time.
Released in 2022,
Arm Cortex-M85 has been the highest performing CPU in the Cortex-M portfolio. With scalar performance of more than 6 CoreMark/MHz and 3 DMIPS/MHz, Cortex-M85 has been an excellent fit for high-performance IoT, industrial control and automotive applications. At the same time, due to the implementation of the
Arm Helium Technology, Cortex-M85 demonstrates significantly higher machine learning (ML) and digital signal processing (DSP) capabilities than
Cortex-M7. These benefits make Cortex-M85 a very powerful core for microcontroller (MCU) applications where compute performance is key.
The deterministic operation (due to the Tightly Coupled Memories – TCMs) combined with the high compute capabilities make Cortex-M85 an ideal CPU choice for applications where intelligence is being increasingly pushed to the edge. The processor can enable endpoint devices to not only sense and collect data, but also perform a significant amount of computation, and even execute sophisticated ML algorithms on the CPU within a predictable time frame.
There is also a rising demand for this high performance to address new workloads, and be deployed in safety critical applications where the IP needs to be capable of managing and detecting any faults.
This is why we are delighted to announce that at the end of 2022, Arm released Cortex-M85 revision 1. Cortex-M85 r1 introduces the following:
- Important functional safety features. The functional safety support helps in achieving both ASIL D/SIL 3 and, with lower hardware overhead, ASIL B/SIL2 safety requirements.
- The implementation of Arm Custom Instructions (ACI). ACI is a key feature that increases software flexibility by allowing user-defined instructions, and can also boost performance even higher by enabling accelerators that are tightly coupled with the datapath of the processor.
- Improved streaming performance, which is very important for workloads making increased memory accesses.
Cortex-M85: The first safety ready high-performing Cortex-M
Automotive and industrial control products rely on safety standards, which ensure that each individual electrical or electronic component integrated into the product meet functional safety requirements.
Arm’s Safety Ready portfolio is based on the ISO 26262 (for automotive) / IEC 61508 (for industrial) safety standards. ISO 26262 / IEC 61508 are risk-based standards that aim to address potential hazards caused by the malfunction of these systems. They provide frameworks and guidelines that should be followed during the development of a system and determine Automotive Safety Integrity Level (ASIL) / Safety Integrity Level (SIL) based on a risk assessment analysis.
In the automotive industry, Cortex-M85 can be used for diverse applications with varying safety needs. Some applications demand ASIL D for the highest safety integrity levels. One example are the high torque traction motors, where the significant growth in vehicle electrification has led to demand for more actuation across the vehicle. Other applications demand a lower safety integrity level, such as ASIL B. This is the case for vehicle cockpit displays incorporating cluster information.
Safety Ready logo
Cortex-M85 r1 is equipped with multiple safety features to address these varying safety needs. To meet the demands of ASIL D single point fault detection, Cortex-M85 can be implemented as a Dual Core Lockstep (DCLS) pair of processors, with one copy of the logic used to detect faults in the other. Although a DCLS configured Cortex-M85 can be deployed to achieve the diagnostic coverage needed for lower safety levels, the processor also supports mechanisms where this can be achieved with greater power and area efficiency. This is done through a combination of self-test functions and the ability of the Cortex-M85 r1 to detect Transient Faults. Self-testing through the use of
Arm Software Test Libraries (STLs) can be used to detect permanent faults in the logic by periodically and flexibly executing the STLs on the processor. The flops in the design can be protected with the Transient Fault Protection (TFP) feature, which is able to identify a single bit fault in groups of flops. The cache memories are protected against faults with Error Correcting Code (ECC) providing Single Error Correction Double Error Detection (SECDED). In combination, these mechanisms can help deliver a more efficient solution for applications with ASIL B requirements.
Furthermore, Cortex-M85 r1 provides hardware which enables the in-field and on-line testing of the internal processor memories with Memory Built-in Self-Test (MBIST). A software Programmable MBIST Controller (PMC) can be integrated into the design to access, exercise, and test these memories while the processor continues to execute. Protection is also offered to transactions into and out of the processor by using interface protection. This is an extension to
Arm’s Advanced Microcontroller Bus Architecture (AMBA) protocol and guards the transactions with parity protection against undetected corruption in the transaction between the core and the receiving interface, like the interconnect.
Arm has performed safety assessments on many of our Cortex-M processors using independent third-party assessors that issue certificates for the IP. Cortex-M85 will follow this same path. It has a safety package which provides information and evidence for partners to use in the development of products with safety requirements. For Cortex-M85, this planned assessment will evaluate both its systematic development and diagnostic capabilities for ASIL D and ASIL B.
Boosting flexibility and performance with Arm Custom Instructions
The compute and processing requirements in recent embedded systems have increased significantly. This is especially true in the IoT space where the market is pushing the compute requirements to the endpoint devices (such as smart sensors/cameras, agricultural drones, etc.) of the IoT system.
The continuous need for higher processing capabilities results in the implementation of high performing processors, like Cortex-M85. At the same time, this raises the need for custom hardware accelerators, and the necessity for easy integration to the existing CPU. Accelerators are treated as memory-mapped IPs, through an internal coprocessor interface. Legacy Cortex-M CPUs, like
Cortex-M33, implement such an interface, allowing the hardware accelerators to be closely integrated to the processor, and reducing the latency in data and instruction transfers. However, some applications require the execution of specialized data processing functions on the CPU, so that they can operate directly on general-purpose registers.
This need is addressed through
Arm Custom Instructions (ACI), with Cortex-M85 – alongside
Cortex-M55 – also implementing this feature. ACI allows chip designers to include custom defined data processing instructions directly on the Cortex-M processor, and enables the users to implement their own instructions by using the existing Cortex-M85 hardware.
Diagram showing how ACI combines with Cortex-M85 to meet the requirements for acceleration
Moreover, with ACI on Cortex-M85, the user does not have to turn to alternative architectures to implement a desired instruction encoding. Instead, this can now be done on CPUs that are based on the Arm architecture, with Cortex-M85 being the first high-performing microcontroller to provide this option. Through ACI, the user is given the power to innovate within the proven Arm architecture, while maintaining the ecosystem advantages of the Cortex-M CPUs.
All of the above makes ACI a powerful feature, as it provides a performance boost for low-latency instructions, easy integration with an existing software ecosystem and scalability across Cortex-M processors. ACI is the perfect fit for applications using specialized bit field processing, trigonometric functions, and image pixel manipulations. It can also be applied to accelerate frequently used data processing functions.
Upgraded streaming performance
Cortex-M85 r1 has an enhanced datapath to deliver significantly higher streaming performance compared to the legacy Cortex-M processors. Specifically, Cortex-M85 r1 delivers about 2x higher streaming performance than Cortex-M55 and Cortex-M7 using LMbench. This enhancement is very important for any workload that requires continuous memory access across the AXI interface. For example, large footprint code that requires external memory access.
Cortex-M85 based products to be brought in the market soon
Arm’s partners have endorsed Cortex-M85 and already announced their plans to bring their M85-based devices to the market in the next year. For example,
Renesas announcedthat it will demonstrate the first working silicon based on Cortex-M85.
Through Cortex-M85 r1, Arm partners can now use all the enhanced features for improved performance and safety, and apply them in the IoT, automotive and industrial markets through their next-generation MCU products.
While it doesn't bother me, I too am of the understanding that Sean expected a rise in revenue by the next AGM. I will be disappointed if we don't see $$$ and he is upbeat and doesn't give good reasons for the lack (if indeed there is) of revenue. He will go down in my books as a typical CEO who won't take responsibility. But we'll see his response with or without revenue leap, it will be character defining IMO.
