Static discharge has always been an issue with CMOS ICs until they are bedded down on a circuit board and installed in equipment. It's just that when you get to these dimensions these problems become more extreme. There is probably a square law relationship, so that at 4 nm the static problem is 4 times worse than at 8 nm.They don't sound like they're going to be very robust chips do they..
I guess, as long as you're not out with what ever devices they're in, on a dry windy day, wearing wool or polyester and make sure you're always wearing your rubber boots, there shouldn't be a problem
I don't know if static electricity will affect the "good" chips, once made..
https://www.circuitstoday.com/how-to-protect-cmos-devices-and-ics#:~:text=Another effect of static damage is that the,voltage discharges that can be generated during handling.