They don't sound like they're going to be very robust chips do they..
I guess, as long as you're not out with what ever devices they're in, on a dry windy day, wearing wool or polyester and make sure you're always wearing your rubber boots, there shouldn't be a problem
I don't know if static electricity will affect the "good" chips, once made..
Now here's a company that's resting on their laurels:
Silicon Frontline Technologies
US7669152B1 Three-dimensional hierarchical coupling extraction
Priority: 20070213
A
pparatus, systems, and methods are provided for processing integrated circuit chip design. A three-dimensional Monte Carlo random-walk process may be applied to a cell in a hierarchical description of the layout of the chip to extract information regarding the cell. The information may include coupling resistance, capacitance, inductance, or combinations thereof. A neighborhood of the cell may be built and data correlated to the neighborhood may be stored. Such a technique may be applied from a bottom level to a top level of the hierarchical description of the chip layout.
It's a system for identifying parasitic or leakage paths in an IC.
It's really the AI equivalent of Anil.
The patent has only a few years to run, and it's only filed in USA. They don't seem to have any other patents.
The inventors were also inventors of this nearly expired patent:
US6577992B1 Transistor level circuit simulator using hierarchical data
NASSDA CORP
D
evice-level circuit simulation is an important step in microelectronic circuit design. Through such simulation, the functionality of a circuit may be validated and performance of the circuit may be predicted before the circuit is physically fabricated. The application of existing simulation tools such as SPICE, however, is limited to the simulation of small subcircuit blocks, typically less than 100,000 transistors, due to their memory capacity and performance limitations.
M
ethods and apparatus for generating a hierarchical representation of a circuit include obtaining a netlist corresponding to the circuit, the circuit including a plurality of subcircuits. A hierarchical representation of the circuit is then generated from the netlist, the hierarchical representation including the plurality of subcircuits arranged among a plurality of levels of the hierarchical representation. Each one of the plurality of subcircuits has an associated subcircuit definition. In addition, each of a plurality of subsets of the subcircuits share a same subcircuit definition, where memory storage for the same subcircuit definition is shared by the subcircuits in each of the subsets. Moreover, each one of the plurality of subcircuits has a dynamic voltage state. Selected ones of the subcircuits in each of the plurality of subsets share a same dynamic voltage state, where memory storage for the same dynamic voltage state is shared by the subcircuits in each of the selected ones of the plurality of subsets. Once generated, the hierarchical representation may be used during simulation of the circuit to reduce the number of computations required.
There does not seem to be a tie-up between Nassda and Silicon Frontline Tech.
Silicon Frontline:
https://www.siliconfrontline.com/company/management/
Yuri Feinberg, CEO
P
rior to SFT, Yuri founded Nassda, the developer of HSIM, which grew to a public company with revenues of $50M. Before Nassda, Yuri was involved at EPIC, where his contributions enabled EPIC to be the leader in circuit simulation.
Clearly Yuri and Andrei TCHERNIAEV are circuit testing whizz kids, but they seem to have let the R&D slip. They must be relying on confidentiality to protect their secrets.
As Moore's law bumps into the buffers, their services will come more and more into demand.