Hi FF,
Thanks for the reminder of the 2021 AI Field Day videos with Anil. They are well worth reviewing.
The AI field Day 2021 was 27-28 May 2021. A lot of water under the bridge since then, and Akida is the better for it.
BrainChip Completes Testing Production Version of the Akida Chip
Latest iteration has been optimized for lower power consumption than the original engineering samples
Aliso Viejo, Calif. – 8 November, 2021 –
BrainChip Holdings Ltd (ASX: BRN), (OTCQX: BCHPY), a leading provider of ultra-low power, high-performance artificial intelligence technology and the world’s first commercial producer of neuromorphic AI chips, today confirmed that functionality and performance testing of the AKD1000 production chips has been completed, which
showed better performance than the original engineering samples.
As part of the continued development of its Akida™ Neuromorphic System-on-Chip (NSoC), BrainChip tested a production version of its AKD1000 chip with several neural network applications, including object classification, keyword spotting and spiking neural networks. T
he improved performance and lower power consumption results were achieved through a better layout and some minor design changes to the design, which were recognized after previous testing of earlier engineering samples.
Well worth re-watching these videos (I always find Ray Lucchesi's questions elicit useful information):
https://brainchipinc.com/videos/ BrainChip: The Future is Bright 28 May 2021.
0:55 - Joshua Fidel - any car mfrs using your chip now - are evaluating lidar datasets for them. This chip not ASIL compatible - IP embedded into chip so car mfrs/component suppliers can do ASIL qualification.
2:40 Marc - defence contractors - yes neuromorphic -learn on-chip - NASA - MetaTF & chip
3:30 Demetrios Brinkmann - best applications - beneficial - image
14:40 - RL - USB chip - $49 to $69
https://brainchipinc.com/videos/ Making Edge AI Possible
@8:40 Ray Lucchesi - neuromorphic analog
10:30 - Mark - low power micro W to milli W
1615 RL - RL - same resolution convert to spikes. difference between frames DVS event domain - no matrix multiplication
https://brainchipinc.com/videos/ The BrainChip Advantage
@ 8:45: Ray Lucchesi -one and a half nodes (6 NPUs) can do key word spotting
@ 15:00: Ray Lucchesi asks about LSTM - Anil LSTM is coming next generation - - new neuron model I&F plus copy
17:30: MetaTF deep learning SNN - CNN2SNN
MetaTF
simulator maps to Akida - will include LSTM - activity based quantization - 4-bit, 2-bit, 1-bit.
ASIL is ISO standard, so it's very comprehensive, but car makers and component suppliers will be fully aware of the requirements.
ISO ASIL
https://www.techdesignforums.com/pr...g-iso-26262-certification-with-asil-ready-ip/
Since high-end ADAS SoCs are mainly used for safety-critical applications, they must meet the stringent requirements of the ISO 26262 functional safety standard, as must all the companies which supply components or semiconductor IP that go into the overall design.
Best practices in applying the ISO 26262 functional safety standard
ISO 26262 describes four automotive safety integrity levels (ASILs) – A, B, C and D – which in turn define the various processes that automotive development teams must use to meet the standard. One key task is to minimize a design’s susceptibility to random hardware failures by defining the functional requirements, using a rigorous development process and taking steps to ensure that safety features can mitigate those hardware failures. Design teams working to meet ISO 26262 standards must also systematically analyze the status of any component or system throughout the supply chain.
The ISO 26262 certification process must start from the very beginning of development process, and include multiple steps to complete the certification process, some of which are detailed below.
Failure mode effect and diagnosis analysis
A failure mode effect and diagnosis analysis (FMEDA) report is generated by development teams to provide all the information about their adherence to ISO 26262 from a functional safety perspective. The FMEDA report must be concurrently reviewed by design and verification engineers. Safety managers monitor the development process, milestones and product reviews to ensure that all the documentation and traceability requirements defined by ISO 26262 are completed throughout the SoC development flow, at both the IP and full-chip level.
ASIL ratings provide evidence of compliance, and define both design targets and a rating assessment at the end of the development flow. The ASIL ratings range from A, for the lowest integrity requirements, to D, for the highest integrity requirements. Let’s go through an example to illustrate a safety-critical product development flow.
Example of a development flow
Figure 1 shows a standard development flow for an IP or SoC. The core architecture and specification goes through RTL design and implementation, and is then verified and validated in hardware and software in the final prototypes.
Since high-end ADAS SoCs are mainly used for safety-critical applications, they must meet the stringent requirements of the ISO 26262 functional safety standard, as must all the companies which supply components or semiconductor IP that go into the overall design.
Making this flow into one that complies with ISO 26262 means starting at the beginning, with the core architecture and specification definition, as shown in Figure 2. This assures the SoC or IP is designed to meet the required functional safety level.
View attachment 4330
Architects and designers write safety plans to help manage the execution of safety activities, as shown in Figure 3. Safety plans help verify that the development flow meets the safety goals, implements the safety features specified in the safety plan, and measures the impact of any possible product failures and the design’s reaction to those failures in terms of functional safety. These plans are also reviewed by a safety manager.
The entire process up to this point is documented and delivered as Work Products, which include key milestones, resources, and the various implementation processes needed to meet functional safety requirements.
View attachment 4331
FMEDA forms a critical part of the safety plan, providing a detailed report encompassing various steps and analysis, as shown in Figure 4. It must include a fault injection analysis for both permanent and transient faults, so their impact can be assessed. FMEDA also considers all the possible failure and distribution modes to understand how the product will behave if a failure occurs and what sort of diagnostics the product implements to identify and communicate such failures to the system.
The ISO 26262 standard also provides guidelines on how to implement safety features to counter various failure modes. It does this by looking at the possible failures, based on the SoC architecture. This failure assessments analysis also applies to IP that is integrated into the SoC. The various mitigation functions and their effectiveness, as recommended by the standard, are shown in Table 1.
| Diagnostic Type | Effectiveness |
| HW Redundancy | High – 99% |
| Configuration Register Test | High – 99% |
| EDC* on Memory | High – 99% |
| Combination of Timeout monitoring, Frame Counter & information Redundancy | High – 99% |
| Self-test supported by Hardware | High – 99% |
| Multi-bit HW redundancy | Medium – 90% |
| Timeout monitoring | Medium – 90% |
| Frame Counter | Medium – 90% |
| Information Redundancy | Medium – 90% |
| Parity Bit – per Word | Low – 60% |
Table 1: Various mitigation functions and their effectiveness as defined by ISO 26262 (Source: Synopsys)
...
Additional automotive requirements
In addition to meeting ISO 26262 functional safety requirements, automotive SoC development teams and the rest of the supply chain must adhere to automotive reliability and quality requirements.
Any product, including IP, for an automotive application must meet the automotive reliability requirements defined by AEC-Q100. Automotive reliability is measured in terms of parts-per-million failure rates under various operating modes and at much higher temperatures than those used to test consumer products. For this reason, SoC and IP designers define temperature profiles which their products are designed and tested to meet, based on the target application. IP providers must make sure their IP meets the reliability targets of the application, which means exploring how a transistor or electromigration analysis might be affected by the defined temperature profile*. IP providers must work with foundries to ensure that any special automotive rules are applied to their design.
[* Our experience with radiation hardening will come in useful in automotive ASIL certification. Also Socionext/TSMC will be familiar with automotive requirements, as will Valeo, Mercedes, Renesas, MegaChip ... ]
Any product development in the automotive supply chain must also meet automotive quality management requirements. In addition to having quality manuals and compliance reports, developers also need to create a design failure mode and effect analysis report that says that the SoC and its components meet the automotive quality management requirements.
Conclusion
Designing automotive SoCs and supporting components such as semiconductor IP demands a parallel functional safety assurance process, rooted in a deep understanding of the requirements of ISO 26262, AEC-Q100 and subtle technical details such as the impact of various temperature profiles on the potential failure modes of an IP block. A safety manager is also necessary to keep the safety process on track, ensure the documentation is kept up to date, and to review safety plans for unexplored failure modes. The overall process should include design and verification engineers throughout.
embeddedvisionsummit.com
www.edge-ai-vision.com
