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Burlingame, CA – December 11, 2023– Quadric® today announced that representatives from the company will be at the Consumer Electronics Show (CES) in Las Vegas, January 9-12, 2024. Email meetquadric@quadric.ioto set up a meeting to learn how a general-purpose neural processing unit (GPNPU) solves the challenge of needing to artificially partition code between an NPU and a digital signal processor (DSP) and/or central processing unit (CPU).
“Because it’s fully programmable, our GPNPU runs all types of machine learning networks, including classical backbones, vision transformers, and large language models,” stated Steve Roddy, Quadric’s Chief Marketing Officer. “One architecture for ML inference plus pre-and-post processing greatly simplifies SoC hardware design and software programming. Porting new artificial intelligence (AI) and ML code is quick and efficient. No hardware changes are required, which means no silicon re-spins are required.”
Quadric’s processor architecture uniquely combines the best attributes of C++ programmability – the ability to run any ML model – with the performance efficiency of NPU accelerators found in many first-generation SoCs in the market today. But unlike inflexible accelerators that force silicon respins when complex new models such as Llama2 are invented, Chimera cores are fully programmable. Chimera GPNPUs run any model. All of the model – all of the layers. No removal of problematic layers. No partitioning. No forcing the data scientist to convert convolutions to adhere to the limited subset of conv types supported in hardware. Any model, any network, any operator.
