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MDhere

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A little while back i put up a demographic impact of the published article "A review of Current Neuromorphic Approaches for Vision, Auditory and Olfactory Sensors" Well i had a little bit of time to check it and well Mumbai was alot of hits (interesting Tata Office is in Mumbai) and Palo Alto, California got some (Home of Tesla, before move to Texas) Just saying....... 😁 co-incidence..maybe... 😁
 

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White Horse

Regular
Has anyone heard of Imec? The technology sounds very similar to ours????





https://www.imec-int.com/en
/Imec Builds World’s First Spiking Neural Network-Based Chip for Radar Signal Processing
Press release

Imec Builds World’s First Spiking Neural Network-Based Chip for Radar Signal Processing​

Flagship use-case includes the creation of a smart, low-power anti-collision radar system for drones that identifies approaching objects in a matter of milliseconds
LEUVEN (Belgium), April 28, 2020 — Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, today presents the world’s first chip that processes radar signals using a spiking recurrent neural network. Mimicking the way groups of biological neurons operate to recognize temporal patterns, imec’s chip consumes 100 times less power than traditional implementations while featuring a tenfold reduction in latency – enabling almost instantaneous decision-making. For example, micro-Doppler radar signatures can be classified using only 30 μW of power. While the chip’s architecture and algorithms can easily be tuned to process a variety of sensor data (including electrocardiogram, speech, sonar, radar and lidar streams), its first use-case will encompass the creation of a low-power, highly intelligent anti-collision radar system for drones that can react much more effectively to approaching objects.
Artificial neural networks (ANNs) have already proven their worth in a wide range of application domains. They are a key ingredient, for instance, of the radar-based anti-collision systems commonly used in the automotive industry. But ANNs come with their share of limitations. For one, they consume too much power to be integrated into increasingly constrained (sensor) devices. Additionally, ANNs’ underlying architecture and data formatting requires data to undertake a time-consuming journey from the sensor device to the AI inference algorithm before a decision can be made. Enter spiking neural networks (SNNs).
“Today, we present the world’s first chip that processes radar signals using a recurrent spiking neural network,” says Ilja Ocket, program manager of neuromorphic sensing at imec.

Imec’s novel chip was initially designed to support electrocardiogram (ECG) and speech processing in power-constrained devices. Yet thanks to its generic architecture that features a completely new digital hardware design, it can also easily be reconfigured to process a variety of other sensory inputs like sonar, radar and lidar data. Contrary to analog SNN implementations, imec’s event-driven digital design makes the chip behave exactly and repeatedly as predicted by the neural network simulation tools.
Use-case: a smarter, low-power anti-collision system for drones (and cars)
The drone industry – even more than the automotive sector – works with constrained devices (e.g. limited battery capacity) that need to react quickly to changes in their environment in order to appropriately react to approaching obstacles.
“Hence, a flagship use-case for our new chip includes the creation of a low-latency, low-power anti-collision system for drones. Doing its processing close to the radar sensor, our chip should enable the radar sensing system to distinguish much more quickly – and accurately – between approaching objects. In turn, this will allow drones to nearly instantaneously react to potentially dangerous situations,” says Ilja Ocket. “One scenario we are currently exploring features autonomous drones that depend on their on-board camera and radar sensor systems for in-warehouse navigation, keeping a safe distance from walls and shelves while performing complex tasks. This technology could be used in plenty of other use-cases as well – from robotics scenarios to the deployment of automatic guided vehicles (AGVs) and even health monitoring.”
“This chip meets the industry’s demand for extremely low-power neural networks that truly learn from data and enable personalized AI. For its creation, we rallied experts from various disciplines within imec – from the development of training algorithms and spiking neural network architectures that take neuroscience as a basis, to biomedical and radar signal processing and ultra-low power digital chip design. That is where imec really makes a difference,” Kathleen Philips, program director of IoT cognitive sensing at imec, concludes.

I think this statement needs a little more scrutiny.

Imec’s novel chip was initially designed to support electrocardiogram (ECG) and speech processing in power-constrained devices. Yet thanks to its generic architecture that features a completely new digital hardware design, it can also easily be reconfigured to process a variety of other sensory inputs like sonar, radar and lidar data. Contrary to analog SNN implementations, imec’s event-driven digital design makes the chip behave exactly and repeatedly as predicted by the neural network simulation tools.
 
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I think this statement needs a little more scrutiny.

Imec’s novel chip was initially designed to support electrocardiogram (ECG) and speech processing in power-constrained devices. Yet thanks to its generic architecture that features a completely new digital hardware design, it can also easily be reconfigured to process a variety of other sensory inputs like sonar, radar and lidar data. Contrary to analog SNN implementations, imec’s event-driven digital design makes the chip behave exactly and repeatedly as predicted by the neural network simulation tools.
Great pickup WH. Probably too soon for @Diogenese to access the new patent???

It is very suspicious that they have been able to engineer such a dramatic change without external assistance.

My opinion only DYOR
FF

AKIDA BALLISTA
 
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Great pickup WH. Probably too soon for @Diogenese to access the new patent???

It is very suspicious that they have been able to engineer such a dramatic change without external assistance.

My opinion only DYOR
FF

AKIDA BALLISTA
I had a quick look at this website and there is a lot of material there. I think they’re saying they’ve got their own SNN chip but not sure of the quality of it compared to Brainchip. I’m still wading through it so I can’t comment on it until I’ve read it properly and a bit tired to concentrate on it atm.

https://www.imec-int.com/en/reading-room?tags[]=Artificial+intelligence

Surprised Unknown Soldier or similar hadn’t thrown this in our face a year or so ago as competition as it looks to be around for a while so I’m guessing (and have a feeling/recollection) it has been looked at already:




1651319613463.png


Regardless I’m still confident of where we are heading. I’m sure if there was another commercial neuromorphic chip out there since 2020 it would have been brought to our attention a lot earlier!

Cheers.
 
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chapman89

Founding Member
Maybe our German investors can keep an eye out for this, they talk about Mercedes Benz Infotainment and Software in the future 😁


D4816442-D426-4C78-AF26-A188866050D3.jpeg
 
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Great pickup WH. Probably too soon for @Diogenese to access the new patent???

It is very suspicious that they have been able to engineer such a dramatic change without external assistance.

My opinion only DYOR
FF

AKIDA BALLISTA
Hi WH
In looking at the dates these claims come from 2020 yet the already revealed patent discussed by @Diogenese confirms they were using analog.
A bit of poetic licence being employed by IMEC.

My opinion only DYOR
FF

AKIDA BALLISTA
 
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White Horse

Regular
Hi WH
In looking at the dates these claims come from 2020 yet the already revealed patent discussed by @Diogenese confirms they were using analog.
A bit of poetic licence being employed by IMEC.

My opinion only DYOR
FF

AKIDA BALLISTA
Hi FF,
However, this is a black and white statement from their website. Hence either factual or misleading.
It will be interesting to see what our sleuths have to say.
 
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Diogenese

Top 20
Great pickup WH. Probably too soon for @Diogenese to access the new patent???

It is very suspicious that they have been able to engineer such a dramatic change without external assistance.

My opinion only DYOR
FF

AKIDA BALLISTA

Hi FF,

I was caught short on this development by Imec.

Imec are using in-memory computing:
EP3671748A1 IN-MEMORY COMPUTING FOR MACHINE LEARNING

[0009] Operations on multiple stored values in the array going beyond bitwise logic functions can be implemented, in particular reduction operations, including summation, can be obtained by in-memory processing. No dedicated external unit is then needed or this unit may require less performance. This is particularly interesting for binary neural network applications for which the matrix-vector multiplications conventionally carried out by MAC units can be achieved by multiple in-memory XNOR products, followed by a subsequent in-memory summation.

[0047] In-memory processing, in the context of the present invention, refers to a memory structure, such as an array or a plurality of sub-arrays comprising memory cells, which also comprises processing logic or processing functionality on stored data bits. In contrast to near memory computing or conventional memory structures which are not in-memory processing, the requested data is not only read and communicated to an external processing unit, but is already modified or processed as of the moment it is sent out of the memory structure. In exemplary embodiments processing of requested data bits, before communicating the results to peripheral further processing units, may include bitwise Boolean operations such as, but not limited to XOR and/or XNOR multiplication of pairs of requested data bits or addition of one or more requested data bits or intermediate functional results thereof. In-memory processing is highly desirable for fast and energy-efficient computing hardware as it is mitigating the von Neumann bottleneck. Having a processing unit waiting for unprocessed fetched data from memory before it can start processing it is often an inefficient use of the available resources and bandwidth. Therefore, a limiting the amount of raw data communicated to the processing unit and sending (pre-) processed data to the processing unit instead, is providing a more efficient use of the available resources and bandwidth. Whereas near memory computing tries to limit the length of data paths from the memory structure to a nearby processing logic, in-memory processing goes one step further by incorporating the processing logic directly into the memory structure.

1651325026470.png


In-memory computing for 1-bit weights and actuations (SNN) are carried out by simple logic gates and an adder.

The title of the patent refers to learning, but I haven't got to that bit yet, as I need to post this retraction of my earlier post asap.
 
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Diogenese

Top 20
Hi FF,

I was caught short on this development by Imec.

Imec are using in-memory computing:
EP3671748A1 IN-MEMORY COMPUTING FOR MACHINE LEARNING

[0009] Operations on multiple stored values in the array going beyond bitwise logic functions can be implemented, in particular reduction operations, including summation, can be obtained by in-memory processing. No dedicated external unit is then needed or this unit may require less performance. This is particularly interesting for binary neural network applications for which the matrix-vector multiplications conventionally carried out by MAC units can be achieved by multiple in-memory XNOR products, followed by a subsequent in-memory summation.

[0047] In-memory processing, in the context of the present invention, refers to a memory structure, such as an array or a plurality of sub-arrays comprising memory cells, which also comprises processing logic or processing functionality on stored data bits. In contrast to near memory computing or conventional memory structures which are not in-memory processing, the requested data is not only read and communicated to an external processing unit, but is already modified or processed as of the moment it is sent out of the memory structure. In exemplary embodiments processing of requested data bits, before communicating the results to peripheral further processing units, may include bitwise Boolean operations such as, but not limited to XOR and/or XNOR multiplication of pairs of requested data bits or addition of one or more requested data bits or intermediate functional results thereof. In-memory processing is highly desirable for fast and energy-efficient computing hardware as it is mitigating the von Neumann bottleneck. Having a processing unit waiting for unprocessed fetched data from memory before it can start processing it is often an inefficient use of the available resources and bandwidth. Therefore, a limiting the amount of raw data communicated to the processing unit and sending (pre-) processed data to the processing unit instead, is providing a more efficient use of the available resources and bandwidth. Whereas near memory computing tries to limit the length of data paths from the memory structure to a nearby processing logic, in-memory processing goes one step further by incorporating the processing logic directly into the memory structure.

View attachment 5300

In-memory computing for 1-bit weights and actuations (SNN) are carried out by simple logic gates and an adder.

The title of the patent refers to learning, but I haven't got to that bit yet, as I need to post this retraction of my earlier post asap.
IBM still thinks in-memory compute means MemRistors:


In-memory computing could be a significant first step towards non-von Neumann computing. Here the key idea is to perform certain tasks, such as bit-wise operations and arithmetic operations, in memory. We call such a memory unit computational memory, where resistive memory devices, in particular phase-change memory (PCM) devices, could play an important role as building blocks. We have found that, if data is stored in PCM devices, the physical attributes of those devices can be exploited to achieve in-place computation. When organized in a cross-bar array, PCM devices can be used to perform matrix-vector multiplications with very low computational complexity. An application of this concept is the problem of compressed sensing.

Imec uses standard silicon logic gates.
 
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D

Deleted member 118

Guest
@Fact Finder an early morning Sunday read or 2 to go with ya cuppa tea and slice off toast with strawberry jam.








18E2FC4A-5A65-48E6-AD99-69DD756B5863.png

0EAA0898-3D18-4055-99C5-6FD9A61783D1.png

 
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TheFunkMachine

seeds have the potential to become trees.
Afternoon Chippers,

Thought I would try to contribute something to the forum.

Engagements & possible exciting events for the coming month of May.
* I dare say there will be others which I have missed.

1, 12th May, Autosense, Detroit, USA, Anil presenting.

1.1, 12th May, Automotive Tech Virtual Conference,
Kris Carlson presenting.

2, 18th May, Embeded Vision Summit.

3, 24th May, Vorago, Space Tech Expo, RAD Hardened AKIDA ??

4, 24th May, Brainchip Annual General Meeting.
* Everyone needs to make their vote count, we do own a peice of the company.

5, 29th May, International Symposium on Olfaction & Electronic Nose, Aveiro, Portugal, Hossam Haick talking, NANOSE.

& last , but not least, something most if not all Chippers have been waiting on........

6, 30th May, F.D.A.A.A, (American Food & Drug Administration Ammendments Act.), Dianose, Covid detection unit, NCT04476927, Required Report Date .


Looking foward to it.

Big thankyou to all the Super Sluthes, Bloody LEDGENDS.

Regards,
Esq.
That’s a great list Esq!:)
Thanks for putting that together. If I where to add anything to that list I would put the next “this is our mission” podcast with Megachips on there:)

I think it is the 3rd of May :)
 
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Esq.111

Fascinatingly Intuitive.
That’s a great list Esq!:)
Thanks for putting that together. If I where to add anything to that list I would put the next “this is our mission” podcast with Megachips on there:)

I think it is the 3rd of May :)
Morning TFM,

Cheers, just added.

Esq.
 
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D

Deleted member 118

Guest
Afternoon Chippers,

Thought I would try to contribute something to the forum.

Engagements & possible exciting events for the coming month of May.
* I dare say there will be others which I have missed.

1, 3rd May, BRN Podcast, No.16, MegaChips ( BRN Partner), Rob Telson & Doug Fairbaine chew the fat.

2, 12th May, Autosense, Detroit, USA, Anil presenting.

3, 12th May, Automotive Tech Virtual Conference,
Kris Carlson presenting.

4, 18th May, Embeded Vision Summit.

5, 24th May, Vorago, Space Tech Expo, RAD Hardened AKIDA ??

6, 24th May, Brainchip Annual General Meeting.
* Everyone needs to make their vote count, we do own a peice of the company.

7, 29th May, International Symposium on Olfaction & Electronic Nose, Aveiro, Portugal, Hossam Haick talking, NANOSE.

& last , but not least, something most if not all Chippers have been waiting on........

8, 30th May, F.D.A.A.A, (American Food & Drug Administration Ammendments Act.), Dianose, Covid detection unit, NCT04476927, Required Report Date .


Looking foward to it.

Big thankyou to all the Super Sluthes, Bloody LEDGENDS.

Regards,
Esq.
You’ve missed the May 20th off the list and one off the most important events ever.
 
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An workshop coming up with Heinrich Gotzig from Valeo who will be chairing


Topics of interest include, but are not limited to:​

  • event-based sensing,
  • event-based neuromorphic engineering,
  • event-driven
  • vision, event-driven audio,
  • event-based olfactory systems,
  • event-driven robot skin,
  • event-based information processing,
  • event-based motion detection and integration,
  • spiking neural networks,
  • edge computing,
  • address-event representation,
  • visual recognition,
  • depth estimation,
  • real-time algorithms,
  • motion estimation,
  • object tracking,
  • sensor fusion.
See this is being held in Poland. Maybe Anil can attend, take a few AKD1000 chips with him, smuggle then across the border to Ukraine and they can put them in numerous weaponry and put Putin on his arse and then the world can get back to its ordinary malfunctioning chaotic self.

SC
 
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Deleted member 118

Guest
See this is being held in Poland. Maybe Anil can attend, take a few AKD1000 chips with him, smuggle then across the border to Ukraine and they can put them in numerous weaponry and put Putin on his arse and then the world can get back to its ordinary malfunctioning chaotic self.

SC
Close but not close enough
 

Diogenese

Top 20
Hi FF,

I was caught short on this development by Imec.

Imec are using in-memory computing:
EP3671748A1 IN-MEMORY COMPUTING FOR MACHINE LEARNING

[0009] Operations on multiple stored values in the array going beyond bitwise logic functions can be implemented, in particular reduction operations, including summation, can be obtained by in-memory processing. No dedicated external unit is then needed or this unit may require less performance. This is particularly interesting for binary neural network applications for which the matrix-vector multiplications conventionally carried out by MAC units can be achieved by multiple in-memory XNOR products, followed by a subsequent in-memory summation.

[0047] In-memory processing, in the context of the present invention, refers to a memory structure, such as an array or a plurality of sub-arrays comprising memory cells, which also comprises processing logic or processing functionality on stored data bits. In contrast to near memory computing or conventional memory structures which are not in-memory processing, the requested data is not only read and communicated to an external processing unit, but is already modified or processed as of the moment it is sent out of the memory structure. In exemplary embodiments processing of requested data bits, before communicating the results to peripheral further processing units, may include bitwise Boolean operations such as, but not limited to XOR and/or XNOR multiplication of pairs of requested data bits or addition of one or more requested data bits or intermediate functional results thereof. In-memory processing is highly desirable for fast and energy-efficient computing hardware as it is mitigating the von Neumann bottleneck. Having a processing unit waiting for unprocessed fetched data from memory before it can start processing it is often an inefficient use of the available resources and bandwidth. Therefore, a limiting the amount of raw data communicated to the processing unit and sending (pre-) processed data to the processing unit instead, is providing a more efficient use of the available resources and bandwidth. Whereas near memory computing tries to limit the length of data paths from the memory structure to a nearby processing logic, in-memory processing goes one step further by incorporating the processing logic directly into the memory structure.

View attachment 5300

In-memory computing for 1-bit weights and actuations (SNN) are carried out by simple logic gates and an adder.

The title of the patent refers to learning, but I haven't got to that bit yet, as I need to post this retraction of my earlier post asap.

The Imec patent application has been abandoned.
 
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Deleted member 118

Guest
Magik eye must be very close to releasing version 2

 
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I am all in favour of what you are suggesting that Brainchip and AKIDA technology might get called in to assist Aeva but my point was not contrary to this but that AKIDA is not competing with Aeva or any other player in LiDAR Valeo is the one competing and so far it has dominated and leads the market and with AKIDA onboard has taken a quantum leap on every other competitor in this space that does not have the AKIDA technology advantage.

Brainchip is a facilitator not a competitor open to anyone to take on board.

REMEMBER the goal is for Brainchip’s technology to become the default standard - CEO Sean Hehir 2022.

My opinion only DYOR
FF
 
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The Imec patent application has been abandoned.
Just to be clear it is EP3671748A1 IN-MEMORY COMPUTING FOR MACHINE LEARNING that has been abandoned.

Does that then mean IMEC only have as far as we know the original patent for an analog SNN?

Many thanks @Diogenese

My opinion only DYOR
FF

AKIDA BALLISTA
 
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Cyw

Regular
Magik eye must be very close to releasing version 2

I have this robot vacuum but it is pretty dumb in avoiding obstacles. It has to hit the obstacle before changing directions. Ecovacs (Chinese company listed in Shanghai) release the new omni robovac that has LiDAR for smart navigation. Wonder if they are using Magikeye? What AI visual sensor processor is available now other than AKIDA?

Deebot X1-Omni
 
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