BRN Discussion Ongoing

[Fact Finder]

Great pickup WH. Probably too soon for @Diogenese to access the new patent???

It is very suspicious that they have been able to engineer such a dramatic change without external assistance.

My opinion only DYOR
FF

AKIDA BALLISTA

Hi WH
In looking at the dates these claims come from 2020 yet the already revealed patent discussed by @Diogenese confirms they were using analog.
A bit of poetic licence being employed by IMEC.

My opinion only DYOR
FF

AKIDA BALLISTA

 

[White Horse]

Hi WH
In looking at the dates these claims come from 2020 yet the already revealed patent discussed by @Diogenese confirms they were using analog.
A bit of poetic licence being employed by IMEC.

My opinion only DYOR
FF

AKIDA BALLISTA

Hi FF,
However, this is a black and white statement from their website. Hence either factual or misleading.
It will be interesting to see what our sleuths have to say.

 

[Diogenese]

Great pickup WH. Probably too soon for @Diogenese to access the new patent???

It is very suspicious that they have been able to engineer such a dramatic change without external assistance.

My opinion only DYOR
FF

AKIDA BALLISTA

Hi FF,

I was caught short on this development by Imec.

Imec are using in-memory computing:
EP3671748A1 IN-MEMORY COMPUTING FOR MACHINE LEARNING

[0009] Operations on multiple stored values in the array going beyond bitwise logic functions can be implemented, in particular reduction operations, including summation, can be obtained by in-memory processing. No dedicated external unit is then needed or this unit may require less performance. This is particularly interesting for binary neural network applications for which the matrix-vector multiplications conventionally carried out by MAC units can be achieved by multiple in-memory XNOR products, followed by a subsequent in-memory summation.

[0047] In-memory processing, in the context of the present invention, refers to a memory structure, such as an array or a plurality of sub-arrays comprising memory cells, which also comprises processing logic or processing functionality on stored data bits. In contrast to near memory computing or conventional memory structures which are not in-memory processing, the requested data is not only read and communicated to an external processing unit, but is already modified or processed as of the moment it is sent out of the memory structure. In exemplary embodiments processing of requested data bits, before communicating the results to peripheral further processing units, may include bitwise Boolean operations such as, but not limited to XOR and/or XNOR multiplication of pairs of requested data bits or addition of one or more requested data bits or intermediate functional results thereof. In-memory processing is highly desirable for fast and energy-efficient computing hardware as it is mitigating the von Neumann bottleneck. Having a processing unit waiting for unprocessed fetched data from memory before it can start processing it is often an inefficient use of the available resources and bandwidth. Therefore, a limiting the amount of raw data communicated to the processing unit and sending (pre-) processed data to the processing unit instead, is providing a more efficient use of the available resources and bandwidth. Whereas near memory computing tries to limit the length of data paths from the memory structure to a nearby processing logic, in-memory processing goes one step further by incorporating the processing logic directly into the memory structure.

In-memory computing for 1-bit weights and actuations (SNN) are carried out by simple logic gates and an adder.

The title of the patent refers to learning, but I haven't got to that bit yet, as I need to post this retraction of my earlier post asap.

 

[Diogenese]

Hi FF,

I was caught short on this development by Imec.

Imec are using in-memory computing:
EP3671748A1 IN-MEMORY COMPUTING FOR MACHINE LEARNING

[0009] Operations on multiple stored values in the array going beyond bitwise logic functions can be implemented, in particular reduction operations, including summation, can be obtained by in-memory processing. No dedicated external unit is then needed or this unit may require less performance. This is particularly interesting for binary neural network applications for which the matrix-vector multiplications conventionally carried out by MAC units can be achieved by multiple in-memory XNOR products, followed by a subsequent in-memory summation.

[0047] In-memory processing, in the context of the present invention, refers to a memory structure, such as an array or a plurality of sub-arrays comprising memory cells, which also comprises processing logic or processing functionality on stored data bits. In contrast to near memory computing or conventional memory structures which are not in-memory processing, the requested data is not only read and communicated to an external processing unit, but is already modified or processed as of the moment it is sent out of the memory structure. In exemplary embodiments processing of requested data bits, before communicating the results to peripheral further processing units, may include bitwise Boolean operations such as, but not limited to XOR and/or XNOR multiplication of pairs of requested data bits or addition of one or more requested data bits or intermediate functional results thereof. In-memory processing is highly desirable for fast and energy-efficient computing hardware as it is mitigating the von Neumann bottleneck. Having a processing unit waiting for unprocessed fetched data from memory before it can start processing it is often an inefficient use of the available resources and bandwidth. Therefore, a limiting the amount of raw data communicated to the processing unit and sending (pre-) processed data to the processing unit instead, is providing a more efficient use of the available resources and bandwidth. Whereas near memory computing tries to limit the length of data paths from the memory structure to a nearby processing logic, in-memory processing goes one step further by incorporating the processing logic directly into the memory structure.

View attachment 5300

In-memory computing for 1-bit weights and actuations (SNN) are carried out by simple logic gates and an adder.

The title of the patent refers to learning, but I haven't got to that bit yet, as I need to post this retraction of my earlier post asap.

IBM still thinks in-memory compute means MemRistors:

In-memory computing

At IBM Research, we’re inventing what’s next in AI, quantum computing, and hybrid cloud to shape the world ahead.

www.zurich.ibm.com

In-memory computing could be a significant first step towards non-von Neumann computing. Here the key idea is to perform certain tasks, such as bit-wise operations and arithmetic operations, in memory. We call such a memory unit computational memory, where resistive memory devices, in particular phase-change memory (PCM) devices, could play an important role as building blocks. We have found that, if data is stored in PCM devices, the physical attributes of those devices can be exploited to achieve in-place computation. When organized in a cross-bar array, PCM devices can be used to perform matrix-vector multiplications with very low computational complexity. An application of this concept is the problem of compressed sensing.

Imec uses standard silicon logic gates.

 

[Deleted member 118]

@Fact Finder an early morning Sunday read or 2 to go with ya cuppa tea and slice off toast with strawberry jam.

Navigating Emerging Technology and Evolving Threats in the U.S.-Australia Alliance

At a time when regional states see growing instability and are concerned about their place in an increasingly tense region, the U.S.-Australia alliance has an opportunity to lead by example.

www.csis.org

US Navy Expands Role of AI in Maritime Warfare | Warrior Maven: Center for Military Modernization

Surface Navy Building Digital Infrastructure to Harness AI

Surface Navy Building Digital Infrastructure to Harness AI

www.nationaldefensemagazine.org

https://www.cigionline.org/static/documents/no.263.pdf

https://www.gao.gov/assets/gao-22-104765.pdf

The Rise of A.I. Fighter Pilots

Artificial intelligence is being taught to fly warplanes. Can the technology be trusted?

www.newyorker.com

 

[TheFunkMachine]

Afternoon Chippers,

Thought I would try to contribute something to the forum.

Engagements & possible exciting events for the coming month of May.
* I dare say there will be others which I have missed.

1, 12th May, Autosense, Detroit, USA, Anil presenting.

1.1, 12th May, Automotive Tech Virtual Conference,
Kris Carlson presenting.

2, 18th May, Embeded Vision Summit.

3, 24th May, Vorago, Space Tech Expo, RAD Hardened AKIDA ??

4, 24th May, Brainchip Annual General Meeting.
* Everyone needs to make their vote count, we do own a peice of the company.

5, 29th May, International Symposium on Olfaction & Electronic Nose, Aveiro, Portugal, Hossam Haick talking, NANOSE.

& last , but not least, something most if not all Chippers have been waiting on........

6, 30th May, F.D.A.A.A, (American Food & Drug Administration Ammendments Act.), Dianose, Covid detection unit, NCT04476927, Required Report Date .


Looking foward to it.

Big thankyou to all the Super Sluthes, Bloody LEDGENDS.

Regards,
Esq.

That’s a great list Esq!
Thanks for putting that together. If I where to add anything to that list I would put the next “this is our mission” podcast with Megachips on there

I think it is the 3rd of May

 

[Esq.111]

That’s a great list Esq!
Thanks for putting that together. If I where to add anything to that list I would put the next “this is our mission” podcast with Megachips on there

I think it is the 3rd of May

Morning TFM,

Cheers, just added.

Esq.

 

[Deleted member 118]

Afternoon Chippers,

Thought I would try to contribute something to the forum.

Engagements & possible exciting events for the coming month of May.
* I dare say there will be others which I have missed.

1, 3rd May, BRN Podcast, No.16, MegaChips ( BRN Partner), Rob Telson & Doug Fairbaine chew the fat.

2, 12th May, Autosense, Detroit, USA, Anil presenting.

3, 12th May, Automotive Tech Virtual Conference,
Kris Carlson presenting.

4, 18th May, Embeded Vision Summit.

5, 24th May, Vorago, Space Tech Expo, RAD Hardened AKIDA ??

6, 24th May, Brainchip Annual General Meeting.
* Everyone needs to make their vote count, we do own a peice of the company.

7, 29th May, International Symposium on Olfaction & Electronic Nose, Aveiro, Portugal, Hossam Haick talking, NANOSE.

& last , but not least, something most if not all Chippers have been waiting on........

8, 30th May, F.D.A.A.A, (American Food & Drug Administration Ammendments Act.), Dianose, Covid detection unit, NCT04476927, Required Report Date .


Looking foward to it.

Big thankyou to all the Super Sluthes, Bloody LEDGENDS.

Regards,
Esq.

You’ve missed the May 20th off the list and one off the most important events ever.

 

[Space Cadet]

An workshop coming up with Heinrich Gotzig from Valeo who will be chairing

NeuroEng 2022 Workshop | EBCCSP'2022 Conference

NeuroEng Workshop First International Workshop on Event Sensing and Neuromorphic Engineering NeuroEng 2022 Technical focus The aim of the International Workshop on Event Sensors and Neuromorphic Engineering is to provide a platform for the research communities to exchange new ideas and research...

ebccsp2022.org

Topics of interest include, but are not limited to:​

• event-based sensing,
• event-based neuromorphic engineering,
• event-driven
• vision, event-driven audio,
• event-based olfactory systems,
• event-driven robot skin,
• event-based information processing,
• event-based motion detection and integration,
• spiking neural networks,
• edge computing,
• address-event representation,
• visual recognition,
• depth estimation,
• real-time algorithms,
• motion estimation,
• object tracking,
• sensor fusion.

See this is being held in Poland. Maybe Anil can attend, take a few AKD1000 chips with him, smuggle then across the border to Ukraine and they can put them in numerous weaponry and put Putin on his arse and then the world can get back to its ordinary malfunctioning chaotic self.

SC

 

[Deleted member 118]

See this is being held in Poland. Maybe Anil can attend, take a few AKD1000 chips with him, smuggle then across the border to Ukraine and they can put them in numerous weaponry and put Putin on his arse and then the world can get back to its ordinary malfunctioning chaotic self.

SC

Close but not close enough

 

[Diogenese]

Hi FF,

I was caught short on this development by Imec.

Imec are using in-memory computing:
EP3671748A1 IN-MEMORY COMPUTING FOR MACHINE LEARNING

[0009] Operations on multiple stored values in the array going beyond bitwise logic functions can be implemented, in particular reduction operations, including summation, can be obtained by in-memory processing. No dedicated external unit is then needed or this unit may require less performance. This is particularly interesting for binary neural network applications for which the matrix-vector multiplications conventionally carried out by MAC units can be achieved by multiple in-memory XNOR products, followed by a subsequent in-memory summation.

[0047] In-memory processing, in the context of the present invention, refers to a memory structure, such as an array or a plurality of sub-arrays comprising memory cells, which also comprises processing logic or processing functionality on stored data bits. In contrast to near memory computing or conventional memory structures which are not in-memory processing, the requested data is not only read and communicated to an external processing unit, but is already modified or processed as of the moment it is sent out of the memory structure. In exemplary embodiments processing of requested data bits, before communicating the results to peripheral further processing units, may include bitwise Boolean operations such as, but not limited to XOR and/or XNOR multiplication of pairs of requested data bits or addition of one or more requested data bits or intermediate functional results thereof. In-memory processing is highly desirable for fast and energy-efficient computing hardware as it is mitigating the von Neumann bottleneck. Having a processing unit waiting for unprocessed fetched data from memory before it can start processing it is often an inefficient use of the available resources and bandwidth. Therefore, a limiting the amount of raw data communicated to the processing unit and sending (pre-) processed data to the processing unit instead, is providing a more efficient use of the available resources and bandwidth. Whereas near memory computing tries to limit the length of data paths from the memory structure to a nearby processing logic, in-memory processing goes one step further by incorporating the processing logic directly into the memory structure.

View attachment 5300

In-memory computing for 1-bit weights and actuations (SNN) are carried out by simple logic gates and an adder.

The title of the patent refers to learning, but I haven't got to that bit yet, as I need to post this retraction of my earlier post asap.

The Imec patent application has been abandoned.

 

[Deleted member 118]

Magik eye must be very close to releasing version 2

Magik-Eye Support

support.magik-eye.com

 

[Food4 thought]

I am all in favour of what you are suggesting that Brainchip and AKIDA technology might get called in to assist Aeva but my point was not contrary to this but that AKIDA is not competing with Aeva or any other player in LiDAR Valeo is the one competing and so far it has dominated and leads the market and with AKIDA onboard has taken a quantum leap on every other competitor in this space that does not have the AKIDA technology advantage.

Brainchip is a facilitator not a competitor open to anyone to take on board.

REMEMBER the goal is for Brainchip’s technology to become the default standard - CEO Sean Hehir 2022.

My opinion only DYOR
FF

 

[Fact Finder]

The Imec patent application has been abandoned.

Just to be clear it is EP3671748A1 IN-MEMORY COMPUTING FOR MACHINE LEARNING that has been abandoned.

Does that then mean IMEC only have as far as we know the original patent for an analog SNN?

Many thanks @Diogenese

My opinion only DYOR
FF

AKIDA BALLISTA

 

[Cyw]

Magik eye must be very close to releasing version 2

Magik-Eye Support

support.magik-eye.com

I have this robot vacuum but it is pretty dumb in avoiding obstacles. It has to hit the obstacle before changing directions. Ecovacs (Chinese company listed in Shanghai) release the new omni robovac that has LiDAR for smart navigation. Wonder if they are using Magikeye? What AI visual sensor processor is available now other than AKIDA?

Deebot X1-Omni

 

[Deleted member 118]

I have this robot vacuum but it is pretty dumb in avoiding obstacles. It has to hit the obstacle before changing directions. Ecovacs (Chinese company listed in Shanghai) release the new omni robovac that has LiDAR for smart navigation. Wonder if they are using Magikeye? What AI visual sensor processor is available now other than AKIDA?

Deebot X1-Omni

Maybe you should buy a Roomba

 

[Fact Finder]

This is the link to IMEC’s website. I cannot find other than an analogue SNN chip that appears to have been fabricate in 2020. It is not an easy site to navigate so others might like to look as well:

Imec R&D, nano electronics and digital technologies

Imec is the world-leading R&D and innovation hub in nanoelectronics and digital technologies.

www.imec-int.com

My opinion only DYOR
FF

AKIDA BALLISTA

 

[Bravo]

Just to be clear it is EP3671748A1 IN-MEMORY COMPUTING FOR MACHINE LEARNING that has been abandoned.

Does that then mean IMEC only have as far as we know the original patent for an analog SNN?

Many thanks @Diogenese

My opinion only DYOR
FF

AKIDA BALLISTA

Hi FF,

It would be funny if this is the case since the press release I posted states "Contrary to analog SNN implementations, imec’s event-driven digital design makes the chip behave exactly and repeatedly as predicted by the neural network simulation tools."

If they had to abandon the new patent and go back to analogue then they have shot themselves in the foot by this admission. The press release was dated the 28 April 2020 (if this helps) and it's an interesting read, especially the list of use cases.

Here's the original post: #9,890

 

[Space Cadet]

Just to be clear it is EP3671748A1 IN-MEMORY COMPUTING FOR MACHINE LEARNING that has been abandoned.

Does that then mean IMEC only have as far as we know the original patent for an analog SNN?

Many thanks @Diogenese

My opinion only DYOR
FF

AKIDA BALLISTA

Maybe they abandoned the digital version because there was a cheap superior one already available lol

SC

 

[Fact Finder]

Hi FF,

It would be funny if this is the case since the press release I posted states "Contrary to analog SNN implementations, imec’s event-driven digital design makes the chip behave exactly and repeatedly as predicted by the neural network simulation tools."

If they had to abandon the new patent and go back to analogue then they have shot themselves in the foot by this admission. The press release was dated the 28 April 2020 (if this helps) and it's an interesting read, especially the list of use cases.

Here's the original post: #9,890

I did not request their White Paper which provides on the description a roadmap towards Ai at the Edge. It does by implication suggest that they are saying in 2022 that they are not yet where they were claiming to be in 2020.

I did not see anyone limping on the website but they could still be off undergoing rehab to learn how to walk with a hole in their foot.

My opinion only DYOR
FF

AKIDA BALLISTA