Waiting Waiting and waiting. Will it happen, who knows loosing faithDamn it esq, don't say things like that around here. You will get reported and deported back to Hot Crapper.
You've suspiciously written something that an MF article would say. Are you a down ramper by any chance? Well if so then you are not doing a great job at it.
Keep the vibes positive please.
Sean is our golden boy and he deserves all the monies and then some. We hired him because he has very high connections in silicon valley and we are so very close to signing multi billion dollar NDAs with with Nanose and Nintendo. There is no further need to justify why our tech will be in every household items in the world. Just like FF, I am off to spread the good news somewhere else.
Weeeeeeeeee......!!!!!!
As always,
Not advice. DYOR
BRN Discussion Ongoing
- Thread starter TechGirl
- Start date
buena suerte :-)
BOB Bank of Brainchip
This is a piece from the 2024 AGM transcript where SH mentions...
"closing in on a decision" and .....
"Based on direct prospect feedback I believe we are well positioned in some of the more critical engagements. In a number of cases, we have made it through the down selection process that eliminates many competitors and focuses on only 2 or 3 vendors for final selection."
Last edited:
Quiltman
Regular
I know most here understand this chart : the chart of the entrepreneur.
It's difficult when you are in the midst of the action, privy to all that is going on.
But when you are on the outside looking in, as are shareholders, somewhat manic !
What Brainchip in delivering to the market is revolutionary, and IMO following this curve.
We are at that point of " Crash & Burn - ie. give up " , or moving towards the uptrend - and everyone is feeling nervous.
Like many here, I attended the AGM to try to be as informed as possible from the business, not hearsay & scuttlebutt, and I satisfied myself, along with all the data that has been made available, that we will succeed.
But I truly do understand those that are losing hope ... it is to be expected ... we are following the normal & expected path of any disruptive technology or entrepreneurial endeavour.
Pom down under
Top 20
Earlyrelease
Regular
Good things come to those that wait.Me waiting for a price sensitive announcement.
Always hated that saying when mum used to say it but it’s a tried and tested historical saying for a reason.
Getupthere
Regular
Edge AI accelerator delivers 60 TOPS at minimal power — Electronic Products
EdgeCortix’s SAKURA-II energy-efficient edge AI accelerator handles the latest GenAI tasks at the edge, including LLMs and LVMs.
Edge AI accelerator delivers 60 TOPS at minimal power
Jul 3, 2024 | 7:31 AM
Startup EdgeCortix Inc. recently launched its next-generation SAKURA-II edge AI accelerator, designed for processing generative AI (GenAI) workloads at the edge with minimal power consumption and low latency. This platform is paired with the company’s second-generation dynamic neural accelerator (DNA) architecture to address the most challenging GenAI tasks in the industry.
EdgeCortix, headquartered in Japan, introduced its first-generation AI accelerator, SAKURA-I, in 2022, claiming over 10× performance-per-watt advantage over competing AI inference solutions based on GPUs for real-time edge applications. It also announced the open-source release of its MERA compiler software framework.
The company has leveraged feedback from customers using its first-generation silicon to deliver an updated architecture that offers future-proofing in terms of activation functions and support for a changing AI model landscape, while adding new features, such as sparse computation, advanced power management, mixed-precision support and a new reshaper engine. It also offers better performance per watt and higher memory capacity in multiple form factors.
SAKURA-II edge AI accelerator (Source: EdgeCortix Inc.)
The SAKURA-II accelerator or co-processor is a compelling solution, with a performance of 60 trillion operations per second (TOPS) with 8 W of typical power consumption, mixed-precision support and built-in memory-compression capabilities, said Sakyasingha Dasgupta, CEO and founder of EdgeCortix. Whether running traditional AI models or the latest GenAI solutions at the edge, it is one of the most flexible and power-efficient accelerators, he added.
SAKURA-II can handle complex tasks, such as large language models (LLMs), large vision models (LVMs) and multimodal transformer-based applications in the manufacturing, Industry 4.0, security, robotics, aerospace and telecommunications industries. It can manage multi-billion parameter models, such as Llama 2, Stable Diffusion, DETR and ViT, within a typical power envelope of 8 W.
In a nutshell, the SAKURA-II accelerator is optimized for GenAI and real-time data streaming with low latency. It delivers exceptional energy efficiency (touted as more than 2× the AI compute utilization of other solutions), higher DRAM capacity—up to 32 GB—to handle complex vision and GenAI workloads, and up to 4× more DRAM bandwidth than other AI accelerators and advanced power management for ultra-high-efficiency modes. It also adds sparse computation to reduce the memory bandwidth, a new integrated tensor reshaper engine to minimize the host CPU load, arbitrary activation function and software-enabled mixed precision for near-F32 accuracy.
EdgeCortix’s solutions aim to reduce the cost, power and time of data transfer by moving more AI processing to the site of data creation. The edge AI accelerator platform addresses two big challenges due to “the explosive growth of the latest-generation AI models,” Dasgupta said. The first challenge is the rising computational demand due to these “exponentially growing models” and the resulting rise in hardware costs, he said.
The cost of deploying a solution or the cost of operation, whether it is in a smart city, robotics or the aerospace industry in an edge environment, is critically important, he added.
The second challenge is how to build more power-efficient systems. “Unfortunately, the majority of today’s AI models are a lot more power-hungry in terms of both electricity consumption as well as carbon emissions,” he said. “So how do we build systems with a software and hardware combination that is a lot more energy-efficient, especially for an edge environment that is constrained by power, weight and size? That really drives who we are as a company.”
The company’s core mission, Dasgupta said, is to deliver a solution that brings near-cloud-level performance to the edge environment, while also delivering orders of magnitude better power efficiency.
Performance per watt is a key factor for customers, Dasgupta added, especially in an edge environment, and within that, real-time processing becomes a critical factor.
Data at the edge
Looking at the data center versus edge landscape, most of the data consumed is being generated or processed, especially enterprise data, at the edge and that will continue into the future, Dasgupta said.
According to IDC, 74 zettabytes of data will be generated at the edge by 2025. Moving this enormous amount of data continuously from the edge to the cloud is expensive both in terms of power and time, he adds. “The fundamental tenet of AI is how we bring computation and intelligence to the seat of data creation.”
Dasgupta said EdgeCortix has achieved this by pairing its design ethos of software first with power-efficient hardware to reduce the cost of data transfer.
The latest product caters to the GenAI landscape as well as across multi-billion parameter LLMs and vision models within the constraint of low-power requirements at the edge across applications, Dasgupta said. The latest low-power GenAI solution targets a range of verticals, from smart cities, smart retail and telecom to robotics, the factory floor, autonomous vehicles and even military/aerospace.
The platform
The software-driven unified platform is comprised of the SAKURA AI accelerator, MERA compiler and framework, DNA technology and the AI accelerator modules and boards. It supports both the latest GenAI and convolutional models.
Designed for flexibility and power efficiency, SAKURA-II offers high memory bandwidth, high accuracy and compact form factors. By leveraging EdgeCortix’s latest-generation runtime reconfigurable neural processing engine, DNA-II, SAKURA-II can provide high power efficiency and real-time processing capabilities while simultaneously executing multiple deep neural network models with low latency.
Dasgupta said it is difficult to put a number to latency because it depends on the AI models and applications. Most applications, depending on the larger models, will be below 10 ms, and in some cases, it could be in the sub-millisecond range.
The SAKURA-II hardware and software platform delivers flexibility, scalability and power efficiency. (Source: EdgeCortix Inc.)
The SAKURA-II platform, with the company’s MERA software suite, features a heterogeneous compiler platform, advanced quantization and model calibration capabilities. This software suite includes native support for development frameworks, such as PyTorch, TensorFlow Lite and ONNX. MERA’s flexible host-to-accelerator unified runtime can scale across single, multi-chip and multi-card systems at the edge. This significantly streamlines AI inferencing and shortens deployment times.
In addition, the integration with the MERA Model Zoo offers a seamless interface to Hugging Face Optimum and gives users access to an extensive range of the latest transformer models. This ensures a smooth transition from training to edge inference.
“One of the exciting elements is a new MERA model library that creates a direct interface with Hugging Face where our customers can bring a large number of current-generation transformer models without having to worry about portability,” Dasgupta said.
MERA Software supports diverse neural networks, from convolutions to the latest GenAI models. (Source: EdgeCortix Inc.)
By building a software-first—Software 2.0—architecture with new innovations, Dasgupta said the company has been able to get an order or two orders of magnitude increase in peak performance per watt compared with general-purpose systems, using CPUs and GPUs, depending on the application.
“We are able to preserve high accuracy [99% of FP32] for applications within those constrained environments of the edge; we’re able to deliver a lot more performance per watt, so better efficiency, and much higher speed in terms of the latency-sensitive and real-time critical applications, especially driven by multimodal-type applications with the latest generative AI models,” Dasgupta said. “And finally, a lower cost of operations in terms of even performance per dollar, preserving a significant advantage compared with other competing solutions.”
This drives edge AI accelerator requirements, which has gone into the design of the latest SAKURA product, Dasgupta said.
More details on SAKURA-II
SAKURA-II can deliver up to 60 TOPS of 8-bit integer, or INT8, performance and 30 trillion 16-bit brain floating-point operations per second (TFLOPS), while also supporting built-in mixed precision for handling next-generation AI tasks. The higher DRAM bandwidth targets the demand for higher performance for LLMs and LVMs.
Also new for the SAKURA-II are the advanced power management features, including on-chip power gating and power management capabilities for ultra-high-efficiency modes and a dedicated tensor reshaper engine to manage complex data permutations on-chip and minimize host CPU load for efficient data handling.
Some of the key architecture innovations include sparse computation that natively supports memory footprint optimization to reduce the amount of memory required to move large amounts of models, especially multi-billion-parameter LLMs, Dasgupta said, which has a big impact on performance and power consumption.
The built-in advanced power management mechanisms can switch off different parts of the device while an application is running in a way that can trade off power versus performance, Dasgupta said, which enhances the performance per watt in applications or models that do not require all 60 TOPS.
“We also added a dedicated IP in the form of a new reshaper engine on the hardware itself, and this has been designed to handle large tensor operations,” Dasgupta said. This dedicated engine on-chip improves power as well as reduces latency even further, he added.
Dasgupta said the accelerator architecture is the key building block of the SAKURA-II’s performance. “We have much higher utilization of our transistors on the semiconductor as compared with some of our competitors, especially from a GPU perspective. It is typically somewhere on average 2× better utilization, and that gives us much better performance per watt.”
SAKURA-II also adds support for arbitrary activation functions on the hardware, which Dasgupta calls a future-proofing mechanism, so as new types of arbitrary activation functions come in, they can be extended to the user without having to change the hardware.
It also offers mixed-precision support on the software and hardware to trade off between performance and accuracy. Running some parts of a model at a higher precision and others at a reduced precision, depending on the application, becomes important in multimodal cases, Dasgupta said.
SAKURA-II is available in several form factors to meet different customer requirements. These include a standalone device in a 19 × 19-mm BGA package, a M.2 module with a single device and PCIe cards with up to four devices. The M.2 module offers 8 or 16 GB of DRAM and is designed for space-constrained applications, while the single (16-GB DRAM) and dual (32-GB DRAM) PCIe cards target edge server applications.
SAKURA-II addresses space-constrained environments with the M.2 module form factor, supporting both x86 or Arm systems, and delivers performance by supporting multi-billion-parameter models as well as traditional vision models, Dasgupta said.
“The latest-generation product supports a very powerful compiler and software stack that can marry our co-processor with existing x86 or Arm systems working across different types of heterogeneous landscape in the edge space.”
SAKURA-II M.2 module (Source: EdgeCortix Inc.)
The unified platform also delivers a high amount of compute, up to 240 TOPS, in a single PCIe card with four devices with under 50 W of power consumption.
Dasgupta said power has been maintained at previous levels with the SAKURA-II, so customers are getting a much higher performance per watt. The power consumption is typically about 8 W for the most complex AI models and even less for some applications, he said.
SAKURA-II will be available as a standalone device, with two M.2 modules with different DRAM capacities (8 GB and 16 GB), and single- and dual-device low-profile PCIe cards. Customers can reserve M.2 modules and PCIe cards for delivery in the second half of 2024. The accelerators, M.2 modules and PCIe cards can be pre-ordered.
Competition? They are moving away from the cloud?
Edge AI accelerator delivers 60 TOPS at minimal power — Electronic Products
EdgeCortix’s SAKURA-II energy-efficient edge AI accelerator handles the latest GenAI tasks at the edge, including LLMs and LVMs.apple.news
Edge AI accelerator delivers 60 TOPS at minimal power
Jul 3, 2024 | 7:31 AM
Startup EdgeCortix Inc. recently launched its next-generation SAKURA-II edge AI accelerator, designed for processing generative AI (GenAI) workloads at the edge with minimal power consumption and low latency. This platform is paired with the company’s second-generation dynamic neural accelerator (DNA) architecture to address the most challenging GenAI tasks in the industry.
EdgeCortix, headquartered in Japan, introduced its first-generation AI accelerator, SAKURA-I, in 2022, claiming over 10× performance-per-watt advantage over competing AI inference solutions based on GPUs for real-time edge applications. It also announced the open-source release of its MERA compiler software framework.
The company has leveraged feedback from customers using its first-generation silicon to deliver an updated architecture that offers future-proofing in terms of activation functions and support for a changing AI model landscape, while adding new features, such as sparse computation, advanced power management, mixed-precision support and a new reshaper engine. It also offers better performance per watt and higher memory capacity in multiple form factors.
SAKURA-II edge AI accelerator (Source: EdgeCortix Inc.)
The SAKURA-II accelerator or co-processor is a compelling solution, with a performance of 60 trillion operations per second (TOPS) with 8 W of typical power consumption, mixed-precision support and built-in memory-compression capabilities, said Sakyasingha Dasgupta, CEO and founder of EdgeCortix. Whether running traditional AI models or the latest GenAI solutions at the edge, it is one of the most flexible and power-efficient accelerators, he added.
SAKURA-II can handle complex tasks, such as large language models (LLMs), large vision models (LVMs) and multimodal transformer-based applications in the manufacturing, Industry 4.0, security, robotics, aerospace and telecommunications industries. It can manage multi-billion parameter models, such as Llama 2, Stable Diffusion, DETR and ViT, within a typical power envelope of 8 W.
In a nutshell, the SAKURA-II accelerator is optimized for GenAI and real-time data streaming with low latency. It delivers exceptional energy efficiency (touted as more than 2× the AI compute utilization of other solutions), higher DRAM capacity—up to 32 GB—to handle complex vision and GenAI workloads, and up to 4× more DRAM bandwidth than other AI accelerators and advanced power management for ultra-high-efficiency modes. It also adds sparse computation to reduce the memory bandwidth, a new integrated tensor reshaper engine to minimize the host CPU load, arbitrary activation function and software-enabled mixed precision for near-F32 accuracy.
EdgeCortix’s solutions aim to reduce the cost, power and time of data transfer by moving more AI processing to the site of data creation. The edge AI accelerator platform addresses two big challenges due to “the explosive growth of the latest-generation AI models,” Dasgupta said. The first challenge is the rising computational demand due to these “exponentially growing models” and the resulting rise in hardware costs, he said.
The cost of deploying a solution or the cost of operation, whether it is in a smart city, robotics or the aerospace industry in an edge environment, is critically important, he added.
The second challenge is how to build more power-efficient systems. “Unfortunately, the majority of today’s AI models are a lot more power-hungry in terms of both electricity consumption as well as carbon emissions,” he said. “So how do we build systems with a software and hardware combination that is a lot more energy-efficient, especially for an edge environment that is constrained by power, weight and size? That really drives who we are as a company.”
The company’s core mission, Dasgupta said, is to deliver a solution that brings near-cloud-level performance to the edge environment, while also delivering orders of magnitude better power efficiency.
Performance per watt is a key factor for customers, Dasgupta added, especially in an edge environment, and within that, real-time processing becomes a critical factor.
Data at the edge
Looking at the data center versus edge landscape, most of the data consumed is being generated or processed, especially enterprise data, at the edge and that will continue into the future, Dasgupta said.
According to IDC, 74 zettabytes of data will be generated at the edge by 2025. Moving this enormous amount of data continuously from the edge to the cloud is expensive both in terms of power and time, he adds. “The fundamental tenet of AI is how we bring computation and intelligence to the seat of data creation.”
Dasgupta said EdgeCortix has achieved this by pairing its design ethos of software first with power-efficient hardware to reduce the cost of data transfer.
The latest product caters to the GenAI landscape as well as across multi-billion parameter LLMs and vision models within the constraint of low-power requirements at the edge across applications, Dasgupta said. The latest low-power GenAI solution targets a range of verticals, from smart cities, smart retail and telecom to robotics, the factory floor, autonomous vehicles and even military/aerospace.
The platform
The software-driven unified platform is comprised of the SAKURA AI accelerator, MERA compiler and framework, DNA technology and the AI accelerator modules and boards. It supports both the latest GenAI and convolutional models.
Designed for flexibility and power efficiency, SAKURA-II offers high memory bandwidth, high accuracy and compact form factors. By leveraging EdgeCortix’s latest-generation runtime reconfigurable neural processing engine, DNA-II, SAKURA-II can provide high power efficiency and real-time processing capabilities while simultaneously executing multiple deep neural network models with low latency.
Dasgupta said it is difficult to put a number to latency because it depends on the AI models and applications. Most applications, depending on the larger models, will be below 10 ms, and in some cases, it could be in the sub-millisecond range.
The SAKURA-II hardware and software platform delivers flexibility, scalability and power efficiency. (Source: EdgeCortix Inc.)
The SAKURA-II platform, with the company’s MERA software suite, features a heterogeneous compiler platform, advanced quantization and model calibration capabilities. This software suite includes native support for development frameworks, such as PyTorch, TensorFlow Lite and ONNX. MERA’s flexible host-to-accelerator unified runtime can scale across single, multi-chip and multi-card systems at the edge. This significantly streamlines AI inferencing and shortens deployment times.
In addition, the integration with the MERA Model Zoo offers a seamless interface to Hugging Face Optimum and gives users access to an extensive range of the latest transformer models. This ensures a smooth transition from training to edge inference.
“One of the exciting elements is a new MERA model library that creates a direct interface with Hugging Face where our customers can bring a large number of current-generation transformer models without having to worry about portability,” Dasgupta said.
MERA Software supports diverse neural networks, from convolutions to the latest GenAI models. (Source: EdgeCortix Inc.)
By building a software-first—Software 2.0—architecture with new innovations, Dasgupta said the company has been able to get an order or two orders of magnitude increase in peak performance per watt compared with general-purpose systems, using CPUs and GPUs, depending on the application.
“We are able to preserve high accuracy [99% of FP32] for applications within those constrained environments of the edge; we’re able to deliver a lot more performance per watt, so better efficiency, and much higher speed in terms of the latency-sensitive and real-time critical applications, especially driven by multimodal-type applications with the latest generative AI models,” Dasgupta said. “And finally, a lower cost of operations in terms of even performance per dollar, preserving a significant advantage compared with other competing solutions.”
This drives edge AI accelerator requirements, which has gone into the design of the latest SAKURA product, Dasgupta said.
More details on SAKURA-II
SAKURA-II can deliver up to 60 TOPS of 8-bit integer, or INT8, performance and 30 trillion 16-bit brain floating-point operations per second (TFLOPS), while also supporting built-in mixed precision for handling next-generation AI tasks. The higher DRAM bandwidth targets the demand for higher performance for LLMs and LVMs.
Also new for the SAKURA-II are the advanced power management features, including on-chip power gating and power management capabilities for ultra-high-efficiency modes and a dedicated tensor reshaper engine to manage complex data permutations on-chip and minimize host CPU load for efficient data handling.
Some of the key architecture innovations include sparse computation that natively supports memory footprint optimization to reduce the amount of memory required to move large amounts of models, especially multi-billion-parameter LLMs, Dasgupta said, which has a big impact on performance and power consumption.
The built-in advanced power management mechanisms can switch off different parts of the device while an application is running in a way that can trade off power versus performance, Dasgupta said, which enhances the performance per watt in applications or models that do not require all 60 TOPS.
“We also added a dedicated IP in the form of a new reshaper engine on the hardware itself, and this has been designed to handle large tensor operations,” Dasgupta said. This dedicated engine on-chip improves power as well as reduces latency even further, he added.
Dasgupta said the accelerator architecture is the key building block of the SAKURA-II’s performance. “We have much higher utilization of our transistors on the semiconductor as compared with some of our competitors, especially from a GPU perspective. It is typically somewhere on average 2× better utilization, and that gives us much better performance per watt.”
SAKURA-II also adds support for arbitrary activation functions on the hardware, which Dasgupta calls a future-proofing mechanism, so as new types of arbitrary activation functions come in, they can be extended to the user without having to change the hardware.
It also offers mixed-precision support on the software and hardware to trade off between performance and accuracy. Running some parts of a model at a higher precision and others at a reduced precision, depending on the application, becomes important in multimodal cases, Dasgupta said.
SAKURA-II is available in several form factors to meet different customer requirements. These include a standalone device in a 19 × 19-mm BGA package, a M.2 module with a single device and PCIe cards with up to four devices. The M.2 module offers 8 or 16 GB of DRAM and is designed for space-constrained applications, while the single (16-GB DRAM) and dual (32-GB DRAM) PCIe cards target edge server applications.
SAKURA-II addresses space-constrained environments with the M.2 module form factor, supporting both x86 or Arm systems, and delivers performance by supporting multi-billion-parameter models as well as traditional vision models, Dasgupta said.
“The latest-generation product supports a very powerful compiler and software stack that can marry our co-processor with existing x86 or Arm systems working across different types of heterogeneous landscape in the edge space.”
SAKURA-II M.2 module (Source: EdgeCortix Inc.)
The unified platform also delivers a high amount of compute, up to 240 TOPS, in a single PCIe card with four devices with under 50 W of power consumption.
Dasgupta said power has been maintained at previous levels with the SAKURA-II, so customers are getting a much higher performance per watt. The power consumption is typically about 8 W for the most complex AI models and even less for some applications, he said.
SAKURA-II will be available as a standalone device, with two M.2 modules with different DRAM capacities (8 GB and 16 GB), and single- and dual-device low-profile PCIe cards. Customers can reserve M.2 modules and PCIe cards for delivery in the second half of 2024. The accelerators, M.2 modules and PCIe cards can be pre-ordered.
" According to IDC, 74 zettabytes of data will be generated at the edge by 2025. Moving this enormous amount of data continuously from the edge to the cloud is expensive both in terms of power and time, he adds. “The fundamental tenet of AI is how we bring computation and intelligence to the seat of data creation.”"
It is a fact that I did not find this paper myself, but it contains tables of an extensive survey of AI chips, conducted by AFRL in conjunction with Dayton Uni.
Table 2 compares 100 AI chips, so it is useful as a compressed, if not 100% accurate, guide to the competition.
https://www.preprints.org/manuscript/202407.0025/download/final_file
...
BrainChip introduced the Akida line of spiking processors. The AKD1000 has 80 NPUs, 3 pJ/synaptic operation, and around 2 W of power consumption [147]. Each NPU consists of eight neural processing engines that run simultaneously and control convolution, pooling, and activation (ReLu) operations [148]. Convolution is normally carried out in INT8 precision, but it can be programmed for INT 1, 2, 3 or 4 precisions while sacrificing 1-3% accuracy. BrainChip has announced future releases of smaller and larger Akida processors under the AKD500, AKD1500, and AKD2000 labels [148]. A trained DNN network can be converted to SNN by using the CNN2SNN tool in the Meta-TF framework for loading a model into an Akida processor. This processor also has on-chip training capability, thus allowing the training of SNNs from scratch by using the Meta-TF framework [146].
...
Several of the edge processors offer on-chip retraining in real-time. This enables retraining of networks without having to send sensitive data to the cloud, thus increasing security and privacy. Intel’s Loihi 2 and Brainchip’s Akida processor can be retrained on local data for personalized applications and faster response rates.
Table 2 compares 100 AI chips, so it is useful as a compressed, if not 100% accurate, guide to the competition.
https://www.preprints.org/manuscript/202407.0025/download/final_file
...
BrainChip introduced the Akida line of spiking processors. The AKD1000 has 80 NPUs, 3 pJ/synaptic operation, and around 2 W of power consumption [147]. Each NPU consists of eight neural processing engines that run simultaneously and control convolution, pooling, and activation (ReLu) operations [148]. Convolution is normally carried out in INT8 precision, but it can be programmed for INT 1, 2, 3 or 4 precisions while sacrificing 1-3% accuracy. BrainChip has announced future releases of smaller and larger Akida processors under the AKD500, AKD1500, and AKD2000 labels [148]. A trained DNN network can be converted to SNN by using the CNN2SNN tool in the Meta-TF framework for loading a model into an Akida processor. This processor also has on-chip training capability, thus allowing the training of SNNs from scratch by using the Meta-TF framework [146].
...
Several of the edge processors offer on-chip retraining in real-time. This enables retraining of networks without having to send sensitive data to the cloud, thus increasing security and privacy. Intel’s Loihi 2 and Brainchip’s Akida processor can be retrained on local data for personalized applications and faster response rates.
Space Cadet
Regular
Tata Elxsi have been talking up health care. Found this interesting. Noo mention of Akida but with NDA's you wouldn't expect to.
Show where they are heading with Neuromorphic and Healthcare. There are so many avenues for us.
https://ai.tataelxsi.com/healthcare...or-disease-detection-diagnosis-and-prognosis/
Apologies if already posted.
SC
Show where they are heading with Neuromorphic and Healthcare. There are so many avenues for us.
https://ai.tataelxsi.com/healthcare...or-disease-detection-diagnosis-and-prognosis/
Apologies if already posted.
SC
Frangipani
Top 20
By chance, I stumbled upon the following post about USC graduate Natalie Fung, who was recently awarded a Master in Communications Data Science - with her resilience and can-do attitude, she truly is an inspiration:
How heart-warming that USC Viterbi even awarded her service dog a certificate of graduation at the commencement ceremony in May!
The May 2024 USC website article, which is linked in the first post, mentions the name of her lab:
Changing Course: Natalie Fung - USC Viterbi | School of Engineering
From PR to data science, Natalie Fung, a graduating master's student, on becoming a "double Trojan" after a life-altering accident.
viterbischool.usc.edu
“Since fall 2021, I’ve been involved with accessibility awareness on campus through the Viterbi Graduate Student Association, from partnering with the Graduate Student Government to put on a disability resource and awareness fair, to creating content on acquiring accommodations at USC.
I’m also a lab manager and research assistant in the Valero Lab under Prof. Francisco Valero-Cuevas, where I previously helped him plan a conference held at USC in conjunction with the National Science Foundation. Four published papers on disability and rehabilitation engineering resulted from the conference!
I’m now being funded by NSF to see how a neuromorphic arm developed in the lab can be directly translated into real life.”
The USC Brain-Body Dynamics Lab is led by Francisco Valero-Cuevas, Professor of Biomedical Engineering, Aerospace and Mechanical Engineering, Electrical and Computer Engineering, Computer Science, and Biokinesiology and Physical Therapy (try to fit all this onto one business card!), who has been fascinated with the biomechanics of the human hand for years (see the 2008 article below) and was already talking about utilising neuromorphic chips in robots three years ago, in a ‘research update’ video recorded on June 17, 2021:
“But at the same time we are building physical robots that have what are called ‘neuromorphic circuits’. These are computer chips that are emulating populations of spiking neurons that then feed motors and amplifiers and the like that actually produce manipulation and locomotion.” (from 2:56 min)
Given that a number of USC Viterbi School of Engineering faculty members are evidently favourably aware of BrainChip (see below) - plus our CTO happens to be a USC School of Engineering alumnus and possibly still has some ties to his alma mater - I wouldn’t be surprised if Valero Lab researchers were also experimenting with Akida.
Remember this June 2023 This is our Mission podcast?
Episode 27: Podcast with USC Professor Dr. Gaurav Sukhatme on Innovation in AI, Robotics & Autonomy
Listen to Episode 27 of our podcast featuring USC Professor Dr. Gaurav Sukhatme as we explore innovation in AI, robotics, and autonomy.brainchip.com
After introducing his guest, who also serves as the Executive Vice Dean at the USC Viterbi School of Engineering, Nandan Nayampally says “You know, we go back a long way … in fact, we had common alma maters.” (03:14 min)
Gaurav Sukatme:
From 25:32 min: “I think the partnership between industry and academia is crucial here to make progress.”
From 27:13 min: “You know, companies like yours, like Brainchip, what you are doing with the University Accelerator Program, I like very much - in fact, we’re looking into it, as you know, we’ll be having a phone [?] conversation about exploring that further. I think programs like that are unique and can really make the nexus between a leading company and academia sort of be tighter and be stronger.”
At the end of the podcast, Nandan Nayampally thanks his guest for sharing his insights and closes with the words “…and hopefully we’ll work together much closer soon.” (35:15 min)
Which makes Brainchip’s involvement in CONCRETE (Center of Neuromorphic Computing and Extreme Environment”), well, not concrete, but certainly more likely…
Meanwhile, yet another university is encouraging their students to apply for a summer internship at BrainChip:
BrainChip– Internship Program 2024 - USC Viterbi | Career Services
BrainChip– Internship Opportunity! Apply Today! About BrainChip: BrainChip develops technology that brings commonsense to the processing of sensor data, allowing efficient use for AI inferencing enabling one to do more with less. Accurately. Elegantly. Meaningfully. They call this Essential AI...viterbicareers.usc.edu
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I guess it is just a question of time before USC will be added to the BrainChip University AI Accelerator Program, although Nandan Nayampally is sadly no longer with our company…
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Jacob Kiraz
Emerged
Problem is no IP Mate
Satchmo25
Member
Prepare yourself for the AI smartphone wars
The AI smartphone wars are coming, and companies are hoping it means big sales.
Samsung already investing in Axelera startup for ai chip. Hope Akida will be part in this smartphone war!
Can the climate survive the insatiable energy demands of the AI arms race?
New computing infrastructure means big tech is likely to miss emissions targets but they can’t afford to get left behind in a winner takes all market
Frangipani
Top 20
Hi FJ-215,
the article you linked to refers to a different Fraunhofer Institute, Fraunhofer IPMS in Dresden, whereas the Fraunhofer Institute shown in the video is Fraunhofer HHI (Heinrich-Hertz-Institut) in Berlin. (There are 76 Fraunhofer Institutes in total.)
At the very end of the video, there is a reference to a research paper, that I posted about a few weeks ago:
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https://thestockexchange.com.au/threads/brn-discussion-ongoing.1/post-417987
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And thanks to the video we now know what neuromorphic hardware the researchers used, even though they didn’t reveal it in their paper!
Our friends at Fraunhofer HHI
are part of the ongoing Berlin 6G Conference (July 2 - 4, 2024). While three of the above paper’s co-authors are session chairs or speakers, Yuzhen Ke and Mehdi Heshmati are giving live demos of Spiky Spot’s akidaesque gesture recognition skills at the conference expo.The Berlin-based researchers have been rather busy conference-hopping in recent weeks: Stockholm (Best Demonstration Award), Antwerp, Denver, Berlin (2x).
I am just not sure whether they have been letting curious visitors to their booth in on the secret behind their obedient robotic dog...
Some of the Fraunhofer Heinrich Hertz Institute researchers from Berlin who appear to have used Akida in their research, as evidenced by their recent video titled Neuromorphic Wireless Cognition for Connected Intelligence (encouragingly, there has been no denial in the comment section so far), are currently attending the IEEE International Conference on Communications in Denver, where they are presenting their demo video at the German 6G Research and Innovation Cluster booth.
IEEE International Conference on Communications
9–13 June 2024 // Denver, CO, USAicc2024.ieee-icc.org
One of their Fraunhofer HHI colleagues was promoting the demo video on LinkedIn earlier today, while at the same time cozying up to Ericsson at the booth opposite them by praising Ericsson’s Head of Research Magnus Frodigh for addressing their common interest in neuromorphic processing and SNNs for 6G in his keynote speech.
After this virtual wave across the aisle, researchers on both sides will surely find the time to have a little chat even closer up, and in the case of Fraunhofer HHI possibly also with others who may have only become aware of the German 6G research delegation’s booth because of Ericsson and Magnus Frodigh getting mentioned in that LinkedIn post.
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Frangipani
Top 20
I like the way Alexandre Mandl from São Paulo, Brazil is asking this legitimate question without dissing NVIDIA:
“Is the next big thing in AI not about raw power but about doing more with less juice?”
www.linkedin.com
“Is the next big thing in AI not about raw power but about doing more with less juice?”
Alexandre Mandl - Magalu Cloud | LinkedIn
Results-driven Sales Leader of Leaders (LoL) with expertise in Value Selling and a proven… · Experience: Magalu Cloud · Education: Fundação Getúlio Vargas · Location: São Paulo · 500+ connections on LinkedIn. View Alexandre Mandl’s profile on LinkedIn, a professional community of 1 billion members.
Bennysmadness
Regular
How many k's we talking? Hope your not hogging them all hahaha
Frangipani
Top 20
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Frangipani
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Speaking of BAE Systems:
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BAE Systems FAST Labs Microelectronics Science and Technology (MS&T) area architects novel and beyond-next-generation RF, mixed-signal, and digital integrated circuits and chipsets, and delivers those new custom microelectronics capabilities into systems. With ongoing growth, MS&T is seeking a technology leader to help drive its strategy forward. The candidate for this position will lead Digital Microelectronics research and development pursuits, programs, and strategies. The trajectory of this portfolio includes algorithmic hardware accelerators, digital signal processor SOCs and ASICs, radiation hard microelectronics, non-traditional compute microelectronics architectures, and new high-risk/high-reward novel compute technologies.
The candidate will lead in engagement with external and internal customers to build, win, and execute programs that support the research and development of digital microelectronics technology. They are expected to leverage their position, reputation, and technical expertise to maintain and expand relationships with government R&D organization such as Department of Commerce, ONR, AFRL, OUSD(R&E), OUSD(A&S), DARPA, etc. Through their internal and external network, the candidate is expected to advance the Digital microelectronics technical and programmatic roadmaps while maintaining alignment across the broader MS&T area.
This job can be hybrid (on-site >=50% of time) or fully on-site.
In this job role, qualified candidates can expect to:
The ideal candidate will possess the following:
Full-Time Salary Range: $140690 – $239140
Please note: This range is based on our market pay structures. However, individual salaries are determined by a variety of factors including, but not limited to: business considerations, local market conditions, and internal equity, as well as candidate qualifications, such as skills, education, and experience.
Employee Benefits: At BAE Systems, we support our employees in all aspects of their life, including their health and financial well-being. Regular employees scheduled to work 20 hours per week are offered: health, dental, and vision insurance; health savings accounts; a 401(k) savings plan; disability coverage; and life and accident insurance. We also have an employee assistance program, a legal plan, and other perks including discounts on things like home, auto, and pet insurance. Our leave programs include paid time off, paid holidays, as well as other types of leave, including paid parental, military, bereavement, and any applicable federal and state sick leave. Employees may participate in the company recognition program to receive monetary or non-monetary recognition awards. Other incentives may be available based on position level and/or job specifics.
Digital Microelectronics Technology Development Lead
103227BR
EEO Career Site Equal Opportunity Employer. Minorities . females . veterans . individuals with disabilities . sexual orientation . gender identity . gender expression
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Digital Microelectronics Technology Development Lead
PUBLISHED: JULY 3, 2024 ONSITE ARLINGTON, VIRGINIA FULL TIME BUSINESS & FINANCEMECHANICAL ENGINEERINGSave
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Description
Job DescriptionBAE Systems FAST Labs Microelectronics Science and Technology (MS&T) area architects novel and beyond-next-generation RF, mixed-signal, and digital integrated circuits and chipsets, and delivers those new custom microelectronics capabilities into systems. With ongoing growth, MS&T is seeking a technology leader to help drive its strategy forward. The candidate for this position will lead Digital Microelectronics research and development pursuits, programs, and strategies. The trajectory of this portfolio includes algorithmic hardware accelerators, digital signal processor SOCs and ASICs, radiation hard microelectronics, non-traditional compute microelectronics architectures, and new high-risk/high-reward novel compute technologies.
The candidate will lead in engagement with external and internal customers to build, win, and execute programs that support the research and development of digital microelectronics technology. They are expected to leverage their position, reputation, and technical expertise to maintain and expand relationships with government R&D organization such as Department of Commerce, ONR, AFRL, OUSD(R&E), OUSD(A&S), DARPA, etc. Through their internal and external network, the candidate is expected to advance the Digital microelectronics technical and programmatic roadmaps while maintaining alignment across the broader MS&T area.
This job can be hybrid (on-site >=50% of time) or fully on-site.
In this job role, qualified candidates can expect to:
- Lead relevant research programs of 3-50 people as principal investigator
- Provide business and execution oversight of programs valued at $1-50M
- Lead pursuits and proposals
- Expand and maintain strategic relationships with government agencies, external companies, and other BAE Systems groups and business areas
- Implement a programmatic strategy to fund technology development
- Pursue personal and portfolio growth so as to support a broad team of scientists, researchers, and technology developers
- This position can be based out of our Merrimack, NH; Nashua, NH; Burlington, MA; Lexington, MA; Manassas, VA; or Arlington, VA facilities, though it will require collaboration with staff across our business areas and facilities in the Northeast.
The ideal candidate will possess the following:
- Excellent written and oral communication skills
- Experience capturing and leading projects within the defense microelectronics community, at the cutting edge of technology
- Prior experience as principal investigator on DoD R&D programs
- Track record of technical innovation as evidenced by journal and conference publications or patent filings
- Demonstrable entrepreneurial drive
- Experience in at least one of the following areas:
- Digital Signal Processing
- AI/ML Hardware Acceleration
- Digital system architecture
- Neural networks or neuromorphic engineering
- In-memory compute processors
- Ability to obtain clearance at the Secret level or higher
- Masters or PhD in electrical engineering or related field
Full-Time Salary Range: $140690 – $239140
Please note: This range is based on our market pay structures. However, individual salaries are determined by a variety of factors including, but not limited to: business considerations, local market conditions, and internal equity, as well as candidate qualifications, such as skills, education, and experience.
Employee Benefits: At BAE Systems, we support our employees in all aspects of their life, including their health and financial well-being. Regular employees scheduled to work 20 hours per week are offered: health, dental, and vision insurance; health savings accounts; a 401(k) savings plan; disability coverage; and life and accident insurance. We also have an employee assistance program, a legal plan, and other perks including discounts on things like home, auto, and pet insurance. Our leave programs include paid time off, paid holidays, as well as other types of leave, including paid parental, military, bereavement, and any applicable federal and state sick leave. Employees may participate in the company recognition program to receive monetary or non-monetary recognition awards. Other incentives may be available based on position level and/or job specifics.
Digital Microelectronics Technology Development Lead
103227BR
EEO Career Site Equal Opportunity Employer. Minorities . females . veterans . individuals with disabilities . sexual orientation . gender identity . gender expression
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