The NPU of the
The NPU of the STM32N6 is internally developed by STM.
<p><strong>Today, ST is officially becoming a member of <a title="MLCommons" href="https://mlcommons.org/en/" target="_blank" rel="noopener">MLCommons™</a>, the consortium responsible for benchmarks quantifying machine learning performance in mobile platforms, data centers, and embedded systems...
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E
arlier today during STMicroelectronics Capital Markets Day (https://cmd.st.com), I gave a presentation on MDG contribution to our ambition of reaching $20B revenue ambition by 2025-27.
During the event, I was proud to pre-announce the #STM32N6: a high performance #STM32 #MCU with our new internally developed Neural Processing Unit (#NPU) providing an order of magnitude benefit in both inference/w and inference/$ against alternative MPU solutions
The #STM32N6 will deliver #MPU #AI workloads at the cost and the power consumption of #MCU. This a complete game changer that will open new ranges of applications for our customers and allow them to democratise #AI at the edge.
I am excited to say we are on track to deliver first samples of the #STM32N6by the end of 2022. I
I am even more excited to announce that LACROIX will leverage this technology in their next generation smart city products.
Stay tuned for more news on the #STM32N6 in the coming months :=)
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Bells and whistles:
This is how STM does in-memory compute (not a pretty sight):
EP3761236A2 ELEMENTS FOR IN-MEMORY COMPUTE
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memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
So add that to Weebit's hybrid analog/digital ReRAM ...
We you did ask!
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