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Meet with BrainChip Inc. @ CES 2023 - BrainChip Inc
Meet with BrainChip Inc. to discuss how the technology can benefit your company or organization.
Make sure your kids get the white balloons if @Fact Finder is at the party.Just had a thought. Clearly it could identify the Varroa mite that would be easier than weeds.
I think as it’s just one object and they could provide many samples for training due to all the scientific study it would be dead easy.
My thought, bearing in mind it is a long time since I was interested in laser technology, is that you can tune lasers to act only on a particular colour.
One experiment I recall was exploding a red balloon inside a white balloon leaving the white balloon undamaged.
All we therefore need is to identify a necessary internal organ of the mite which has a colour not in common with the bee and ‘Death Ray Heaven Bee Hives’ is born.
My opinion only DYOR
FF
AKIDA BALLISTA
You stirred up some emotions with that post.A little bit of Australian history on our Department of Defence Barra Sonobuoy invention, hopefully we will be in future models as it uses hydrophones, acoustics, radio signals etc, I really enjoyed the article and it makes me proud to be Australian
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The Barra Sonobuoy: the Australian invention that makes it harder for subs to hide
The Barra sonobuoy is one of Australia's most successful Defence joint development projects, and highlights Australia's history as a global leader in the development and manufacture of advanced technologies.www.dst.defence.gov.au
THE BARRA SONOBUOY: THE AUSTRALIAN INVENTION THAT MAKES IT HARDER FOR SUBS TO HIDE
5 December 2022
NEWS
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The Barra sonobuoy is one of Australia's most successful Defence joint development projects, and highlights Australia's history as a global leader in the development and manufacture of advanced technologies.
Sonobuoys were first developed and used at the end of World War II in response to the devastating destruction of allied merchant ships in the Atlantic caused by German U-boats.
The ability to locate submarines so they could be sunk, or prevented from attacking, became critical for the Allied war effort, and so the idea of the 'buoy sonar' was born. The idea was simple: a sonobuoy was dropped into the water by passing aircraft and, upon impact, an underwater acoustic sensor (hydrophone) and floating radio transmitter would deploy. Any underwater acoustic signals detected by the hydrophone, caused by a nearby U-boat for example, would then be relayed to the aircraft via the radio transmitter.
However, early sonobuoys that consisted of a single, omnidirectional hydrophone were limited in range and effectiveness. In 1964, Dr Alan Butement, the first Chief Scientist within the Department of Supply, proposed a much more sophisticated concept for a 'directional' sonobuoy, along with Henry d'Assumpcao, later Chief Defence Scientist. Both took out the original patent.
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1979 Press Release - Extract from Killen, J (Minister of Defence) 1979, Export marketing contract for Australian anti-submarine weapon, press release, June 8.
Although Butement and d'Assumpcao conceived of the original idea, its realisation depended on a huge amount work by a vast number of engineers. The Weapons Systems Research Laboratory of the Weapons Research Establishment (which became part of what is now Defence Science and Technology Group) began work on the Barra project, initially known as the Nangana Project, in 1964. Their task was to develop a new sonobuoy system, consisting of multiple hydrophones arranged in a horizontal plane, that could be deployed from aircraft and helicopters to detect, locate and classify quiet submarines and surface ships. This new design provided an improvement on the previous technology through more accurate detection and localisation.
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Schematic of the Barra sonobuoy
Like its predecessors, the Barra sonobuoy consisted of two parts: a surface float and a sub-surface component that separated on impact with the water after being deployed from an aircraft. The sub-surface component was the Sonobuoy Launch Canister, which was essentially a 1200mm long tube with a diameter of 120mm, which was ejected out of the maritime patrol aircraft using a small explosive source called a CAD (Command Activated Device).
It deployed a small drogue (parachute) to ensure the buoy entered the water correctly. Upon entering the water, a saltwater battery was activated, setting in motion the deployment of both the horizontal acoustic receiver array down to a pre-set depth, and the radio-frequency transmitter that floated on the surface. The acoustic receiver array (originally envisaged as a cruciform array) consisted of 5 telescopic, radial arms that deployed once the buoy was submerged, with 5 hydrophones on each arm that would pick up relevant data and send it via the surface float to a sonics processor in an aircraft.
Two or more sonobuoys working together would allow for the detection of multiple noise sources and their direction of movement.
This gave the Barra a huge advantage over existing sonobuoys -- by having so many hydrophones, the incoming signal was amplified by as much as 14dB, and the processing system could accurately determine the direction of the incoming signal, down to a couple of degrees.
While the concept was straight forward, the engineering task that followed was definitely not. A detector array of several metres in diameter had to be arranged inside a small canister along with sophisticated microelectronics, which could withstand being dropped from a great height, as well as being immersed in water at sometimes close to freezing temperatures.
In the initial development, an underwater test facility was established in South Australia, and the trials undertaken there led to an improved, more efficient sonobuoy model. In 1967, sea trials were completed in St Vincent's Gulf, South Australia and later off Jervis Bay, New South Wales in close collaboration with the Royal Australian Navy and the Royal Australian Air Force.
The development of the Barra sonobuoy system included both the sonobuoy itself, which was designed and manufactured by Australian scientists, as well as a sonics processor – the AQS901 airborne computer, which picked up radio signals transmitted from the sonobuoy and processed them – designed, developed, and manufactured in the United Kingdom in accordance with an agreement made in 1975.
In 1977, Amalgamated Wireless Australasia Limited (AWA Ltd) was awarded the initial contract to produce Barra sonobuoys, and the first production Barra was presented to the United Kingdom's High Commissioner for Australia in 1980, marking the beginning of deliveries of Barra sonobuoys to United Kingdom and Australian Air Forces and Navies.
Over time, more than 56,000 sonobuoys were manufactured, earning Australia over $200 million in exports. The Barra sonobuoy is one of many stories that highlights our long history of innovation in Defence science over the last 115 years.
This article is one of series of articles celebrating 115 years of Defence science and technology. Defence science in Australia can be traced back to 1907 when Cecil Napier Hake was appointed Chemical Adviser to the Department of Defence. Today more than 2000 Defence scientists, engineers, IT specialists and technicians form the Defence Science and Technology Group responsible for providing scientific advice and high-tech solutions for Australia's Defence and national security agencies.
You stirred up some emotions with that post.
View attachment 25861
warships, submarines, uboats, passenger liners, sailing ships, fishing vessels, cargo ships, merchant ships, ship database
Website with searchable ship database about warships, passenger liners, merchant ships, photo galleries, technical details, stories, news and much more.www.maritimequest.com
An uncle I never got to meet.
View attachment 25862
No I appreciate it TG, made me think of him and others.Sorry about your uncle Rise, was not my intention to upset you, hope you are ok![]()
Cheers , DioThis isn't about AI - it's about the chemistry of the pixels.
Here are a couple of their pending applications:
US2022216418A1 COMPOUND AND PHOTOELECTRIC DEVICE, IMAGE SENSOR, AND ELECTRONIC DEVICE INCLUDING THE SAME
US2022220127A1 COMPOSITION FOR PHOTOELECTRIC DEVICE, AND PHOTOELECTRIC DEVICE, IMAGE SENSOR, AND ELECTRONIC DEVICE INCLUDING THE SAME
You're a bloody champion of a dad!Happy new year to all the brainiacs here. This year is shaping up nicely to be a good year for us, and if not there's always the next one. One thing is for sure, it will happen and I'm willing to wait. My holding is going nowhere and I've convinced the kids their shares we got them are long term. Hopefully the 50k shares each will set them up. Got them at 6c for them so the only way is up.
I dont contribute much here but appreciate the research many do and read daily.
May health and prosperity follow us all wherever we may be.
Bring on 2023
You're a bloody champion of a dad!
Why thank you Rise. Was method in my madness, if they had their own stash they wouldn't want mine lol. I didn't want to share
358? Is that one of the Ferrari’s you’ll be buying from the BRN profits?The first $50 note I've received this year in change has this serial number
Omen?
It's going to be a bloody good year for pure AI disruptive tech View attachment 25864
VideoCardz | Alder Lake | Raptor Lake | Meteor Lake |
---|---|---|---|
Intel Mainstream CPU Roadmap (RUMORED) | |||
Desktop Launch Date | Q4 2021 | Q4 2022 | Q4 2023 |
CPU Node | Intel 7 | Intel 7 | Intel 4 |
Big Core µArch | Golden Cove | Raptor Cove | Redwood Cove |
Small Core µArch | Gracemont | Gracemont | Crestmont |
Graphics µArch | Xe-LP | Xe-LP | Xe-LPG |
Max CPU Core Count | 16 (8C+8c) | 24 (8C+16c) | TBC |
Max GPU Core Count | 96 EU | 96 EU | 128-192 EU |
Desktop Socket | LGA1700 | LGA1700 | LGA 1851 |
Memory Support | DDR4/DDR5-4800 | DDR4/DDR5-5600 | DDR5 |
PCIe Gen | PCIe 5.0 | PCIe 5.0 | PCIe 5.0 |
Intel Core Series | 12th Gen Core | 13th Gen Core | 14th Gen Core |
Hi Fmf,Some slightly dated (well, last few months anyway) articles / news on Intel & SiFive over next couple posts.
Obviously, we know pretty much all the content but still think all worth a skim through at least IMO as can see various connections and where we can fit as well.
I read earlier FF reminding us of VCIX implementation on the X280 & WikiChip Fuse in Sept gives us a better insight.
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SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators
SiFive introduces a new high-performance coprocessor interface targeting custom accelerators; scores design wins from Google, NASA.fuse.wikichip.org
SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators
September 20, 2022 David Schor AI, AI Hardware Summit, Linley Processor Conference, neural processors, SiFive, Vector Coprocessor Interface Extension (VCIX)
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Last year SiFive introduced the Intelligence X280 processor, part of a new category of RISC-V processors for SiFive that aims at assisting AI and machine learning workloads.
Launched under the new family of processors called SiFive Intelligence, the X280 is the first core to cater to AI acceleration. At a high level, the X280 builds on top of their silicon-proven U7-series high-performance (Linux-capable) core. SiFive’s Intelligence X280 is somewhat of a unique processor from SiFive. Targetting ML workloads, its main feature point is both the new RISC-V Vector (RVV) Extension as well as SiFive Intelligence Extensions – the company’s own RISC-V custom-extension for handling ML workloads which includes fixed-point data types from 8-bits to 64-bits as well as 16-64 bit FP and the BFloat16 data type. On the RVV extension side, the X280 supports 512-bit vector register lengths, allowing variable length operations up to 512-bits.
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As we mentioned earlier, the X280 builds on SiFive’s successful U7-series core. This is a 64-bit RISC-V core supporting the RV64GCV ISA and extensions. It is an 8-stage dual-issue in-order pipeline. Each core features 32-KiB private L1 data and instruction caches as well as a private L2 cache.
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The RISC-V Vector extension is a variable length instruction set. For the X280, the core utilizes a 256b pipeline. In other words, both the vector ALU and load/store architecture data width is 256-bit, doing two operations per 512-bit register data. In addition to the vector extension, SiFive added the “Intelligence Extensions” part of the RISC-V custom extensions ISA support. SiFive didn’t go into any details as to what those extensions entail but did note that compared to the standard RISC-V Vector ISA, the Intelligence Extensions provide a 4-6x performance improvement in int8 (matmul) and bf16 operations.
One of the interesting things that SiFive has done is add that capability for automatic translations of Arm Neon vector code into RISC-V Vectors directly into their compiler. And while it may not produce the most optimal code, it’s a way to quickly and accurately move on Arm Neon code directly to SiFive’s RISC-V code. At last year’s Linley Processor Conference, According to Chris Lattner at Last year’s, SiFive’s then President of Engineering & Product group noted that SiFive itself has been using this feature to port a large number of software packages.
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Each of the X280 cores goes into an X280 Core Complex which supports up to a quad-core coherent multi-core cluster configuration. The core cluster can be fully scaled up in a configuration that consists of up to 4 clusters for a total of 16 cores. A system-level L3 cache made of 1 MiB banks (up to 8 MiB) is also supported. The system supports a rich number of ports for I/O and communication with other important sub-system components via the system matrix.
Vector Coprocessor Interface Extension (VCIX)
At the 2022 AI Hardware Summit, Krste Asanovic SiFive Co-Founder and Chief Architect introduced a new Vector Coprocessor Interface Extension (VCIX).
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As customer evaluation of the X280 went underway, SiFive say it started noticing new potential usage trends for the core. One such usage is not as the primary ML accelerator, but rather as a snappy side coprocessor/control processor with ML acceleration functionality. In other words, SiFive says it has noticed that companies were considering the X280 as a replacement coprocessor and control processor for their main SoC. Instead of rolling out their own sequencers and other controllers, the X280 proved a good potential replacement.
To assist customers with such applications, SiFive developed the new Vector Coprocessor Interface Extension (VCIX, pronounced “Vee-Six”). VCIX allows for tight coupling between the customer’s SoC/accelerator and the X280. For example, consider a hardware AI startup with a novel way of processing neural networks or one that has designed a very large computational engine. Instead of designing a custom sequencer or control unit, they can simply use the X280 as a drop-in replacement. With VCIX, they are given direct connections to the X280. The interface includes direct access into the vector unit and memory units as well as the instruction stream, allowing an external circuit to utilize the vector pipeline as well as directly access the caches and vector register file.
The capabilities of essentially modifying the X280 core are far beyond anything you can get from someone like Arm. In theory, you could have an accelerator processing its own custom instructions by doing operations on its own side and sending various tasks to the X280 (as a standard RISC-V operation) or directly execute various operations on the X280 vector unit by going directly to that unit. Alternatively, the VCIX interface can work backward by allowing for custom execution engines to be connected to X280 for various custom applications (e.g., FFTs, image signal processing, Matrix operations). That engine would then operate as if they are part of the X280, operating in and out of the X280’s own vector register file. In other words, VCIX essentially allows you to much better customize the X280 core with custom instructions and custom operations on top of a fully working RISC-V core capable of booting full Linux and supporting virtualization.
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The VCIX is a high-performance direct-coupling interface to the X280 and its instruction stream. To that end, Asanovic noted that on the X280 with the new VCIX interface, the X280 is capable of sending 1,024 bits over onto the accelerator/external component each cycle and retrieving 512 bits per cycle, every cycle sustained over the VCIX interface.
SiFive says that utilizing their Vector Coprocessor Interface Extension, various accesses and operations from outside can now be done in as low as single-digit cycles or 10s of cycles, instead of 100s of cycles from the normal cluster bus interfaces or memory mapped interfaces. Extremely low-cycle latency is important for developing computational circuits that are highly integrated with the X280.
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Google Accelerators
Cliff Young, Google TPU Architect, and MLPerf Co-Founder was also part of the SiFive announcement. As we’ve seen from other Google accelerators, their hardware team always looks to eliminate redundant work by utilizing off-the-shelf solutions if it doesn’t add any real value to design it themselves in-house.
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For their own TPU accelerators, beyond the inter-chip interconnect and their highly-refined Matrix Multiply Unit (MXU) which utilizes a systolic array, much of everything else is rather generic and not particularly unique to their chip. Young noted that when they started 9 years ago, they essentially built much of this from scratch, saying “scalar and vector technologies are relatively well-understood. Krste is one of the pioneers in the vector computing areas and has built beautiful machines that way. But should Google duplicate what Krste has already been doing? Should we be reinventing the wheel along with the Matrix Multiply and the interconnect we already have? We’d be much happier if the answer was ‘no’. If we can focus on the stuff that we do great and we can also reuse a general-purpose processor with a general-purpose software stack and integrate that into our future accelerators.” Young added, “the promise of VCIX is to get our accelerators and our general-purpose cores closer together; not far apart across something like a PCIe interface with 1000s of cycles of delay but right next to each other with just a few 100s of cycles through the on-chip path and down to 10s of cycles through direct vector register access.”
The SiFive-Google partnership announcement is one of several public announcements that took place over the past year. Last year SiFive announced that AI chip startup Tenstorrent will also make use of the X280 processor in its next-generation AI training and inference processors. Earlier this month, NASA announced that it has selected SiFive’s X280 cores for its next-generation High-Performance Spaceflight Computing (HPSC) processor. HPSC will utilize an 8-core X280 cluster along with 4 additional SiFive RISC-V cores to “deliver 100x the computational capability of today’s space computers”.