Another one where I'd love to see us piggybacked on SiFive & Intel into the Horse Creek next year especially given the other articles and strategy that Intel are looking to execute.
Given we are now part of the IFS & have a pre-existing relationship with SiFive, I actually wouldn't be surprised to maybe see us added to the Intel Pathfinder for Risc-V down the track.
Intel, SiFive demonstrated high-performance RISC-V Horse Creek development platform on Intel 4 Process.
fuse.wikichip.org
Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
October 7, 2022 David Schor Cadence,
Intel,
Intel 4,
Intel Foundry Services (IFS),
Intel Innovation 2022,
RISC-V,
SiFive,
Synopsys
Last year Intel announced the development of the Horse Creek Platform, a partnership with SiFive for the development of a new high-performance RISC-V development system as part of both the company’s Intel Foundry Services (IFS) and their effort to catalyze the adoption of RISC-V. The boards were said to be a continuation of SiFive’s own HiFive development boards designed to grow the RISC-V ecosystem and accelerate prototyping.
Early this year Intel also announced the IFS Accelerator ecosystem alliance designed to help accelerate chip prototyping and tape-outs through deep collaboration with various semiconductor partners across EDA, IPs, and design services. IFS Accelerator is a comprehensive suite of tools comprising silicon-verified Intel-process-specific optimized IP portfolio (from std cell library, memory, GP I/O, analog, and I/F IPs). Strategically, A large and vibrant ecosystem will be incredibly important for the success of Intel’s foundry strategy and IFS Accelerator is one of a piece of that. The company initially started Accelerator in September of 2021 to assist the automotive industry with transitioning to more advanced nodes, however, it has since broadened its effort into other segments.
It’s worth noting that SiFive is a member of the IFS Accelerator, saying “SiFive will enable IFS customers to create computing platforms featuring RISC-V, optimized for their market applications. Intel’s broad portfolio of IP compliments the SiFive portfolio of performance-driven processor IP such as the SiFive Intelligence and SiFive Performance families of processor IP.”
Horse Creek
At the recent Intel Innovation 2022 Developer Conference, the company demoed Horse Creek for the first time in public. Horse Creek is a Raspberry Pi-inspired RISC-V software development board. It’s physically quite a bit larger due to a large number of integrated interfaces. For example, there’s 8 GiB of DDR5. PCIe 5.0 slot. SPI Flash contains the U-Boot, and a myriad of other monitoring and debugging interfaces.
Within 18 months, Horse Creek went from an announcement to a fully working A0 stepping chip running Linux. Manufactured on the company’s
most advanced Intel 4 process, the die measures just 4 mm by 4 mm and is packaged in a 19 mm x 19 mm BGA package. The chip intends to also demonstrate the interoperability of 3rd-party controllers and IPs along with Intel’s own hard IP PHYs. As such the SoC itself integrates a number of advanced interfaces.
The SoC itself integrates quad-core SiFive P550 RISC-V cores. Each core features private L1 and L2 caches with a shared last-level cache – all operating at 2.2 GHz. At the time of tape out those were the highest-performance RISC-V cores. Note that since SiFive actually announced next-generation P650 cores, surpassing them in performance. The SoC integrates Intel’s own PCIe 5.0 PHY with x8 lanes along with Synopsys PCIe 5 Controller. It also integrates Intel’s DDR5 PHYs supporting 5600 MT/s rates along with Cadence’s memory controller. Other Intel’s own Intel 4 IPs include 2 MiB of shared SRAM (part of their memory compiler), process monitor, caches, Power/Clock/PLLs, electronic fuses, JTAG, and various cell libraries.
Horse Creek boots up Linux, and Intel demonstrated the chip executing a video game (running on the CPUs as there is no GPU) along with various other applications (media player, playback, browser, etc).
Pathfinder for RISC-V
About a month ago Intel also announced Intel Pathfinder for RISC-V, a rapid prototyping development environment for system integrators. Essentially, it’s a suite of IPs, middleware, open-source, and 3rd party tools along with OS support designed to simplify the exploration of pre-silicon RISC-V-based designs. Intel said it is partnering with commercial and open-source RISC-V IP providers to enable a consistent environment for software development across different RISC-V-based processors. On the commercial side, RISC-V core IPs include those from Andes, Codasip, SiFive, MIPS, and others. Pathfinder includes a number of FPGA platforms for RISC-V chip emulations. The starter edition utilizes the Terasic Developer Kit for Intel Pathfinder while the commercial tools include boards
based on the Stratix 10 GX for full chip emulation capabilities.
No availability date for the new Horse Creek Dev boards has been announced yet.
Just something a little more recent on Pathfinder for more background.
Hope we get a berth.
I see Renesas in the mix too.
Intel simplifies access to Pathfinder for RISC-V and adds 14 new partners
December 8, 2022
Nitin Dahad
Intel Pathfinder for RISC-V merges Starter and Professional editions to ease user transitions, and 14 new ecosystem partners are added.
Intel has simplified access to its
Pathfinder for RISC-V initiative by unifying its starter and professional editions and added 14 new ecosystem partners with an array of new features, taking the total number of industry partners to 33.
Designed for SoC architects and system software developers, Intel Pathfinder for RISC-V is a pre-silicon development environment that supports IP selection via testing for compatibility and performance, as well as early-stage software development using Intel FPGA and simulator platforms. Previously users had to select which edition they wanted, but now it has unified its Starter and Professional editions. Intel said this merger into a single product is to ease user transitions; individual users can download the new version with its enhanced features, and commercial developers can use the same version and request custom extensions for vendor-specific capabilities required for their projects.
The new features include:
- Static kernel debug for users wanting to debug the Linux kernel.
- Multi-core support via SMP Linux.
- A new FMC add-on board available in Q1’23 using Intel Stratix 10 GX FPGA development board enabling new I/O interfaces and simplifying connectivity.
- A new Intel Cyclone 10 GX FPGA development board to be supported in Q1’23, enabling lower cost and additional flexibility.
Intel’s general manager for RISC-V Ventures, Vijay Krishnan, said to embedded.com, “Since the launch of Intel Pathfinder for RISC-V, we have added 14 new ecosystem partners to strengthen the initiative for a total of 33 industry partners. Furthermore, we are starting to see the value of Intel Pathfinder for RISC-V flow downstream from pre-silicon development to silicon. Examples from today’s announcement are the regenerative agriculture solution (using Renesas RISC-V SoC) and the decision of EMASS to sample their silicon BSP with our IDE. PES University in India is using our product to train students, Codasip is incorporating us in their university program, and UC Santa Barbara is driving innovative manycore designs with Intel Pathfinder. So our presence in academia and research is also growing.”
He added, “While we cannot share specific numbers, we are on course to hitting our internal goals for the total number of downloads for 2022. The current momentum gives us great impetus in terms of adding more capabilities and customers in 2023. Maintaining a torrid pace of execution and fostering ecosystem collaboration are key imperatives for Intel Pathfinder for RISC-V.”
Intel’s chief strategy officer and senior vice-president, Saf Yeboah, said, “Intel Pathfinder for RISC-V highlights Intel’s strategic investments in accelerating the adoption of open architectures, with the ultimate goal of creating greater value and choice for end-users.”
Ecosystem partners add new features
Open-source simulator supporting a breadth of RISC-V models
Antmicro and Intel’s cooperation enables easier architectural exploration and pre-silicon development by providing vector instruction-capable RISC-V platform simulation in Renode for Intel Pathfinder in early 2023. Renode is an open-source software development framework with commercial support from Antmicro that allows development, debug and test of multi-node device systems reliably, scalably and effectively. Tim Ansell, a software engineer at Google, said,
“Renode gives you the ability to do a lot of work on real-world objects without ever having to have any hardware. It allows you to have continuous integration systems which run very comprehensive test suites without having to set up bespoke hardware CI systems. This makes it a powerful framework for testing, and in fact it has enabled significantly more insight into product development.”
New floating-point unit for RISC-V cores
CalligoTech has designed posit numeric unit (PNU) IP, a coprocessor for real-number computations using POSITs – a new number system with higher accuracy and better dynamic range, at reduced power. Within the Intel Pathfinder for RISC-V developer environment, the company will enable its PNU with CORE-V CVA6 cores and enhanced RISC-V Compilers (C/C++/gFortran).
Enhanced audio capabilities for hearables, wearables and smart home devices
CEVA announced that its CEVA-BX1 and CEVA-BX2 audio DSP IP will be available with Intel Pathfinder for RISC-V in the Q1’23 timeframe, enabling customers to evaluate best-in-class DSP and audio front-end software IPs from CEVA combined with RISC-V based host platforms.
Bringing RISC-V cores and tools to education institutes
Codasip is collaborating with Intel to enable undergraduate and graduate level courses that will benefit from Codasip RISC-V IP and Intel Pathfinder for RISC-V. The goal is to be integrated into courses at multiple universities in the fall of 2023.
Ultra-low power SoC for AIoT
Embedded A.I. Systems (EMASS) has announced its intent to deliver engineering samples of the edge AI SoC named ECS-DoT in Q1’23. Its board support package (BSP) integrates Intel Pathfinder for RISC-V IDE and combined with the ultra-low power consumption of our SOC, could potentially unlock new capabilities and use cases for customers in the AIoT segment.
Combining RISC-V with neuromorphic accelerators
General Vision has combined its NeuroMem technology with RISC-V host processors and Intel Pathfinder for RISC-V developer tools to enable next generation real time learning pattern recognition featuring low latency and ultra-low power.
RISC-V cores and SoC reference designs for efficient scaling
G S Madhusudan, CEO & co-founder, InCore Semiconductors, said, “As we roll-out a comprehensive range of RISC-V commercial we see a synergistic opportunity to use Intel Pathfinder for RISC-V as the IDE that will enable our customers and SoC design partners to scale efficiently. InCore is keen to grow this collaboration with Intel to take full advantage of the massive customer interest in RISC-V based SOCs by providing a comprehensive, class leading development environment.”
Solution for regenerative agriculture
LATERAL.systems is applying innovative edge solutions utilizing AI-driven predictive analytics in supporting regenerative agriculture to provide farmers rich data insights that enable food safety, optimal crop quality and higher yields. Combining LATERAL’s edge platform application-level capabilities with IOTech middleware, RISC-V silicon and Intel Pathfinder for RISC-V, the company plans to field test its solution targeting the indoor farming community in 2023. IOTech has been working with Intel Pathfinder for RISC-V since its launch.
Renesas is providing customers a new option of RISC-V based MPU with RZ/Five, ideal for use cases such as industrial gateways and controllers. Andes said Intel Pathfinder for RISC-V enables its customers’ software development using open-source tools, FPGA platforms for early SoC development and verification, and easy migration path from FPGA to ASIC via Intel Foundry Services.
RISC-V within the engineering curriculum
PES University, a teaching and research institute in India, has already revamped the computer architecture course within the undergraduate program to be entirely on RISC-V. PES is also partnering with Intel to enable its students to use Intel Pathfinder for RISC-V as a development tool.
RISC-V design services
Prodapt has joined Intel’s ecosystem by actively promoting Intel Pathfinder for RISC-V as a developer tool for its design services customers.
USB controller for Intel Pathfinder for RISC-V
System Level Solutions (SLS) announced support for Intel Pathfinder for RISC-V via its USB host and device controller IP for the Intel Cyclone 10 GX development board, which is a recent addition to the family of Intel FPGA boards supported by Intel Pathfinder for RISC-V. SLS hopes to expand this relationship over time by providing peripheral IP that will accelerate the adoption of RISC-V across FPGA and ASIC designs.
RISC-V reference designs
Tessolve is working to enable its first RISC-V based SOC reference design in early 2023, using Intel Pathfinder for RISC-V as the preferred development environment. Tessolve said it would work with Intel to implement these reference designs to drive cost-effective and rapid scaling of RISC-V based designs.
Exploring CORE-V CVA6 open-source manycore RISC-V architectures
The University of California Santa Barbara is collaborating with Intel within the OpenHW ecosystem on research that will enable octa-core and higher configurations of the open-source CORE-V CVA6 RISC-V cores with Intel Pathfinder for RISC-V. Over time, it expects this work will benefit RISC-V developers across academia, research, and commercial organizations
those kids are going to be nicely set up with those parcels in the future. You're a good Dad 
