Getupthere
Regular
Meet with BrainChip Inc. @ CES 2023 - BrainChip Inc
Meet with BrainChip Inc. to discuss how the technology can benefit your company or organization.
BRN Discussion Ongoing
- Thread starter TechGirl
- Start date
Make sure your kids get the white balloons if @Fact Finder is at the party.
Rise from the ashes
Regular
You stirred up some emotions with that post.A little bit of Australian history on our Department of Defence Barra Sonobuoy invention, hopefully we will be in future models as it uses hydrophones, acoustics, radio signals etc, I really enjoyed the article and it makes me proud to be Australian
The Barra Sonobuoy: the Australian invention that makes it harder for subs to hide
The Barra sonobuoy is one of Australia's most successful Defence joint development projects, and highlights Australia's history as a global leader in the development and manufacture of advanced technologies.www.dst.defence.gov.au
THE BARRA SONOBUOY: THE AUSTRALIAN INVENTION THAT MAKES IT HARDER FOR SUBS TO HIDE
5 December 2022
NEWS
The Barra sonobuoy is one of Australia's most successful Defence joint development projects, and highlights Australia's history as a global leader in the development and manufacture of advanced technologies.
Sonobuoys were first developed and used at the end of World War II in response to the devastating destruction of allied merchant ships in the Atlantic caused by German U-boats.
The ability to locate submarines so they could be sunk, or prevented from attacking, became critical for the Allied war effort, and so the idea of the 'buoy sonar' was born. The idea was simple: a sonobuoy was dropped into the water by passing aircraft and, upon impact, an underwater acoustic sensor (hydrophone) and floating radio transmitter would deploy. Any underwater acoustic signals detected by the hydrophone, caused by a nearby U-boat for example, would then be relayed to the aircraft via the radio transmitter.
However, early sonobuoys that consisted of a single, omnidirectional hydrophone were limited in range and effectiveness. In 1964, Dr Alan Butement, the first Chief Scientist within the Department of Supply, proposed a much more sophisticated concept for a 'directional' sonobuoy, along with Henry d'Assumpcao, later Chief Defence Scientist. Both took out the original patent.
1979 Press Release - Extract from Killen, J (Minister of Defence) 1979, Export marketing contract for Australian anti-submarine weapon, press release, June 8.
Although Butement and d'Assumpcao conceived of the original idea, its realisation depended on a huge amount work by a vast number of engineers. The Weapons Systems Research Laboratory of the Weapons Research Establishment (which became part of what is now Defence Science and Technology Group) began work on the Barra project, initially known as the Nangana Project, in 1964. Their task was to develop a new sonobuoy system, consisting of multiple hydrophones arranged in a horizontal plane, that could be deployed from aircraft and helicopters to detect, locate and classify quiet submarines and surface ships. This new design provided an improvement on the previous technology through more accurate detection and localisation.
Schematic of the Barra sonobuoy
Like its predecessors, the Barra sonobuoy consisted of two parts: a surface float and a sub-surface component that separated on impact with the water after being deployed from an aircraft. The sub-surface component was the Sonobuoy Launch Canister, which was essentially a 1200mm long tube with a diameter of 120mm, which was ejected out of the maritime patrol aircraft using a small explosive source called a CAD (Command Activated Device).
It deployed a small drogue (parachute) to ensure the buoy entered the water correctly. Upon entering the water, a saltwater battery was activated, setting in motion the deployment of both the horizontal acoustic receiver array down to a pre-set depth, and the radio-frequency transmitter that floated on the surface. The acoustic receiver array (originally envisaged as a cruciform array) consisted of 5 telescopic, radial arms that deployed once the buoy was submerged, with 5 hydrophones on each arm that would pick up relevant data and send it via the surface float to a sonics processor in an aircraft.
Two or more sonobuoys working together would allow for the detection of multiple noise sources and their direction of movement.
This gave the Barra a huge advantage over existing sonobuoys -- by having so many hydrophones, the incoming signal was amplified by as much as 14dB, and the processing system could accurately determine the direction of the incoming signal, down to a couple of degrees.
While the concept was straight forward, the engineering task that followed was definitely not. A detector array of several metres in diameter had to be arranged inside a small canister along with sophisticated microelectronics, which could withstand being dropped from a great height, as well as being immersed in water at sometimes close to freezing temperatures.
In the initial development, an underwater test facility was established in South Australia, and the trials undertaken there led to an improved, more efficient sonobuoy model. In 1967, sea trials were completed in St Vincent's Gulf, South Australia and later off Jervis Bay, New South Wales in close collaboration with the Royal Australian Navy and the Royal Australian Air Force.
The development of the Barra sonobuoy system included both the sonobuoy itself, which was designed and manufactured by Australian scientists, as well as a sonics processor – the AQS901 airborne computer, which picked up radio signals transmitted from the sonobuoy and processed them – designed, developed, and manufactured in the United Kingdom in accordance with an agreement made in 1975.
In 1977, Amalgamated Wireless Australasia Limited (AWA Ltd) was awarded the initial contract to produce Barra sonobuoys, and the first production Barra was presented to the United Kingdom's High Commissioner for Australia in 1980, marking the beginning of deliveries of Barra sonobuoys to United Kingdom and Australian Air Forces and Navies.
Over time, more than 56,000 sonobuoys were manufactured, earning Australia over $200 million in exports. The Barra sonobuoy is one of many stories that highlights our long history of innovation in Defence science over the last 115 years.
This article is one of series of articles celebrating 115 years of Defence science and technology. Defence science in Australia can be traced back to 1907 when Cecil Napier Hake was appointed Chemical Adviser to the Department of Defence. Today more than 2000 Defence scientists, engineers, IT specialists and technicians form the Defence Science and Technology Group responsible for providing scientific advice and high-tech solutions for Australia's Defence and national security agencies.
warships, submarines, uboats, passenger liners, sailing ships, fishing vessels, cargo ships, merchant ships, ship database
Website with searchable ship database about warships, passenger liners, merchant ships, photo galleries, technical details, stories, news and much more.
www.maritimequest.com
An uncle I never got to meet.
TechGirl
Founding Member
Sorry about your uncle Rise, was not my intention to upset you, hope you are ok
Rise from the ashes
Regular
No I appreciate it TG, made me think of him and others.Sorry about your uncle Rise, was not my intention to upset you, hope you are ok
This isn't about AI - it's about the chemistry of the pixels.
Here are a couple of their pending applications:
US2022216418A1 COMPOUND AND PHOTOELECTRIC DEVICE, IMAGE SENSOR, AND ELECTRONIC DEVICE INCLUDING THE SAME
US2022220127A1 COMPOSITION FOR PHOTOELECTRIC DEVICE, AND PHOTOELECTRIC DEVICE, IMAGE SENSOR, AND ELECTRONIC DEVICE INCLUDING THE SAME
Tothemoon24
Top 20
Cheers , Dio
Happy New Year All,
CES is very close now, this may have already been mentioned, but for the ones who aren't aware, Major Exhibitors will
be hosting Press Events on 3 & 4 January, prior to the event proper from 5 to 8 January, remembering the time difference
with the Pacific, it'll be the early hours (between Midnight and 3am) the following day West to East Coasts of Australia.
25% of all floor space at this event is taken up by Automobile Companies, what an event to attend, if any US shareholders
are attending please inform the forum, much appreciated.
Regards, The Texta
CES is very close now, this may have already been mentioned, but for the ones who aren't aware, Major Exhibitors will
be hosting Press Events on 3 & 4 January, prior to the event proper from 5 to 8 January, remembering the time difference
with the Pacific, it'll be the early hours (between Midnight and 3am) the following day West to East Coasts of Australia.
25% of all floor space at this event is taken up by Automobile Companies, what an event to attend, if any US shareholders
are attending please inform the forum, much appreciated.
Regards, The Texta
Dozzaman1977
Regular
The first $50 note I've received this year in change has this serial number
Omen?
It's going to be a bloody good year for pure AI disruptive tech
Omen?
It's going to be a bloody good year for pure AI disruptive tech
Fredsnugget
Regular
Happy new year to all the brainiacs here. This year is shaping up nicely to be a good year for us, and if not there's always the next one. One thing is for sure, it will happen and I'm willing to wait. My holding is going nowhere and I've convinced the kids their shares we got them are long term. Hopefully the 50k shares each will set them up. Got them at 6c for them so the only way is up.
I dont contribute much here but appreciate the research many do and read daily.
May health and prosperity follow us all wherever we may be.
Bring on 2023
I dont contribute much here but appreciate the research many do and read daily.
May health and prosperity follow us all wherever we may be.
Bring on 2023
Rise from the ashes
Regular
You're a bloody champion of a dad!
Meetupsoon
Member
Something to think about, maybe:
The Dark Side of AI: A Warning from Jordan Peterson (scary truth about ChatGPT)
Fullmoonfever
Top 20
Some slightly dated (well, last few months anyway) articles / news on Intel & SiFive over next couple posts.
Obviously, we know pretty much all the content but still think all worth a skim through at least IMO as can see various connections and where we can fit as well.
I read earlier FF reminding us of VCIX implementation on the X280 & WikiChip Fuse in Sept gives us a better insight.
fuse.wikichip.org
Last year SiFive introduced the Intelligence X280 processor, part of a new category of RISC-V processors for SiFive that aims at assisting AI and machine learning workloads.
Launched under the new family of processors called SiFive Intelligence, the X280 is the first core to cater to AI acceleration. At a high level, the X280 builds on top of their silicon-proven U7-series high-performance (Linux-capable) core. SiFive’s Intelligence X280 is somewhat of a unique processor from SiFive. Targetting ML workloads, its main feature point is both the new RISC-V Vector (RVV) Extension as well as SiFive Intelligence Extensions – the company’s own RISC-V custom-extension for handling ML workloads which includes fixed-point data types from 8-bits to 64-bits as well as 16-64 bit FP and the BFloat16 data type. On the RVV extension side, the X280 supports 512-bit vector register lengths, allowing variable length operations up to 512-bits.
As we mentioned earlier, the X280 builds on SiFive’s successful U7-series core. This is a 64-bit RISC-V core supporting the RV64GCV ISA and extensions. It is an 8-stage dual-issue in-order pipeline. Each core features 32-KiB private L1 data and instruction caches as well as a private L2 cache.
The RISC-V Vector extension is a variable length instruction set. For the X280, the core utilizes a 256b pipeline. In other words, both the vector ALU and load/store architecture data width is 256-bit, doing two operations per 512-bit register data. In addition to the vector extension, SiFive added the “Intelligence Extensions” part of the RISC-V custom extensions ISA support. SiFive didn’t go into any details as to what those extensions entail but did note that compared to the standard RISC-V Vector ISA, the Intelligence Extensions provide a 4-6x performance improvement in int8 (matmul) and bf16 operations.
One of the interesting things that SiFive has done is add that capability for automatic translations of Arm Neon vector code into RISC-V Vectors directly into their compiler. And while it may not produce the most optimal code, it’s a way to quickly and accurately move on Arm Neon code directly to SiFive’s RISC-V code. At last year’s Linley Processor Conference, According to Chris Lattner at Last year’s, SiFive’s then President of Engineering & Product group noted that SiFive itself has been using this feature to port a large number of software packages.
Each of the X280 cores goes into an X280 Core Complex which supports up to a quad-core coherent multi-core cluster configuration. The core cluster can be fully scaled up in a configuration that consists of up to 4 clusters for a total of 16 cores. A system-level L3 cache made of 1 MiB banks (up to 8 MiB) is also supported. The system supports a rich number of ports for I/O and communication with other important sub-system components via the system matrix.
As customer evaluation of the X280 went underway, SiFive say it started noticing new potential usage trends for the core. One such usage is not as the primary ML accelerator, but rather as a snappy side coprocessor/control processor with ML acceleration functionality. In other words, SiFive says it has noticed that companies were considering the X280 as a replacement coprocessor and control processor for their main SoC. Instead of rolling out their own sequencers and other controllers, the X280 proved a good potential replacement.
To assist customers with such applications, SiFive developed the new Vector Coprocessor Interface Extension (VCIX, pronounced “Vee-Six”). VCIX allows for tight coupling between the customer’s SoC/accelerator and the X280. For example, consider a hardware AI startup with a novel way of processing neural networks or one that has designed a very large computational engine. Instead of designing a custom sequencer or control unit, they can simply use the X280 as a drop-in replacement. With VCIX, they are given direct connections to the X280. The interface includes direct access into the vector unit and memory units as well as the instruction stream, allowing an external circuit to utilize the vector pipeline as well as directly access the caches and vector register file.
The capabilities of essentially modifying the X280 core are far beyond anything you can get from someone like Arm. In theory, you could have an accelerator processing its own custom instructions by doing operations on its own side and sending various tasks to the X280 (as a standard RISC-V operation) or directly execute various operations on the X280 vector unit by going directly to that unit. Alternatively, the VCIX interface can work backward by allowing for custom execution engines to be connected to X280 for various custom applications (e.g., FFTs, image signal processing, Matrix operations). That engine would then operate as if they are part of the X280, operating in and out of the X280’s own vector register file. In other words, VCIX essentially allows you to much better customize the X280 core with custom instructions and custom operations on top of a fully working RISC-V core capable of booting full Linux and supporting virtualization.
The VCIX is a high-performance direct-coupling interface to the X280 and its instruction stream. To that end, Asanovic noted that on the X280 with the new VCIX interface, the X280 is capable of sending 1,024 bits over onto the accelerator/external component each cycle and retrieving 512 bits per cycle, every cycle sustained over the VCIX interface.
SiFive says that utilizing their Vector Coprocessor Interface Extension, various accesses and operations from outside can now be done in as low as single-digit cycles or 10s of cycles, instead of 100s of cycles from the normal cluster bus interfaces or memory mapped interfaces. Extremely low-cycle latency is important for developing computational circuits that are highly integrated with the X280.
For their own TPU accelerators, beyond the inter-chip interconnect and their highly-refined Matrix Multiply Unit (MXU) which utilizes a systolic array, much of everything else is rather generic and not particularly unique to their chip. Young noted that when they started 9 years ago, they essentially built much of this from scratch, saying “scalar and vector technologies are relatively well-understood. Krste is one of the pioneers in the vector computing areas and has built beautiful machines that way. But should Google duplicate what Krste has already been doing? Should we be reinventing the wheel along with the Matrix Multiply and the interconnect we already have? We’d be much happier if the answer was ‘no’. If we can focus on the stuff that we do great and we can also reuse a general-purpose processor with a general-purpose software stack and integrate that into our future accelerators.” Young added, “the promise of VCIX is to get our accelerators and our general-purpose cores closer together; not far apart across something like a PCIe interface with 1000s of cycles of delay but right next to each other with just a few 100s of cycles through the on-chip path and down to 10s of cycles through direct vector register access.”
The SiFive-Google partnership announcement is one of several public announcements that took place over the past year. Last year SiFive announced that AI chip startup Tenstorrent will also make use of the X280 processor in its next-generation AI training and inference processors. Earlier this month, NASA announced that it has selected SiFive’s X280 cores for its next-generation High-Performance Spaceflight Computing (HPSC) processor. HPSC will utilize an 8-core X280 cluster along with 4 additional SiFive RISC-V cores to “deliver 100x the computational capability of today’s space computers”.
Obviously, we know pretty much all the content but still think all worth a skim through at least IMO as can see various connections and where we can fit as well.
I read earlier FF reminding us of VCIX implementation on the X280 & WikiChip Fuse in Sept gives us a better insight.
SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators
SiFive introduces a new high-performance coprocessor interface targeting custom accelerators; scores design wins from Google, NASA.
fuse.wikichip.org
SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators
September 20, 2022 David Schor AI, AI Hardware Summit, Linley Processor Conference, neural processors, SiFive, Vector Coprocessor Interface Extension (VCIX)
Last year SiFive introduced the Intelligence X280 processor, part of a new category of RISC-V processors for SiFive that aims at assisting AI and machine learning workloads.
Launched under the new family of processors called SiFive Intelligence, the X280 is the first core to cater to AI acceleration. At a high level, the X280 builds on top of their silicon-proven U7-series high-performance (Linux-capable) core. SiFive’s Intelligence X280 is somewhat of a unique processor from SiFive. Targetting ML workloads, its main feature point is both the new RISC-V Vector (RVV) Extension as well as SiFive Intelligence Extensions – the company’s own RISC-V custom-extension for handling ML workloads which includes fixed-point data types from 8-bits to 64-bits as well as 16-64 bit FP and the BFloat16 data type. On the RVV extension side, the X280 supports 512-bit vector register lengths, allowing variable length operations up to 512-bits.
As we mentioned earlier, the X280 builds on SiFive’s successful U7-series core. This is a 64-bit RISC-V core supporting the RV64GCV ISA and extensions. It is an 8-stage dual-issue in-order pipeline. Each core features 32-KiB private L1 data and instruction caches as well as a private L2 cache.
The RISC-V Vector extension is a variable length instruction set. For the X280, the core utilizes a 256b pipeline. In other words, both the vector ALU and load/store architecture data width is 256-bit, doing two operations per 512-bit register data. In addition to the vector extension, SiFive added the “Intelligence Extensions” part of the RISC-V custom extensions ISA support. SiFive didn’t go into any details as to what those extensions entail but did note that compared to the standard RISC-V Vector ISA, the Intelligence Extensions provide a 4-6x performance improvement in int8 (matmul) and bf16 operations.
One of the interesting things that SiFive has done is add that capability for automatic translations of Arm Neon vector code into RISC-V Vectors directly into their compiler. And while it may not produce the most optimal code, it’s a way to quickly and accurately move on Arm Neon code directly to SiFive’s RISC-V code. At last year’s Linley Processor Conference, According to Chris Lattner at Last year’s, SiFive’s then President of Engineering & Product group noted that SiFive itself has been using this feature to port a large number of software packages.
Each of the X280 cores goes into an X280 Core Complex which supports up to a quad-core coherent multi-core cluster configuration. The core cluster can be fully scaled up in a configuration that consists of up to 4 clusters for a total of 16 cores. A system-level L3 cache made of 1 MiB banks (up to 8 MiB) is also supported. The system supports a rich number of ports for I/O and communication with other important sub-system components via the system matrix.
Vector Coprocessor Interface Extension (VCIX)
At the 2022 AI Hardware Summit, Krste Asanovic SiFive Co-Founder and Chief Architect introduced a new Vector Coprocessor Interface Extension (VCIX).
As customer evaluation of the X280 went underway, SiFive say it started noticing new potential usage trends for the core. One such usage is not as the primary ML accelerator, but rather as a snappy side coprocessor/control processor with ML acceleration functionality. In other words, SiFive says it has noticed that companies were considering the X280 as a replacement coprocessor and control processor for their main SoC. Instead of rolling out their own sequencers and other controllers, the X280 proved a good potential replacement.
To assist customers with such applications, SiFive developed the new Vector Coprocessor Interface Extension (VCIX, pronounced “Vee-Six”). VCIX allows for tight coupling between the customer’s SoC/accelerator and the X280. For example, consider a hardware AI startup with a novel way of processing neural networks or one that has designed a very large computational engine. Instead of designing a custom sequencer or control unit, they can simply use the X280 as a drop-in replacement. With VCIX, they are given direct connections to the X280. The interface includes direct access into the vector unit and memory units as well as the instruction stream, allowing an external circuit to utilize the vector pipeline as well as directly access the caches and vector register file.
The capabilities of essentially modifying the X280 core are far beyond anything you can get from someone like Arm. In theory, you could have an accelerator processing its own custom instructions by doing operations on its own side and sending various tasks to the X280 (as a standard RISC-V operation) or directly execute various operations on the X280 vector unit by going directly to that unit. Alternatively, the VCIX interface can work backward by allowing for custom execution engines to be connected to X280 for various custom applications (e.g., FFTs, image signal processing, Matrix operations). That engine would then operate as if they are part of the X280, operating in and out of the X280’s own vector register file. In other words, VCIX essentially allows you to much better customize the X280 core with custom instructions and custom operations on top of a fully working RISC-V core capable of booting full Linux and supporting virtualization.
The VCIX is a high-performance direct-coupling interface to the X280 and its instruction stream. To that end, Asanovic noted that on the X280 with the new VCIX interface, the X280 is capable of sending 1,024 bits over onto the accelerator/external component each cycle and retrieving 512 bits per cycle, every cycle sustained over the VCIX interface.
SiFive says that utilizing their Vector Coprocessor Interface Extension, various accesses and operations from outside can now be done in as low as single-digit cycles or 10s of cycles, instead of 100s of cycles from the normal cluster bus interfaces or memory mapped interfaces. Extremely low-cycle latency is important for developing computational circuits that are highly integrated with the X280.
Google Accelerators
Cliff Young, Google TPU Architect, and MLPerf Co-Founder was also part of the SiFive announcement. As we’ve seen from other Google accelerators, their hardware team always looks to eliminate redundant work by utilizing off-the-shelf solutions if it doesn’t add any real value to design it themselves in-house.
For their own TPU accelerators, beyond the inter-chip interconnect and their highly-refined Matrix Multiply Unit (MXU) which utilizes a systolic array, much of everything else is rather generic and not particularly unique to their chip. Young noted that when they started 9 years ago, they essentially built much of this from scratch, saying “scalar and vector technologies are relatively well-understood. Krste is one of the pioneers in the vector computing areas and has built beautiful machines that way. But should Google duplicate what Krste has already been doing? Should we be reinventing the wheel along with the Matrix Multiply and the interconnect we already have? We’d be much happier if the answer was ‘no’. If we can focus on the stuff that we do great and we can also reuse a general-purpose processor with a general-purpose software stack and integrate that into our future accelerators.” Young added, “the promise of VCIX is to get our accelerators and our general-purpose cores closer together; not far apart across something like a PCIe interface with 1000s of cycles of delay but right next to each other with just a few 100s of cycles through the on-chip path and down to 10s of cycles through direct vector register access.”
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The SiFive-Google partnership announcement is one of several public announcements that took place over the past year. Last year SiFive announced that AI chip startup Tenstorrent will also make use of the X280 processor in its next-generation AI training and inference processors. Earlier this month, NASA announced that it has selected SiFive’s X280 cores for its next-generation High-Performance Spaceflight Computing (HPSC) processor. HPSC will utilize an 8-core X280 cluster along with 4 additional SiFive RISC-V cores to “deliver 100x the computational capability of today’s space computers”.
Easytiger
Regular
Susan Burghart
By Don Clark and Ana Swanson
Don Clark reports on the semiconductor industry, and Ana Swanson reports on trade and international economics.
In September, the chip giant Intel gathered officials at a patch of land near Columbus, Ohio, where it pledged to invest at least $20 billion in two new factories to make semiconductors.
A month later, Micron Technology celebrated a new manufacturing site near Syracuse, N.Y., where the chip company expected to spend $20 billion by the end of the decade and eventually perhaps five times that.
And in December, Taiwan Semiconductor Manufacturing Company hosted a shindig in Phoenix, where it plans to triple its investment to $40 billion and build a second new factory to create advanced chips.
The pledges are part of an enormous ramp-up in U.S. chip-making plans over the past 18 months, the scale of which has been likened to Cold War-era investments in the Space Race.
U.S. Pours Money Into Chips, but Even Soaring Spending Has Limits
Amid a tech cold war with China, U.S. companies have pledged nearly $200 billion for chip manufacturing projects since early 2020. But the investments are not a silver bullet.By Don Clark and Ana Swanson
Don Clark reports on the semiconductor industry, and Ana Swanson reports on trade and international economics.
- Jan. 1, 2023
- 6 MIN READ
In September, the chip giant Intel gathered officials at a patch of land near Columbus, Ohio, where it pledged to invest at least $20 billion in two new factories to make semiconductors.
A month later, Micron Technology celebrated a new manufacturing site near Syracuse, N.Y., where the chip company expected to spend $20 billion by the end of the decade and eventually perhaps five times that.
And in December, Taiwan Semiconductor Manufacturing Company hosted a shindig in Phoenix, where it plans to triple its investment to $40 billion and build a second new factory to create advanced chips.
The pledges are part of an enormous ramp-up in U.S. chip-making plans over the past 18 months, the scale of which has been likened to Cold War-era investments in the Space Race.
Fullmoonfever
Top 20
This one from the WSJ earlier in the year gives an insight into what Intel want to achieve and can see how & why we popped up in the IFS.....pieces of their puzzle they are collecting.
www.wsj.com
By Asa Fitch
Follow
Updated April 9, 2022 12:01 am ET
Intel Corp. INTC 0.84%increase; green up pointing triangle is reworking its artificial-intelligence strategy as it tries to gain ground on Nvidia Corp., the leader in the market for chips designed to excel at AI computations.
Over the past year, under new chief executive Pat Gelsinger, Intel has added staff and introduced new AI software for its expanding lineup of chips to improve AI-driven chatbots, facial recognition and movie recommendations, among other applications.
Intel is known mainly for its dominance in the market for central processing units, the brains behind personal computers and the servers that run corporate networks and the internet. But it has lost some of its sheen for investors over the past decade as Nvidia gobbled up the market for chips specifically designed for AI purposes, especially chips that train AI models.
Nvidia now accounts for about 80% of revenue from AI-specific computation in big data centers, according to Informa PLC’s Omdia unit, a British research and consulting firm, although that doesn’t account for any AI calculations done on Intel’s general-purpose CPUs. That dominance in AI-specific chips helped Nvidia surpass Intel as the most valuable chip company in the U.S. by market capitalization two years ago.
AI chips are a relatively small but rapidly growing segment of the overall chip market. Rising demand for faster, more efficient AI computation has spawned dozens of chip startups, while the leading chip makers have invested heavily. The AI chip market was worth around $8 billion in 2020, but is expected to grow to nearly $200 billion by 2030, according to a report from Allied Market Research, based in Portland, Ore.
An array of so-called neuromorphic chips Intel is researching. They are built to mimic the structure of the human brain and could eventually be added to Intel’s AI offerings.PHOTO: JASON HENRY FOR THE WALL STREET JOURNAL
Intel’s strategy is to build a stable of chips and open-source software that covers a broad range of computing needs as AI becomes more prevalent. For instance, it could sell customers a package that would allow them to hand off some tasks to specialist chips that excel at things like image recognition, while handling other work on general-purpose chips.
Intel hopes the efficiency of that kind of division of labor could help companies optimize performance for their specific AI tasks and save money by cutting power consumption. That could make sense for customers that have a lot of data and do a lot of AI processing—big corporations and well-funded startups—although Intel also hopes to capture demand for AI computation through sales to the large cloud-computing providers and even products for individual consumers.
One important change Intel has made in pursuit of that strategy is the addition of graphics processing units to its product line. Unveiled more than two years ago, those chips could help it stack up better against Nvidia, which specializes in GPUs initially developed for computer gaming but adapted for machine-learning tasks. Intel in 2019 bought Israeli startup Habana Labs, which makes chips designed specifically for training AI models—systems that spit out realistic-sounding sentences, for example—and for generating output from those models.
Another change is in the way Intel knits together its AI products for customers.
“It isn’t even a question of do we have to invest more—we invest quite a bit in AI,” says Sandra Rivera, a longtime Intel executive whom Mr. Gelsinger tapped to head the data-center business and AI strategy last summer. “But we haven’t gotten the leverage of those investments when we have different strategies and different execution priorities” for various products.
Kavitha Prasad, vice president and general manager of data center, AI and cloud execution and strategy, at Intel headquarters.PHOTO: JASON HENRY FOR THE WALL STREET JOURNAL
Since taking her new role, Ms. Rivera has brought in several new executives, including Kavitha Prasad, who came from a machine-learning startup after an earlier stint at Intel. Ms. Prasad, who directly oversees the AI strategy, is leading a shift in focus she says is centered on using AI to reach customers’ business goals, rather than offering a menu of chips and letting customers figure out the rest.
“Intel has all these technologies, but what is bringing it together to make it cohesive from a customer perspective, so that the customers are able to deploy it at a much faster rate, so that they’re able to get to their business outcomes faster?” she says. “It is not about having the solutions, but it’s about meaningfully bringing them together to make it happen.”
Bringing it all together is largely the job of Intel’s software architects, led by Chief Technology Officer Greg Lavender, whom Mr. Gelsinger hired from VMware Inc., where Mr. Gelsinger was previously CEO.
Inside a data center at the Intel headquarters.PHOTO: JASON HENRY FOR THE WALL STREET JOURNAL
Success, of course, isn’t a sure thing. Nvidia, already far ahead of Intel and the rest of the competition, is moving quickly with its own chips, announcing a new generation of superfast processors in March. While analysts say Intel’s strategy could help make it a more formidable competitor to Nvidia, its ability to tap the AI market hinges on delivering AI-targeted chips and related software on schedule. Recent history suggests that could be a challenge. Intel has stumbled in chip-manufacturing technology in recent years, leaving it behind South Korea’s Samsung Electronics Co. and Taiwan Semiconductor Manufacturing Co. in the high-stakes race to make chips with the smallest transistors and best performance. Some of its latest CPU chips for servers have been delayed.
Mr. Gelsinger aims to reverse that trajectory by rededicating the company to manufacturing—he’s announced tens of billions of spending on new chip factories over the next several years—and building up a business making chips on contract according to others’ designs. Whether the company can execute on Mr. Gelsinger’s plan to retake the technological lead from its Asian competitors in the next few years is an open question.
“There are a lot of things they haven’t executed on over the last five or six years,” says Matt Bryson, an analyst at Wedbush Securities. “Clearly under Pat Gelsinger Intel is investing more in product development, and if you put more money into development, you should have a better ability to execute, but it comes back to how do you know until you are showing products and starting to see traction?”
Ms. Rivera says Intel is ready to make that leap. “We have the customer relationships, we have the market position, we have the unique differentiation—we just need to execute our strategy,” she says.
Inside Intel’s Strategy to Compete With Nvidia in the AI-Chip Market
Nvidia has dominated the growing artificial-intelligence business. Intel wants to change that.
www.wsj.com
Inside Intel’s Strategy to Compete With Nvidia in the AI-Chip Market
Nvidia has dominated the growing artificial-intelligence business. Intel wants to change that.
By Asa Fitch
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Updated April 9, 2022 12:01 am ET
Intel Corp. INTC 0.84%increase; green up pointing triangle is reworking its artificial-intelligence strategy as it tries to gain ground on Nvidia Corp., the leader in the market for chips designed to excel at AI computations.
Over the past year, under new chief executive Pat Gelsinger, Intel has added staff and introduced new AI software for its expanding lineup of chips to improve AI-driven chatbots, facial recognition and movie recommendations, among other applications.
Intel is known mainly for its dominance in the market for central processing units, the brains behind personal computers and the servers that run corporate networks and the internet. But it has lost some of its sheen for investors over the past decade as Nvidia gobbled up the market for chips specifically designed for AI purposes, especially chips that train AI models.
Nvidia now accounts for about 80% of revenue from AI-specific computation in big data centers, according to Informa PLC’s Omdia unit, a British research and consulting firm, although that doesn’t account for any AI calculations done on Intel’s general-purpose CPUs. That dominance in AI-specific chips helped Nvidia surpass Intel as the most valuable chip company in the U.S. by market capitalization two years ago.
AI chips are a relatively small but rapidly growing segment of the overall chip market. Rising demand for faster, more efficient AI computation has spawned dozens of chip startups, while the leading chip makers have invested heavily. The AI chip market was worth around $8 billion in 2020, but is expected to grow to nearly $200 billion by 2030, according to a report from Allied Market Research, based in Portland, Ore.
The plan
An array of so-called neuromorphic chips Intel is researching. They are built to mimic the structure of the human brain and could eventually be added to Intel’s AI offerings.PHOTO: JASON HENRY FOR THE WALL STREET JOURNAL
Intel’s strategy is to build a stable of chips and open-source software that covers a broad range of computing needs as AI becomes more prevalent. For instance, it could sell customers a package that would allow them to hand off some tasks to specialist chips that excel at things like image recognition, while handling other work on general-purpose chips.
Intel hopes the efficiency of that kind of division of labor could help companies optimize performance for their specific AI tasks and save money by cutting power consumption. That could make sense for customers that have a lot of data and do a lot of AI processing—big corporations and well-funded startups—although Intel also hopes to capture demand for AI computation through sales to the large cloud-computing providers and even products for individual consumers.
One important change Intel has made in pursuit of that strategy is the addition of graphics processing units to its product line. Unveiled more than two years ago, those chips could help it stack up better against Nvidia, which specializes in GPUs initially developed for computer gaming but adapted for machine-learning tasks. Intel in 2019 bought Israeli startup Habana Labs, which makes chips designed specifically for training AI models—systems that spit out realistic-sounding sentences, for example—and for generating output from those models.
Another change is in the way Intel knits together its AI products for customers.
“It isn’t even a question of do we have to invest more—we invest quite a bit in AI,” says Sandra Rivera, a longtime Intel executive whom Mr. Gelsinger tapped to head the data-center business and AI strategy last summer. “But we haven’t gotten the leverage of those investments when we have different strategies and different execution priorities” for various products.
Kavitha Prasad, vice president and general manager of data center, AI and cloud execution and strategy, at Intel headquarters.PHOTO: JASON HENRY FOR THE WALL STREET JOURNAL
Since taking her new role, Ms. Rivera has brought in several new executives, including Kavitha Prasad, who came from a machine-learning startup after an earlier stint at Intel. Ms. Prasad, who directly oversees the AI strategy, is leading a shift in focus she says is centered on using AI to reach customers’ business goals, rather than offering a menu of chips and letting customers figure out the rest.
“Intel has all these technologies, but what is bringing it together to make it cohesive from a customer perspective, so that the customers are able to deploy it at a much faster rate, so that they’re able to get to their business outcomes faster?” she says. “It is not about having the solutions, but it’s about meaningfully bringing them together to make it happen.”
Bringing it all together is largely the job of Intel’s software architects, led by Chief Technology Officer Greg Lavender, whom Mr. Gelsinger hired from VMware Inc., where Mr. Gelsinger was previously CEO.
The biggest challenge
Inside a data center at the Intel headquarters.PHOTO: JASON HENRY FOR THE WALL STREET JOURNAL
Success, of course, isn’t a sure thing. Nvidia, already far ahead of Intel and the rest of the competition, is moving quickly with its own chips, announcing a new generation of superfast processors in March. While analysts say Intel’s strategy could help make it a more formidable competitor to Nvidia, its ability to tap the AI market hinges on delivering AI-targeted chips and related software on schedule. Recent history suggests that could be a challenge. Intel has stumbled in chip-manufacturing technology in recent years, leaving it behind South Korea’s Samsung Electronics Co. and Taiwan Semiconductor Manufacturing Co. in the high-stakes race to make chips with the smallest transistors and best performance. Some of its latest CPU chips for servers have been delayed.
Mr. Gelsinger aims to reverse that trajectory by rededicating the company to manufacturing—he’s announced tens of billions of spending on new chip factories over the next several years—and building up a business making chips on contract according to others’ designs. Whether the company can execute on Mr. Gelsinger’s plan to retake the technological lead from its Asian competitors in the next few years is an open question.
“There are a lot of things they haven’t executed on over the last five or six years,” says Matt Bryson, an analyst at Wedbush Securities. “Clearly under Pat Gelsinger Intel is investing more in product development, and if you put more money into development, you should have a better ability to execute, but it comes back to how do you know until you are showing products and starting to see traction?”
Ms. Rivera says Intel is ready to make that leap. “We have the customer relationships, we have the market position, we have the unique differentiation—we just need to execute our strategy,” she says.
robsmark
Regular
358? Is that one of the Ferrari’s you’ll be buying from the BRN profits?
Fullmoonfever
Top 20
Another one where I'd love to see us piggybacked on SiFive & Intel into the Horse Creek next year especially given the other articles and strategy that Intel are looking to execute.
Given we are now part of the IFS & have a pre-existing relationship with SiFive, I actually wouldn't be surprised to maybe see us added to the Intel Pathfinder for Risc-V down the track.
fuse.wikichip.org
Last year Intel announced the development of the Horse Creek Platform, a partnership with SiFive for the development of a new high-performance RISC-V development system as part of both the company’s Intel Foundry Services (IFS) and their effort to catalyze the adoption of RISC-V. The boards were said to be a continuation of SiFive’s own HiFive development boards designed to grow the RISC-V ecosystem and accelerate prototyping.
Early this year Intel also announced the IFS Accelerator ecosystem alliance designed to help accelerate chip prototyping and tape-outs through deep collaboration with various semiconductor partners across EDA, IPs, and design services. IFS Accelerator is a comprehensive suite of tools comprising silicon-verified Intel-process-specific optimized IP portfolio (from std cell library, memory, GP I/O, analog, and I/F IPs). Strategically, A large and vibrant ecosystem will be incredibly important for the success of Intel’s foundry strategy and IFS Accelerator is one of a piece of that. The company initially started Accelerator in September of 2021 to assist the automotive industry with transitioning to more advanced nodes, however, it has since broadened its effort into other segments.
It’s worth noting that SiFive is a member of the IFS Accelerator, saying “SiFive will enable IFS customers to create computing platforms featuring RISC-V, optimized for their market applications. Intel’s broad portfolio of IP compliments the SiFive portfolio of performance-driven processor IP such as the SiFive Intelligence and SiFive Performance families of processor IP.”
Within 18 months, Horse Creek went from an announcement to a fully working A0 stepping chip running Linux. Manufactured on the company’s most advanced Intel 4 process, the die measures just 4 mm by 4 mm and is packaged in a 19 mm x 19 mm BGA package. The chip intends to also demonstrate the interoperability of 3rd-party controllers and IPs along with Intel’s own hard IP PHYs. As such the SoC itself integrates a number of advanced interfaces.
The SoC itself integrates quad-core SiFive P550 RISC-V cores. Each core features private L1 and L2 caches with a shared last-level cache – all operating at 2.2 GHz. At the time of tape out those were the highest-performance RISC-V cores. Note that since SiFive actually announced next-generation P650 cores, surpassing them in performance. The SoC integrates Intel’s own PCIe 5.0 PHY with x8 lanes along with Synopsys PCIe 5 Controller. It also integrates Intel’s DDR5 PHYs supporting 5600 MT/s rates along with Cadence’s memory controller. Other Intel’s own Intel 4 IPs include 2 MiB of shared SRAM (part of their memory compiler), process monitor, caches, Power/Clock/PLLs, electronic fuses, JTAG, and various cell libraries.
Horse Creek boots up Linux, and Intel demonstrated the chip executing a video game (running on the CPUs as there is no GPU) along with various other applications (media player, playback, browser, etc).
No availability date for the new Horse Creek Dev boards has been announced yet.
Given we are now part of the IFS & have a pre-existing relationship with SiFive, I actually wouldn't be surprised to maybe see us added to the Intel Pathfinder for Risc-V down the track.
Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
Intel, SiFive demonstrated high-performance RISC-V Horse Creek development platform on Intel 4 Process.
fuse.wikichip.org
Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
October 7, 2022 David Schor Cadence, Intel, Intel 4, Intel Foundry Services (IFS), Intel Innovation 2022, RISC-V, SiFive, Synopsys
Last year Intel announced the development of the Horse Creek Platform, a partnership with SiFive for the development of a new high-performance RISC-V development system as part of both the company’s Intel Foundry Services (IFS) and their effort to catalyze the adoption of RISC-V. The boards were said to be a continuation of SiFive’s own HiFive development boards designed to grow the RISC-V ecosystem and accelerate prototyping.
Early this year Intel also announced the IFS Accelerator ecosystem alliance designed to help accelerate chip prototyping and tape-outs through deep collaboration with various semiconductor partners across EDA, IPs, and design services. IFS Accelerator is a comprehensive suite of tools comprising silicon-verified Intel-process-specific optimized IP portfolio (from std cell library, memory, GP I/O, analog, and I/F IPs). Strategically, A large and vibrant ecosystem will be incredibly important for the success of Intel’s foundry strategy and IFS Accelerator is one of a piece of that. The company initially started Accelerator in September of 2021 to assist the automotive industry with transitioning to more advanced nodes, however, it has since broadened its effort into other segments.
It’s worth noting that SiFive is a member of the IFS Accelerator, saying “SiFive will enable IFS customers to create computing platforms featuring RISC-V, optimized for their market applications. Intel’s broad portfolio of IP compliments the SiFive portfolio of performance-driven processor IP such as the SiFive Intelligence and SiFive Performance families of processor IP.”
Horse Creek
At the recent Intel Innovation 2022 Developer Conference, the company demoed Horse Creek for the first time in public. Horse Creek is a Raspberry Pi-inspired RISC-V software development board. It’s physically quite a bit larger due to a large number of integrated interfaces. For example, there’s 8 GiB of DDR5. PCIe 5.0 slot. SPI Flash contains the U-Boot, and a myriad of other monitoring and debugging interfaces.
Within 18 months, Horse Creek went from an announcement to a fully working A0 stepping chip running Linux. Manufactured on the company’s most advanced Intel 4 process, the die measures just 4 mm by 4 mm and is packaged in a 19 mm x 19 mm BGA package. The chip intends to also demonstrate the interoperability of 3rd-party controllers and IPs along with Intel’s own hard IP PHYs. As such the SoC itself integrates a number of advanced interfaces.
The SoC itself integrates quad-core SiFive P550 RISC-V cores. Each core features private L1 and L2 caches with a shared last-level cache – all operating at 2.2 GHz. At the time of tape out those were the highest-performance RISC-V cores. Note that since SiFive actually announced next-generation P650 cores, surpassing them in performance. The SoC integrates Intel’s own PCIe 5.0 PHY with x8 lanes along with Synopsys PCIe 5 Controller. It also integrates Intel’s DDR5 PHYs supporting 5600 MT/s rates along with Cadence’s memory controller. Other Intel’s own Intel 4 IPs include 2 MiB of shared SRAM (part of their memory compiler), process monitor, caches, Power/Clock/PLLs, electronic fuses, JTAG, and various cell libraries.
Horse Creek boots up Linux, and Intel demonstrated the chip executing a video game (running on the CPUs as there is no GPU) along with various other applications (media player, playback, browser, etc).
Pathfinder for RISC-V
About a month ago Intel also announced Intel Pathfinder for RISC-V, a rapid prototyping development environment for system integrators. Essentially, it’s a suite of IPs, middleware, open-source, and 3rd party tools along with OS support designed to simplify the exploration of pre-silicon RISC-V-based designs. Intel said it is partnering with commercial and open-source RISC-V IP providers to enable a consistent environment for software development across different RISC-V-based processors. On the commercial side, RISC-V core IPs include those from Andes, Codasip, SiFive, MIPS, and others. Pathfinder includes a number of FPGA platforms for RISC-V chip emulations. The starter edition utilizes the Terasic Developer Kit for Intel Pathfinder while the commercial tools include boards based on the Stratix 10 GX for full chip emulation capabilities.
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No availability date for the new Horse Creek Dev boards has been announced yet.
Fullmoonfever
Top 20
Now back mid year, the following came up.
So, when I read the article I could see the VPU relates to Movidius, who Intel acquired some 6 years ago (as per the article).
However, I'd like to know if any chance now or in the future if Akida has potential to be included as the AI accelerator...... be damn nice if was
videocardz.com
A new commit to Linux VPU driver today confirms that the company has plans to introduce a new processing unit into consumer 14th Gen Core processors, a Versatile Processing Unit.
The VPU driver is included into the Linux Direct Rendering Manager (DRM), the same way their graphics driver is integrated. The VPU appears 6 years after Intel acquired a company called Movidius, which has been developing their own VPUs. It is not entirely clear if and how Intel plans to incorporate Movidius designs into Meteor Lake, it could be a full-blown SoC-like integration or just a copy of architecture bits needed for Meteor Lake. Obviously after so many years, VPU design should be much more complex.
The confirmation on VPU comes from Kerner.org patches, where the following description is added:
Intel VPU for Meteor Lake, Source: kernel.org
Thus, Intel confirms the new VPU has five components, including CPU to VPU integration unit, memory management, RISC controller, network on chip and the most important part, the Neural Compute Subsystem (NCS) doing the actual work. This VPU unit could be considered Intel’s alternative to NVIDIA’s Tensor Cores, a dedicated chip that is heavily focused on AI algorithms.
Intel Meteor Lake is now officially coming next year, eventually it should become available for mobile and desktop platforms packed with new hybrid architecture featuring Redwood Cove and Crestmont CPU cores and Intel’s newest Xe-LPG graphics architecture.
So, when I read the article I could see the VPU relates to Movidius, who Intel acquired some 6 years ago (as per the article).
However, I'd like to know if any chance now or in the future if Akida has potential to be included as the AI accelerator...... be damn nice if was
Intel confirms 14th Gen Meteor Lake has ‘Versatile Processing Unit’ for AI/Deep Learning applications
Published: 30th Jul 2022, 16:52 GMT
Intel confirms 14th Gen Meteor Lake has 'Versatile Processing Unit' for AI/Deep Learning applications - VideoCardz.com
Versatile Processing Unit for deep learning and AI inference Intel is adding VPU to Meteor Lake and newer. A new commit to Linux VPU driver today confirms that the company has plans to introduce a new processing unit into consumer 14th Gen Core processors, a Versatile Processing Unit. The VPU...
Versatile Processing Unit for deep learning and AI inference
Intel is adding VPU to Meteor Lake and newer.A new commit to Linux VPU driver today confirms that the company has plans to introduce a new processing unit into consumer 14th Gen Core processors, a Versatile Processing Unit.
The VPU driver is included into the Linux Direct Rendering Manager (DRM), the same way their graphics driver is integrated. The VPU appears 6 years after Intel acquired a company called Movidius, which has been developing their own VPUs. It is not entirely clear if and how Intel plans to incorporate Movidius designs into Meteor Lake, it could be a full-blown SoC-like integration or just a copy of architecture bits needed for Meteor Lake. Obviously after so many years, VPU design should be much more complex.
The confirmation on VPU comes from Kerner.org patches, where the following description is added:
Intel VPU for Meteor Lake, Source: kernel.org
Thus, Intel confirms the new VPU has five components, including CPU to VPU integration unit, memory management, RISC controller, network on chip and the most important part, the Neural Compute Subsystem (NCS) doing the actual work. This VPU unit could be considered Intel’s alternative to NVIDIA’s Tensor Cores, a dedicated chip that is heavily focused on AI algorithms.
Intel Meteor Lake is now officially coming next year, eventually it should become available for mobile and desktop platforms packed with new hybrid architecture featuring Redwood Cove and Crestmont CPU cores and Intel’s newest Xe-LPG graphics architecture.
| VideoCardz | Alder Lake | Raptor Lake | Meteor Lake |
|---|---|---|---|
| Intel Mainstream CPU Roadmap (RUMORED) | |||
| Desktop Launch Date | Q4 2021 | Q4 2022 | Q4 2023 |
| CPU Node | Intel 7 | Intel 7 | Intel 4 |
| Big Core µArch | Golden Cove | Raptor Cove | Redwood Cove |
| Small Core µArch | Gracemont | Gracemont | Crestmont |
| Graphics µArch | Xe-LP | Xe-LP | Xe-LPG |
| Max CPU Core Count | 16 (8C+8c) | 24 (8C+16c) | TBC |
| Max GPU Core Count | 96 EU | 96 EU | 128-192 EU |
| Desktop Socket | LGA1700 | LGA1700 | LGA 1851 |
| Memory Support | DDR4/DDR5-4800 | DDR4/DDR5-5600 | DDR5 |
| PCIe Gen | PCIe 5.0 | PCIe 5.0 | PCIe 5.0 |
| Intel Core Series | 12th Gen Core | 13th Gen Core | 14th Gen Core |
Hi Fmf,Some slightly dated (well, last few months anyway) articles / news on Intel & SiFive over next couple posts.
Obviously, we know pretty much all the content but still think all worth a skim through at least IMO as can see various connections and where we can fit as well.
I read earlier FF reminding us of VCIX implementation on the X280 & WikiChip Fuse in Sept gives us a better insight.
SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators
SiFive introduces a new high-performance coprocessor interface targeting custom accelerators; scores design wins from Google, NASA.
SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators
September 20, 2022 David Schor AI, AI Hardware Summit, Linley Processor Conference, neural processors, SiFive, Vector Coprocessor Interface Extension (VCIX)
Last year SiFive introduced the Intelligence X280 processor, part of a new category of RISC-V processors for SiFive that aims at assisting AI and machine learning workloads.
Launched under the new family of processors called SiFive Intelligence, the X280 is the first core to cater to AI acceleration. At a high level, the X280 builds on top of their silicon-proven U7-series high-performance (Linux-capable) core. SiFive’s Intelligence X280 is somewhat of a unique processor from SiFive. Targetting ML workloads, its main feature point is both the new RISC-V Vector (RVV) Extension as well as SiFive Intelligence Extensions – the company’s own RISC-V custom-extension for handling ML workloads which includes fixed-point data types from 8-bits to 64-bits as well as 16-64 bit FP and the BFloat16 data type. On the RVV extension side, the X280 supports 512-bit vector register lengths, allowing variable length operations up to 512-bits.
As we mentioned earlier, the X280 builds on SiFive’s successful U7-series core. This is a 64-bit RISC-V core supporting the RV64GCV ISA and extensions. It is an 8-stage dual-issue in-order pipeline. Each core features 32-KiB private L1 data and instruction caches as well as a private L2 cache.
The RISC-V Vector extension is a variable length instruction set. For the X280, the core utilizes a 256b pipeline. In other words, both the vector ALU and load/store architecture data width is 256-bit, doing two operations per 512-bit register data. In addition to the vector extension, SiFive added the “Intelligence Extensions” part of the RISC-V custom extensions ISA support. SiFive didn’t go into any details as to what those extensions entail but did note that compared to the standard RISC-V Vector ISA, the Intelligence Extensions provide a 4-6x performance improvement in int8 (matmul) and bf16 operations.
One of the interesting things that SiFive has done is add that capability for automatic translations of Arm Neon vector code into RISC-V Vectors directly into their compiler. And while it may not produce the most optimal code, it’s a way to quickly and accurately move on Arm Neon code directly to SiFive’s RISC-V code. At last year’s Linley Processor Conference, According to Chris Lattner at Last year’s, SiFive’s then President of Engineering & Product group noted that SiFive itself has been using this feature to port a large number of software packages.
Each of the X280 cores goes into an X280 Core Complex which supports up to a quad-core coherent multi-core cluster configuration. The core cluster can be fully scaled up in a configuration that consists of up to 4 clusters for a total of 16 cores. A system-level L3 cache made of 1 MiB banks (up to 8 MiB) is also supported. The system supports a rich number of ports for I/O and communication with other important sub-system components via the system matrix.
Vector Coprocessor Interface Extension (VCIX)
At the 2022 AI Hardware Summit, Krste Asanovic SiFive Co-Founder and Chief Architect introduced a new Vector Coprocessor Interface Extension (VCIX).
As customer evaluation of the X280 went underway, SiFive say it started noticing new potential usage trends for the core. One such usage is not as the primary ML accelerator, but rather as a snappy side coprocessor/control processor with ML acceleration functionality. In other words, SiFive says it has noticed that companies were considering the X280 as a replacement coprocessor and control processor for their main SoC. Instead of rolling out their own sequencers and other controllers, the X280 proved a good potential replacement.
To assist customers with such applications, SiFive developed the new Vector Coprocessor Interface Extension (VCIX, pronounced “Vee-Six”). VCIX allows for tight coupling between the customer’s SoC/accelerator and the X280. For example, consider a hardware AI startup with a novel way of processing neural networks or one that has designed a very large computational engine. Instead of designing a custom sequencer or control unit, they can simply use the X280 as a drop-in replacement. With VCIX, they are given direct connections to the X280. The interface includes direct access into the vector unit and memory units as well as the instruction stream, allowing an external circuit to utilize the vector pipeline as well as directly access the caches and vector register file.
The capabilities of essentially modifying the X280 core are far beyond anything you can get from someone like Arm. In theory, you could have an accelerator processing its own custom instructions by doing operations on its own side and sending various tasks to the X280 (as a standard RISC-V operation) or directly execute various operations on the X280 vector unit by going directly to that unit. Alternatively, the VCIX interface can work backward by allowing for custom execution engines to be connected to X280 for various custom applications (e.g., FFTs, image signal processing, Matrix operations). That engine would then operate as if they are part of the X280, operating in and out of the X280’s own vector register file. In other words, VCIX essentially allows you to much better customize the X280 core with custom instructions and custom operations on top of a fully working RISC-V core capable of booting full Linux and supporting virtualization.
The VCIX is a high-performance direct-coupling interface to the X280 and its instruction stream. To that end, Asanovic noted that on the X280 with the new VCIX interface, the X280 is capable of sending 1,024 bits over onto the accelerator/external component each cycle and retrieving 512 bits per cycle, every cycle sustained over the VCIX interface.
SiFive says that utilizing their Vector Coprocessor Interface Extension, various accesses and operations from outside can now be done in as low as single-digit cycles or 10s of cycles, instead of 100s of cycles from the normal cluster bus interfaces or memory mapped interfaces. Extremely low-cycle latency is important for developing computational circuits that are highly integrated with the X280.
Google Accelerators
Cliff Young, Google TPU Architect, and MLPerf Co-Founder was also part of the SiFive announcement. As we’ve seen from other Google accelerators, their hardware team always looks to eliminate redundant work by utilizing off-the-shelf solutions if it doesn’t add any real value to design it themselves in-house.
For their own TPU accelerators, beyond the inter-chip interconnect and their highly-refined Matrix Multiply Unit (MXU) which utilizes a systolic array, much of everything else is rather generic and not particularly unique to their chip. Young noted that when they started 9 years ago, they essentially built much of this from scratch, saying “scalar and vector technologies are relatively well-understood. Krste is one of the pioneers in the vector computing areas and has built beautiful machines that way. But should Google duplicate what Krste has already been doing? Should we be reinventing the wheel along with the Matrix Multiply and the interconnect we already have? We’d be much happier if the answer was ‘no’. If we can focus on the stuff that we do great and we can also reuse a general-purpose processor with a general-purpose software stack and integrate that into our future accelerators.” Young added, “the promise of VCIX is to get our accelerators and our general-purpose cores closer together; not far apart across something like a PCIe interface with 1000s of cycles of delay but right next to each other with just a few 100s of cycles through the on-chip path and down to 10s of cycles through direct vector register access.”
The SiFive-Google partnership announcement is one of several public announcements that took place over the past year. Last year SiFive announced that AI chip startup Tenstorrent will also make use of the X280 processor in its next-generation AI training and inference processors. Earlier this month, NASA announced that it has selected SiFive’s X280 cores for its next-generation High-Performance Spaceflight Computing (HPSC) processor. HPSC will utilize an 8-core X280 cluster along with 4 additional SiFive RISC-V cores to “deliver 100x the computational capability of today’s space computers”.
I think this bit is particularly interesting, especially the choice of example of a "hardware start-up with a novel way of processing neural networks".
To assist customers with such applications, SiFive developed the new Vector Coprocessor Interface Extension (VCIX, pronounced “Vee-Six”). VCIX allows for tight coupling between the customer’s SoC/accelerator and the X280. For example, consider a hardware AI startup with a novel way of processing neural networks or one that has designed a very large computational engine. Instead of designing a custom sequencer or control unit, they can simply use the X280 as a drop-in replacement. With VCIX, they are given direct connections to the X280. The interface includes direct access into the vector unit and memory units as well as the instruction stream, allowing an external circuit to utilize the vector pipeline as well as directly access the caches and vector register file.
VCIX is designed to interface the NN to the SiFive X280.
The VCIX is a high-performance direct-coupling interface to the X280 and its instruction stream. To that end, Asanovic noted that on the X280 with the new VCIX interface, the X280 is capable of sending 1,024 bits over onto the accelerator/external component each cycle and retrieving 512 bits per cycle, every cycle sustained over the VCIX interface. [Per cycle @ 300 MHz, for example].
On the other hand, Google seem reluctant to abandon their in-house MXU and TPU:
Cliff Young, Google TPU Architect, and MLPerf Co-Founder was also part of the SiFive announcement. As we’ve seen from other Google accelerators, their hardware team always looks to eliminate redundant work by utilizing off-the-shelf solutions if it doesn’t add any real value to design it themselves in-house.
For their own TPU accelerators, beyond the inter-chip interconnect and their highly-refined Matrix Multiply Unit (MXU) which utilizes a systolic array, much of everything else is rather generic and not particularly unique to their chip. Young noted that when they started 9 years ago, they essentially built much of this from scratch, saying “scalar and vector technologies are relatively well-understood. Krste is one of the pioneers in the vector computing areas and has built beautiful machines that way. But should Google duplicate what Krste has already been doing? Should we be reinventing the wheel along with the Matrix Multiply and the interconnect we already have? We’d be much happier if the answer was ‘no’. If we can focus on the stuff that we do great and we can also reuse a general-purpose processor with a general-purpose software stack and integrate that into our future accelerators.” Young added, “the promise of VCIX is to get our accelerators and our general-purpose cores closer together; not far apart across something like a PCIe interface with 1000s of cycles of delay but right next to each other with just a few 100s of cycles through the on-chip path and down to 10s of cycles through direct vector register access.”
Google are still dabbling with analog SNNs:
WO2020077215A1 TEMPORAL CODING IN LEAKY SPIKING NEURAL NETWORKS
Spiking neural networks that perform temporal encoding for phase-coherent neural computing are provided. In particular, according to an aspect of the present disclosure, a spiking neural network can include one or more spiking neurons that have an activation layer that uses a double exponential function to model a leaky input that an incoming neuron spike provides to a membrane potential of the spiking neuron*. The use of the double exponential function in the neuron's temporal transfer function creates a better defined maximum in time. This allows very clearly defined state transitions between "now" and the "future step" to happen without loss of phase coherence.
May be time for a little morphic resonance.
Footnote: Wonder if Cliff Young still has those gumboots?
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