Hmmm ... it never Rains*, but it's poor.
The original Rain AI analog random nanowire tech, which was also backed by Sam Altman to the tune of $50M of OpenAi's money (and a little of his own) was a complete fizzer, and they are now pursuing a totally different digital approach.
Their random nanowire NN, which so beguiled Altman and the Saudis, confused the brain's complexity with chaos.
US2023023533A1 MEMRISTIVE DEVICE 20200218
View attachment 63711
[0035] A
s indicated in the cross-sectional view of FIG. 3 B, not all nanowires 310 have electrodes located at the same cross-sectional cut. Although electrodes 350 are arranged in a rectangular array, memristive device 300 is not a crossbar array. Instead, nanowires 310 are dispersed on substrate 302 . In some embodiments, nanowires 310 are randomly or pseudo-randomly distributed across substrate 302 . In some embodiments, nanowires 310 have a distribution that is replicated multiple times across substrate. However, the arrangement of nanowires 310 in a particular replication may not be ordered. In other embodiments, the distribution of nanowires 310 may not be random or pseudo-random, but is not an ordered array. For example, two nanowires 310 may cross in multiple locations.
Rain have now moved on to what they call digital-in-memory, but this patent application is for analog-in-memory with DAC/ADC.
WO2024091680A1 COMPUTE IN-MEMORY ARCHITECTURE FOR CONTINUOUS ON-CHIP LEARNING 20221028
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View attachment 63713
[0036] F
IG. 3 depicts an embodiment of a cell in one embodiment of an SRAM CIM module usable for CIM module 230 . Also shown is DAC 202 of compute engine 200 . For clarity, only one SRAM cell 310 is shown. However, multiple SRAM cells 310 may be present. For example, multiple SRAM cells 310 may be arranged in a rectangular array. An SRAM cell 310 may store a weight or a part of the weight. The CIM module shown includes lines 302 , 304 , and 318 , transistors 306 , 308 , 312 , 314 , and 316 , capacitors 320 (Cs) and 322 (CL ). In the embodiment shown in FIG. 3 , DAC 202 converts a digital input voltage to differential voltages, V1 and V2 , with zero reference. These voltages are coupled to each cell within the row. DAC 202 is thus used to temporal code differentially. Lines 302 and 304 carry voltages V1 and V2 , respectively, from DAC 202 . Line 318 is coupled with address decoder 270 (not shown in FIG. 3 ) and used to select cell 310 (and, in the embodiment shown, the entire row including cell 310 ), via transistors 306 and 308.
So what does Rain have up its sleeve? (wet elbow, cold shoulder, goosebumps, ...)
Gordon Wilson Co-founder & Executive Advisor
C
EO at Rain for 6 years, Gordon laid the foundation for Rain to become a leading AI infrastructure company. He is a lifelong storyteller and scientific communicator.
Say no more ...
I think the Biden administration has done the Saudis a favour.
* ... in southern California, ...
It's interesting that Rain AI is no longer referring to neuromorphic technology.
Rain AI Unveils Andes Technology as Its RISC-V Partner
Andes Technology Corporation
Tue, 4 June 2024 at 11:00 am AEST·4-min read
Andes Technology Corporation
San Francisco, CA , June 03, 2024 (GLOBE NEWSWIRE) --
Rain AI Licenses Andes AX45MPV and Taps Andes Custom Computing BU to Accelerate Its Launch of Groundbreaking Compute-In-Memory (CIM) Generative AI Solutions
San Francisco, CA, June 03, 2024 - Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announces that Rain AI, a pioneer in compute-in-memory (CIM) technology, licensed Andes’ AX45MPV RISC-V vector processor. Rain AI designs novel accelerator solutions, and the two companies are collaborating to accelerate Rain AI’s product roadmap.
As the world economy embraces generative AI to deliver unprecedented benefits to consumers and business alike, energy consumption stands as a significant hurdle regardless of the deployment points, be it the cloud, edge, and especially the smallest sensors. CIM represents the most promising solution to lower the energy footprint by as much as 50X. By performing computations directly in the memory bit-cells, CIM can dramatically reduce the energy required for matrix operations commonly found in machine learning.
However, CIM by itself cannot completely address the vast and growing number of machine learning operators. A RISC-V CPU is ideal for efficient programming and future-proofing of an CIM-based NPU. The RISC-V architecture allows users to add custom instructions to encapsulate the CIM computing blocks, easing software development efforts. Andes automates this instruction customization process with its automated COPILOT compiler.
Mr. Frankwell Lin, Chairman and CEO of Andes, says, "Andes is honored and excited to have Rain AI as its licensee and partner. As the first RISC-V vector processor provider, we see CIM as an inevitable necessity to enable generative AI applications and therefore have focused on CIM customers.
To our knowledge, Rain AI has designed one of the most energy efficient matrix multiplication units using digital CIM technology, so we look forward to Rain AI unveiling its breakthrough solutions."
Mr. William Passo, CEO of Rain AI, echoed this sentiment, stating, "It is rare to see a vendor who shares the same market and technology vision as us, has best-in-class RISC-V solutions for our technology needs, and can commit resources to help us accelerate our roadmap to significantly reduce the energy required for AI. Running the most advanced models in any form factor is the future of AI, and we are now one step closer with Andes."
Indeed, Rain AI further taps into Andes’ Custom Computing Business Unit (CCBU) to help accelerate the integration of Andes AX45MPV and the ACE/COPILOT instruction customization with on-site and remote consulting services. Andes’ CCBU is a small team of experts tasked to perform complex customizations and integrations for a few promising cutting-edge licensees.
Both companies can share that AX45MPV and Andes’ unique RISC-V instruction customization solution, ACE/COPILOT both play pivotal roles to complement Rain AI’s groundbreaking CIM hardware, compiler, and runtime software to deliver scalable ML solutions for a variety of deployment points.
Rain AI will unveil its accelerator solution in early 2025.
About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (
TWSE: 6533;
SIN: US03420C2089;
ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit
https://www.andestech.com. Follow Andes on
LinkedIn,
Twitter,
Bilibili and
YouTube! !
About Rain AI
Rain AI’s mission is to enable advanced and abundant AI everywhere by building the world’s most efficient AI hardware. It creates flexible solutions for generative AI inference and training utilizing novel compute-in-memory CIM technology, RISC-V processing cores, advanced packaging techniques, and optimized ML algorithms. By co-designing hardware with leading AI models, Rain AI sets new standards in AI efficiency and performance.
Rain AI investors include Sam Altman, Dan Gross, and Y Combinator. For further information, visit
http://www.rain.ai.
CONTACT: Jonah McLeod +1 (510) 449-8634
Jonahm@andestch.com
San Francisco, CA , June 03, 2024 (GLOBE NEWSWIRE) -- Rain AI Licenses Andes AX45MPV and Taps Andes Custom Computing BU to Accelerate Its Launch of Groundbreaking Compute-In-Memory (CIM) Generative AI Solutions San Francisco, CA, June 03, 2024 - Andes Technology, a leading supplier of...
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