Back in November 2023 Infineon unveiled its new PSoC Edge product. It describes how the microcontroller is integrated and says in this article that "the Cortex-M33
is paired with Infineon’s proprietary NNLite hardware accelerator, known for its ultra-low power consumption, intended to expedite neural network processing in ML applications further.
Try as I might I have not been able to find anything that further describes what this NNLite neural network accelerator is.
Very mysterious indeed...
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n Infineon, a leading semiconductor manufacturer, has recently unveiled a new family of microcontrollers that combines cutting-edge technology to cater to the growing demands of the Internet of Things (IoT) and industrial sectors. This family of microcontrollers integrates an Arm Cortex-M55...
hardwarebee.com
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neural network accelerator
This an Infineon analog NN patent appln from2019. It is adapted to work with digital circuits via ADC/DACs
US2022284951A1 SILICON-OXIDE-NITRIDE-OXIDE-SILICON BASED MULTI-LEVEL NON-VOLATILE MEMORY DEVICE AND METHODS OF OPERATION THEREOF 20191126
A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including
NVM cells arranged in rows and columns, in which NVM transistors of
the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels,
digital-to-analog (DAC) function that receives and converts digital signals from external devices,
column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and
analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.
[0052] In one embodiment, the plurality of the semiconductor devices may be configured to function as
artificial neurons in a deep neural network (DNN) performing neuromorphic computing in an artificial intelligence (AI) application.
[00118] FIGS. 14 and 15 are representative block diagrams respectively illustrating
a Von-Neumann architecture of a multiply accumulate (MAC) system and an artificial neuron according to one embodiment of the present disclosure. Artificial Intelligence (AI) may be defined as the ability of a machine to perform cognitive functions executed by a human brain, such has reasoning, perception, and learning. Machine learning may use algorithms to find patterns in data and use a model that recognizes those patterns to make predictions on any new data or patterns.
At the heart of AI applications or machine learning, there is the MAC or dot product operation, wherein it may take two numbers (input values and weight values), multiplies them together, and add the results to an accumulator.
The artificial neuron 1504 in FIG. 15 may be a portion of a deep neural network (DNN) that features an example of a MAC operation. DNN mimics the functionalities of a human brain by implementing massively parallel computing (neuromorphic computing) architecture connecting low power computing elements (neurons) and adaptive memory elements (synapses). One reason for the rapid growth in machine learning is the availability of graphic processing units (GPUs). In a MAC application, such as system 1402 , GPUs may perform necessary computations much faster than a general purpose CPU.
One of the downsides of using GPUs for MAC operations is that GPUs tend to utilize floating-point arithmetic, which may be well beyond the needs of a relatively simple machine learning algorithms, like the MAC operations. Besides, AI applications, especially those run at the edge, may require MAC to run at high power efficiency to reduce power need and heat generation. The existing all digital Von-Nuemann architecture-based systems, like MAC system 1502 , may also create major bottleneck issues between GPUs that do the computation and memory that only stores data (weight values, input values, output values, etc.) due to the frequent accesses of the memory. Therefore, there are needs to consider using low power consumption memory elements that may be configured to perform as an inference device, as well as a data storage device.
[0119] FIG. 16 is a representative block diagram illustrating a neural network accelerator system in accordance with one embodiment of the present disclosure.
"
One of the downsides of using GPUs for MAC operations is that GPUs tend to utilize floating-point arithmetic, which may be well beyond the needs of a relatively simple machine learning algorithms" - this may explain the "lite" appellation.
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. He also thinks that if there is manipulation, he(they) are not doing a good job because each time they dispute a dot join another poster on here will highlight the facts again as to why they dot joined and it is likely that any new members to the forum would not have seen those facts previously. He thinks most are not manipulator's and are just lonely and hoping for any response, or angry because they timed their buy in badly and are just venting. sad really.
