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A recent patent publication from TCS.
@Diogenese is this TSC patent using Brainchip's Akida?
Abstract
State of art techniques rely of FPGA based approaches when power efficiency is of concern. However, compared to SNN on Neuromorphic hardware, ANN on FPGA requires higher power and longer design cycles to deploy neural network on hardware accelerators. Embodiments of the present disclosure provide a method and system for energy efficient hierarchical multi-stage SNN architecture for classification and segmentation of high-resolution images. Patch-to-patch-class classification approach is used, where the image is divided into smaller patches, and classified at first stage into multiple labels based on percentage coverage of a parameter of interest, for example, cloud coverage in satellite images. The image portion corresponding to the partially covered patches is divided into further smaller size patches, classified by a binary classifier at second level of classification. Labels across multiple SNN classifier levels are aggregated to identify segmentation map of the input image in accordance with the coverage parameter of interest.
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A recent patent publication from TCS.
@Diogenese is this TSC patent using Brainchip's Akida?
Abstract
State of art techniques rely of FPGA based approaches when power efficiency is of concern. However, compared to SNN on Neuromorphic hardware, ANN on FPGA requires higher power and longer design cycles to deploy neural network on hardware accelerators. Embodiments of the present disclosure provide a method and system for energy efficient hierarchical multi-stage SNN architecture for classification and segmentation of high-resolution images. Patch-to-patch-class classification approach is used, where the image is divided into smaller patches, and classified at first stage into multiple labels based on percentage coverage of a parameter of interest, for example, cloud coverage in satellite images. The image portion corresponding to the partially covered patches is divided into further smaller size patches, classified by a binary classifier at second level of classification. Labels across multiple SNN classifier levels are aggregated to identify segmentation map of the input image in accordance with the coverage parameter of interest.
US20230154154A1 - Energy efficient hierarchical snn architecture for classification and segmentation of high-resolution images - Google Patents
State of art techniques rely of FPGA based approaches when power efficiency is of concern. However, compared to SNN on Neuromorphic hardware, ANN on FPGA requires higher power and longer design cycles to deploy neural network on hardware accelerators. Embodiments of the present disclosure...
patents.google.com
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