BRN Discussion Ongoing

[Fullmoonfever]

Could this be where Renesas first introduce our IP?​

First samples for RISC-V and ARM embedded modules​

New Products | June 2, 2022
Aries Embedded has received first samples of its latest RISC-V and ARM-based embedded system-in-package boards ready to show for the first time later this month. The MSRZG2UL and MSRZFive are based on the single-core microprocessors RZ/G2UL and RZ/Five microcontrollers from Renesas Electronics. The RZ/G2UL microprocessor includes a Cortex-A55 (1.0 GHz) CPU and…
By Nick Flaherty

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Aries Embedded has received first samples of its latest RISC-V and ARM-based embedded system-in-package boards ready to show for the first time later this month.

The MSRZG2UL and MSRZFive are based on the single-core microprocessors RZ/G2UL and RZ/Five microcontrollers from Renesas Electronics.
The RZ/G2UL microprocessor includes a Cortex-A55 (1.0 GHz) CPU and a CortexM33 coprocessor, while the RZ/Five has a RISC-V CPU core (AX45MP Single) running at 1.0 GHz.
“The microcontrollers have numerous interfaces and are therefore the ideal basis for our new system-on-modules for industrial gateway devices,” said Andreas Widder, Managing Director of Aries Embedded. “The new MSRZ SiPs are used in industrial controllers, IoT devices and other embedded systems with simple GUI functions.”

Related RISC-V articles​

• ARM battles RISC-V at Renesas
• SoM is built around multi-core RISC-V SoC FPGA
• RISC-V reference design for Intel FPGA module

The smallest “S” size MSRZ SiP SoMs measure 30 by 30 mm and conform to the SGET OSM standard and offer an LCD controller. They support 512 MB to 4 GB of DDR4 RAM and 4 GB of eMMC NAND flash. The numerous interfaces include camera input (MIPI-CSI), display output (Parallerl-IF), USB2.0 2ch, SD 2ch, CAN (CAN-FD) and Gigabit Ethernet 2-Channel. The temperature range is -25 °C to +85 °C and -40 °C to +85 °C for industrial environments.
The MSRZG2UL and MSRZFive SiPs will be available as samples from the third quarter of 2022. Series production will start in the fourth quarter of 2022.
ARIES Embedded will present the system-in-packages for the first time at Embedded World from 22nd June in Nuremberg.
www.aries-embedded.com/

JT first raised Aries back in June & recent article sheds a little more on them.

Noticed some known names we discuss being Renesas, STMicro, Xilinx, Microchip linked / used by Aries.

Have wondered myself previously about the V2L from Renesas.

BRN Discussion Ongoing

Howdy Team, Have I missed anything? I suppose I better put my rubber gloves on and get back to work finding some more wet spots!

thestockexchange.com.au

Smart embedded vision – off-the-shelf and custom-made

ARIES Embedded, specialist in embedded services and products, is further expanding its portfolio around smart embedded vision.

www.electronicspecifier.com

Smart embedded vision – off-the-shelf and custom-made​

9th September 2022
ARIES Embedded
Sam Holland

ARIES Embedded, specialist in embedded services and products, is further expanding its portfolio around smart embedded vision.
Explained Andreas Widder, Managing Director of ARIES Embedded: "Off-the-shelf products often cannot meet the various complex requirements of embedded vision projects. Precisely tailored to our customers' projects, we select the optimal microprocessors and FPGAs from leading manufacturers for our boards and services in each case."

For simple vision applications that can also use artificial intelligence, ARIES Embedded provides comparatively inexpensive products with the system-in-packages (SiP) MSRZG2UL and MSMP1. The FPGA-based system-on-modules (SoM) from the three major manufacturers Intel, Microchip, and Xilinx are more flexible and meet higher demands. The areas of application range from industrial image processing, agriculture, robotics, automated driving, UAV (unmanned aerial vehicle), and drones to medical technology.

Versatile FPGAs for challenging smart vision​

Embedded vision modules based on FPGAs can use almost any sensor in terms of light spectrum, resolution, frame rate, and electrical interface. On the IP side, it is possible to map the complete image path from the data source (image sensor, camera) to the data sink (monitor, storage medium). For this, ARIES Embedded uses suitable compression methods such as MJPEG compression and H.264/H.265, which are available as fixed IP blocks in the FPGA or integrates corresponding soft cores.

IP development also covers image processing, including white balance, brightness, sharpness etc. as well as further image processing. In addition to the standard products, ARIES Embedded designs the appropriate hardware that mechanically corresponds exactly to the customer's specifications.

The M100PF and M100PFS SoMs rely on Microchip's PolarFire (SoC) FPGA architecture, with the M100PFS supporting four high-performance 64-bit RISC-V cores. The C-Vision kit is based on the proven MCVEVP FPGA development board with Intel's Cyclone V SoC FPGA and includes two Basler dart cameras, an adapter card, and an AI accelerator card. The UAV and robotics platform URP, developed by TOPIC Embedded Systems and in the portfolio of ARIES Embedded, offers a highly integrated single board design based on the Xilinx Zynq UltraScale+ MPSoC.

Simple vision applications based on CPUs​

For applications with lower vision functionality requirements, ARIES Embedded offers modules based on Renesas’ RZG2UL/RZFive and STMicroelectronics’ STM32MP1. "The microprocessors are much less expensive and more convenient to use than FPGAs," added Andreas Widder. "Renesas in particular offers a solution with the RZ/V2L architecture that supports artificial intelligence applications." In addition to the standard modules, ARIES Embedded develops the complete hardware and basic software.

The versatile, OSM (open standard module)-compatible MSRZG2UL and MSRZFive system-in-packages are based on Renesas' RZ/G2UL and RZ/Five single-core microprocessors. The RZ/G2UL microprocessor contains a Cortex®-A55 (1.0 GHz) CPU and a CortexM33 coprocessor, while the RZ/Five has a RISC-V CPU core (AX45MP Single) running at 1.0 GHz. ARIES Embedded's MSMP1 SiP integrates STMicroelectronics' STM32MP1 CPU family with high-performance single or dual-arm CortexA7 cores (up to 800 MHz) combined with a CortexM4 core (up to 209 MHz).

ARIES Embedded will present its wide range of embedded systems at Vision 2022, the world's leading trade show for machine vision, from October 4 to 6, 2022 in Stuttgart, Germany, at stand C08 in hall 8.

 

[equanimous]

SNUFA 2022

Spiking Neural networks as Universal Function Approximators

snufa.net

SNUFA 2022​

Spiking Neural networks as Universal Function Approximators​

SNUFA 2022​

Brief summary. This online workshop brings together researchers in the fields of computational neuroscience, machine learning, and neuromorphic engineering to present their work and discuss ways of translating these findings into a better understanding of neural circuits. Topics include artificial and biologically plausible learning algorithms and the dissection of trained spiking circuits toward understanding neural processing. We have a manageable number of talks with ample time for discussions.

Executive committee. Katie Schuman, Timothée Masquelier, Dan Goodman, and Friedemann Zenke.

Quick links. Register (free) Submit an abstract (before 28 Sept 2022)

Invited speakers​

• Charlotte Frenkel, TU Delft
• Priya Panda, Yale
• Yiota Poirazi, Institute of Molecular Biology and Biotechnology (IMBB)
• Yonghong Tian, Peking University

Key information​

Workshop. 9-10 November 2022, European afternoons.

Registration. Free but mandatory. Click here to register.

Abstract submission deadline. 28 September 2022. Click here to submit.

Final decisions. 12 October 2022.

Format​

• Two half days
• 4 invited talks
• 8 contributed talks
• Poster session
• Panel debate (topic to be decided, let us know if you have a good idea)

Abstract submissions​

Click here to submit. Abstracts will be made publicly available at the end of the abstract submissions deadline for blinded public comments and ratings. We will select the most highly rated abstracts for contributed talks, subject to maintaining a balance between the different fields of, broadly speaking, neuroscience, computer science and neuromorphic engineering. Abstracts not selected for a talk will be presented as posters, and there is an option to submit an abstract directly for a poster and not a talk if you prefer.

Energy, Power, Control, and Networks (EPCN)

beta.nsf.gov

• Science Topics
• News & Multimedia
• About NSF
• Funding & Awards

• Overview
• Fund Your Research
• NSF-Funded Projects
• Research Directorates & Offices

Energy, Power, Control, and Networks (EPCN)

1. Back to search results

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Important Information for Proposers
A revised version of the NSF Proposal & Award Policies & Procedures Guide (PAPPG) (NSF 22-1), is effective for proposals submitted, or due, on or after October 4, 2021. Please be advised that, depending on the specified due date, the guidelines contained in NSF 22-1 may apply to proposals submitted in response to this funding opportunity.


Supports research in modeling, optimization, learning, adaptation and control of networked multi-agent systems; higher-level decision making; and dynamic resource allocation and risk management.

Synopsis​

The Energy, Power, Control, and Networks (EPCN) Program supports innovative research in modeling, optimization, learning, adaptation, and control of networked multi-agent systems, higher-level decision making, and dynamic resource allocation, as well as risk management in the presence of uncertainty, sub-system failures, and stochastic disturbances. EPCN also invests in novel machine learning algorithms and analysis, adaptive dynamic programming, brain-like networked architectures performing real-time learning, and neuromorphic engineering. EPCN’s goal is to encourage research on emerging technologies and applications including energy, transportation, robotics, and biomedical devices & systems. EPCN also emphasizes electric power systems, including generation, transmission, storage, and integration of renewable energy sources into the grid; power electronics and drives; battery management systems; hybrid and electric vehicles; and understanding of the interplay of power systems with associated regulatory & economic structures and with consumer behavior.
Areas managed by Program Directors (please contact Program Directors listed in the EPCN staff directory for areas of interest):
Control Systems

• Distributed Control and Optimization
• Networked Multi-Agent Systems
• Stochastic, Hybrid, Nonlinear Systems
• Dynamic Data-Enabled Learning, Decision and Control
• Cyber-Physical Control Systems
• Applications (Biomedical, Transportation, Robotics)

Energy and Power Systems

• Solar, Wind, and Storage Devices Integration with the Grid
• Monitoring, Protection and Resilient Operation of Grid
• Power Grid Cybersecurity
• Market design, Consumer Behavior, Regulatory Policy
• Microgrids
• Energy Efficient Buildings and Communities

Power Electronics Systems

• Advanced Power Electronics and Electric Machines
• Electric and Hybrid Electric Vehicles
• Energy Harvesting, Storage Devices and Systems
• Innovative Grid-tied Power Electronic Converters

Learning and Adaptive Systems

• Neural Networks
• Neuromorphic Engineering Systems
• Data analytics and Intelligent Systems
• Machine Learning Algorithms, Analysis and Applications

Collapse

Program contacts​

Eyad Abed	eabed@nsf.gov	(703)292-8339	ENG/ECCS
Aranya Chakrabortty	achakrab@nsf.gov	(703) 292-8113	ENG/ECCS
Mahesh Krishnamurthy	mkrishna@nsf.gov	(703)292-8339	ENG/ECCS
Donald Wunsch	dwunsch@nsf.gov	(703) 292-7102	ENG/ECCS

Awards made through this program​

Browse projects funded by this programMap of recent awards made through this program

Organization(s)​

• Directorate for Engineering (ENG)
• Division of Electrical, Communications and Cyber Systems (ENG/ECCS)

Upcoming due dates​

Full proposal accepted anytime

For additional information regarding the removal of deadlines for this program, please refer to the Dear Colleague Letter [https://www.nsf.gov/pubs/2018/nsf18082/nsf18082.jsp] and Frequently Asked Questions [https://www.nsf.gov/pubs/2018/nsf18083/nsf18083.jsp].
Proposals submitted to other program announcements and solicitations, including the Faculty Early Career Development Program (CAREER), must meet their respective deadlines; please refer to the deadline dates specified in the appropriate announcement or solicitation. Proposals for EArly-concept Grants for Exploratory Research (EAGER) or Rapid Response Research (RAPID) can be submitted at any time but Principal Investigators must contact the cognizant program director prior to submission. Proposals for supplements or workshops can be submitted at any time, and PIs are encouraged to contact the cognizant PD prior to submission.

Program guidelines​

Apply to PD 18-7607 as follows:
Full proposals submitted via FastLane or Research.gov: NSF Proposal & Award Policies & Procedures Guide proposal preparation guidelines apply.
Full proposals submitted via Grants.gov: NSF Grants.gov Application Guide: A Guide for the Preparation and Submission of NSF Applications via Grants.gov guidelines apply.
Alert: Many NSF programs are only accepting proposals in Research.gov or Grants.gov. FastLane may no longer be a submission option. For more information, please visit Program Descriptions that Require Proposal Preparation and Submission in Research.gov or Grants.gov.

Share​

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Published:

 

[Diogenese]

SNUFA 2022

Spiking Neural networks as Universal Function Approximators

snufa.net

SNUFA 2022​

Spiking Neural networks as Universal Function Approximators​

SNUFA 2022​

Brief summary. This online workshop brings together researchers in the fields of computational neuroscience, machine learning, and neuromorphic engineering to present their work and discuss ways of translating these findings into a better understanding of neural circuits. Topics include artificial and biologically plausible learning algorithms and the dissection of trained spiking circuits toward understanding neural processing. We have a manageable number of talks with ample time for discussions.

Executive committee. Katie Schuman, Timothée Masquelier, Dan Goodman, and Friedemann Zenke.

Quick links. Register (free) Submit an abstract (before 28 Sept 2022)

Invited speakers​

• Charlotte Frenkel, TU Delft
• Priya Panda, Yale
• Yiota Poirazi, Institute of Molecular Biology and Biotechnology (IMBB)
• Yonghong Tian, Peking University

Key information​

Workshop. 9-10 November 2022, European afternoons.

Registration. Free but mandatory. Click here to register.

Abstract submission deadline. 28 September 2022. Click here to submit.

Final decisions. 12 October 2022.

Format​

• Two half days
• 4 invited talks
• 8 contributed talks
• Poster session
• Panel debate (topic to be decided, let us know if you have a good idea)

Abstract submissions​

Click here to submit. Abstracts will be made publicly available at the end of the abstract submissions deadline for blinded public comments and ratings. We will select the most highly rated abstracts for contributed talks, subject to maintaining a balance between the different fields of, broadly speaking, neuroscience, computer science and neuromorphic engineering. Abstracts not selected for a talk will be presented as posters, and there is an option to submit an abstract directly for a poster and not a talk if you prefer.

I have seen a couple of papers in which Timothee is a co-author, relating to MemRistor NN.

 

[Izzzzzzzzzzy]

Mercedes is helping Rivian with their automotive.
Today I met a guy who worked with Rivian automotive. I asked him if he had heard of Brainchip AKIDA.
He said yes Mercedes is helping us with that.
He works in Amsterdam for Rivian.

Instantly came after reading this

 

[equanimous]

I have seen a couple of papers in which Timothee is a co-author, relating to MemRistor NN.

Energy, Power, Control, and Networks (EPCN)

beta.nsf.gov

• Science Topics
• News & Multimedia
• About NSF
• Funding & Awards

• Overview
• Fund Your Research
• NSF-Funded Projects
• Research Directorates & Offices

Energy, Power, Control, and Networks (EPCN)

1. Back to search results

Printthis Page

Important Information for Proposers
A revised version of the NSF Proposal & Award Policies & Procedures Guide (PAPPG) (NSF 22-1), is effective for proposals submitted, or due, on or after October 4, 2021. Please be advised that, depending on the specified due date, the guidelines contained in NSF 22-1 may apply to proposals submitted in response to this funding opportunity.


Supports research in modeling, optimization, learning, adaptation and control of networked multi-agent systems; higher-level decision making; and dynamic resource allocation and risk management.

Synopsis​

The Energy, Power, Control, and Networks (EPCN) Program supports innovative research in modeling, optimization, learning, adaptation, and control of networked multi-agent systems, higher-level decision making, and dynamic resource allocation, as well as risk management in the presence of uncertainty, sub-system failures, and stochastic disturbances. EPCN also invests in novel machine learning algorithms and analysis, adaptive dynamic programming, brain-like networked architectures performing real-time learning, and neuromorphic engineering. EPCN’s goal is to encourage research on emerging technologies and applications including energy, transportation, robotics, and biomedical devices & systems. EPCN also emphasizes electric power systems, including generation, transmission, storage, and integration of renewable energy sources into the grid; power electronics and drives; battery management systems; hybrid and electric vehicles; and understanding of the interplay of power systems with associated regulatory & economic structures and with consumer behavior.
Areas managed by Program Directors (please contact Program Directors listed in the EPCN staff directory for areas of interest):
Control Systems

• Distributed Control and Optimization
• Networked Multi-Agent Systems
• Stochastic, Hybrid, Nonlinear Systems
• Dynamic Data-Enabled Learning, Decision and Control
• Cyber-Physical Control Systems
• Applications (Biomedical, Transportation, Robotics)

Energy and Power Systems

• Solar, Wind, and Storage Devices Integration with the Grid
• Monitoring, Protection and Resilient Operation of Grid
• Power Grid Cybersecurity
• Market design, Consumer Behavior, Regulatory Policy
• Microgrids
• Energy Efficient Buildings and Communities

Power Electronics Systems

• Advanced Power Electronics and Electric Machines
• Electric and Hybrid Electric Vehicles
• Energy Harvesting, Storage Devices and Systems
• Innovative Grid-tied Power Electronic Converters

Learning and Adaptive Systems

• Neural Networks
• Neuromorphic Engineering Systems
• Data analytics and Intelligent Systems
• Machine Learning Algorithms, Analysis and Applications

Collapse

Program contacts​

Eyad Abed	eabed@nsf.gov	(703)292-8339	ENG/ECCS
Aranya Chakrabortty	achakrab@nsf.gov	(703) 292-8113	ENG/ECCS
Mahesh Krishnamurthy	mkrishna@nsf.gov	(703)292-8339	ENG/ECCS
Donald Wunsch	dwunsch@nsf.gov	(703) 292-7102	ENG/ECCS

Awards made through this program​

Browse projects funded by this programMap of recent awards made through this program

Organization(s)​

• Directorate for Engineering (ENG)
• Division of Electrical, Communications and Cyber Systems (ENG/ECCS)

Upcoming due dates​

Full proposal accepted anytime

For additional information regarding the removal of deadlines for this program, please refer to the Dear Colleague Letter [https://www.nsf.gov/pubs/2018/nsf18082/nsf18082.jsp] and Frequently Asked Questions [https://www.nsf.gov/pubs/2018/nsf18083/nsf18083.jsp].
Proposals submitted to other program announcements and solicitations, including the Faculty Early Career Development Program (CAREER), must meet their respective deadlines; please refer to the deadline dates specified in the appropriate announcement or solicitation. Proposals for EArly-concept Grants for Exploratory Research (EAGER) or Rapid Response Research (RAPID) can be submitted at any time but Principal Investigators must contact the cognizant program director prior to submission. Proposals for supplements or workshops can be submitted at any time, and PIs are encouraged to contact the cognizant PD prior to submission.

Program guidelines​

Apply to PD 18-7607 as follows:
Full proposals submitted via FastLane or Research.gov: NSF Proposal & Award Policies & Procedures Guide proposal preparation guidelines apply.
Full proposals submitted via Grants.gov: NSF Grants.gov Application Guide: A Guide for the Preparation and Submission of NSF Applications via Grants.gov guidelines apply.
Alert: Many NSF programs are only accepting proposals in Research.gov or Grants.gov. FastLane may no longer be a submission option. For more information, please visit Program Descriptions that Require Proposal Preparation and Submission in Research.gov or Grants.gov.

Share​

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Published:

CCF: Foundations of Emerging Technologies (FET)

beta.nsf.gov

Computer and Information Science and Engineering : Core Programs
CCF: Foundations of Emerging Technologies (FET)

View guidelines​

22-631

1. Back to search results

Printthis Page

Important Information for Proposers
A revised version of the NSF Proposal & Award Policies & Procedures Guide (PAPPG) (NSF 22-1), is effective for proposals submitted, or due, on or after October 4, 2021. Please be advised that, depending on the specified due date, the guidelines contained in NSF 22-1 may apply to proposals submitted in response to this funding opportunity.


Supports research at the intersection of computing and biological systems; nanoscale science and engineering; and quantum information science and other technologies supporting novel computing and communication models.

Synopsis​

The Foundations of Emerging Technologies (FET) program supports overarching fundamental research in disruptive technologies and models in computing and communication. Current exemplars include but are not limited to biological computation, nanoscale science and engineering, quantum information science and engineering, neuromorphic computing, and other disruptive technologies and computing models.
The goal of the FET program is to germinate and foster radical innovations in computing and communication modalities, in topics spanning the various fields of research traditionally funded by the core CCF programs, which may include the theory, algorithms, software, hardware, and architecture of computing and communication systems, as applied to these innovations. Interdisciplinary collaboration between computer and information scientists as well as those in various other fields such as biology, chemistry, engineering, mathematics, and physics are highly encouraged to promote groundbreaking inventions and paradigm-shifting solutions for hardware and software platforms in computing and communication.
The FET program seeks transformative research projects in any disruptive area aligned with the goals of the program as identified above. The following research areas are called out specifically at this time.
The Biological Systems Science and Engineering program element explores opportunities at the intersection of biology and computer science, with a specific focus on activities that advance understanding of computing and communication processes in biological systems to recreate or use them as models for, or demonstrations of, innovative computing and communication systems. Topics of interest include but are not limited to: understanding the complexity of biological systems via algorithmic, mathematical, and/or stochastic modeling techniques for simulation and analysis of biological systems and biochemical networks at multiple scales; and harnessing the computing power of biomolecules in designing systems that complement and extend the capability of silicon-based computing systems. Research in the Synthetic Biology area, with a focus on constructing/redesigning novel hybrid programmable biological systems capable of computing and information processing, is also in scope for the program. Some examples for research topics include but are not limited to issues in resource allocation in a designed synthetic cell/system, design tools for engineering biological systems, and advanced biomolecule-based data-storage devices.
The Quantum Information Science program element explores new research ideas in quantum computing, quantum communication, and other quantum-based approaches for processing, exchanging, and using information. Topics of interest include but are not limited to the design, development, and rigorous analysis of a broad and general collection of quantum; study of quantum programming languages, quantum architectures, and quantum circuits; simulation of quantum algorithms and systems; design of quantum computers and systems; benchmarking, programming, optimizing, and testing quantum computer systems experimentally; development of both theoretical and practical approaches to fault tolerance; demonstration of scalable quantum computations, thereby paving the road to quantum supremacy; and explorations into quantum information in communication and networking.
Additionally, the FET program promotes research that demonstrates how computational and engineering principles can be synergistically advanced to mimic brain-like problem solving with novel neural and cognitive architectures. In particular, the program encourages research on neuromorphic computing with hardware-friendly learning mechanisms such as spike-timing dependent plasticity (STDP), reinforcement and Q-learning. Proposals on brain-computer interfaces will be considered by the FET program if they aim at solving problems in fundamentally new ways.
The FET program also solicits research on emerging topics of quantum-like, but non-qubit-based, computing paradigms. Such methodologies may typically address hard computational problems in integer factorization, hardware methods to solving NP-hard problems, machine learning, and so on. Examples of such efforts may include but are not limited to computing using probabilistic bits and single-flux quantum logic circuits.
The FET program promotes innovative research on multiscale modeling of computing and communications systems based on future emerging technologies as well.

 

[Fullmoonfever]

@Diogenese

Didn't know if this site is something you would find interesting to trawl through at your leisure?

Found an AMD / Xilinx Documentation Portal while trawling Google and most is above my head and a lot refers to CNN but haven't dug through to see if any CNN - SNN conversions or other links for us?

AMD Technical Information Portal

docs.xilinx.com

Found

 

[equanimous]

@Diogenese

Would love to hear your thoughts on this.

https://arxiv.org/pdf/2209.11891.pdf

[Submitted on 24 Sep 2022]

Neuromorphic Integrated Sensing and Communications​

Jiechen Chen, Nicolas Skatchkovsky, Osvaldo Simeone

Neuromorphic computing is an emerging technology that support event-driven data processing for applications requiring efficient online inference and/or control. Recent work has introduced the concept of neuromorphic communications, whereby neuromorphic computing is integrated with impulse radio (IR) transmission to implement low-energy and low-latency remote inference in wireless IoT networks. In this paper, we introduce neuromorphic integrated sensing and communications (N-ISAC), a novel solution that enables efficient online data decoding and radar sensing. N-ISAC leverages a common IR waveform for the dual purpose of conveying digital information and of detecting the presence or absence of a radar target. A spiking neural network (SNN) is deployed at the receiver to decode digital data and detect the radar target using directly the received signal. The SNN operation is optimized by balancing performance metric for data communications and radar sensing, highlighting synergies and trade-offs between the two applications.

V. CONCLUSIONS In this paper, we have proposed a novel ISAC solution that leverages the synergy of neuromorphic computing and IR transmission for both data transmission and radar detection. Data are encoded on an IR waveform that is used for the dual purpose of data decoding and target sensing. A single- or dualSNN receiver architecture is considered to estimate data and the presence/absence of a target. Experiments have demonstrated the advantage of the proposed neuromorphic ISAC (NISAC) over conventional separate sensing and communications in terms of normalized test throughput and radar test detection error.

 

[Stable Genius]

Akida Foundations

Immerse yourself in the powerful new world of the akida™ neuromorphic processor IP! The future of AI is NOW!

brainchip.com

View attachment 17468

SiFive Intelligence X280 64-bit RISC-V processor integrates AI extensions - CNX Software

SiFive Intelligence X280 is multi-core, Linux capable RISC-V processor adding SiFive Intelligence Extensions optimized for AI/ML edge compute

www.cnx-software.com

View attachment 17469

SiFive Intelligence Extensions for ML workloads – BF16/FP16/FP32/FP64, int8 to 64 fixed-point data types

My take.
The Intelligence Extensions are embedded in the X280 chip and can run by itself, performing inference tasks at the edge, where it can also act as an apps processor and inference engine for smaller workloads.

For Akida IP to be employed, you need a custom chip where I'm guessing the Akida Neuron fabric integrates through this AXI4 bus interconnect.

Hi @krugerrands,

All the discussions been about the X280 but what about the X280A?

The “A” stands for something?

 

[Bravo]

Hi All,

Speaking of 4-bit quantization, I found another reference to it in a different Qualcomm blog to the one @GStocks123 posted. This time Qualcomm refers to it in conjunction with Snapdragon mobile platforms and the Qualcomm Hexagon DSP, which seems to indicate that they consider it "highly beneficial to quantize values to smaller representations, down to as low as 4-bit". Why else would they mention it directly after discussing Snapdragon and Hexagon, if it didn't improve the actual performance, latency, of these two specific processors??

Naturally I don't want to get everyone too excited and will leave you to draw your own conclusions.

B



View attachment 17449

Exploring AIMET’s Post-Training Quantization Methods

*/ AIMET White Paper

developer.qualcomm.com

In this article posted on 14 August 2022, it refers to Qualcomm's new Snapdragon 8 Gen 1 and it says it has "an upgraded Hexagon NPU/DSP with a 2x faster tensor accelerator than the Snapdragon 888".

I think this is the first time I've ever heard Hexagon described as having been upgraded and it's also the first time I've heard it referred to it as Hexagon NPU/DSP becasue previously it was just called Hexagon DSP.

Does anyone (@Diogenese) think this upgraded NPU version could be one with Akida quantizing down to 4-bit?

Don't worry if you don't have a clue as to what I'm talking about, because, to be honest, I don't really either.

Snapdragon 8 Gen 1 Vs A15 Bionic How Qualcomms New Chip Compares - pokemonwe.com

Snapdragon 8 Gen 1 Vs A15 Bionic How Qualcomms New Chip ComparesThe Snapdragon 8 Gen 1 uses a newer fabrication process and has more CPU cores compared to Apple's A15 Bionic, but does that make it faster?

pokemonwe.com

 

[Frank Zappa]

That's the closest I have come to reading a physical newspaper in a very long time. And I mean decades!

I am actually going to go to the newsagents and buy the Australian Financial Review as I read that 2—3 times a week years ago and enjoyed doing it . Why I stopped I do not remember. I see old farts reading them in coffee ️ shops . Maybe there is a renaissance happening like vinyl and now cassettes.

 

[equanimous]

@Diogenese

Would love to hear your thoughts on this.

https://arxiv.org/pdf/2209.11891.pdf

[Submitted on 24 Sep 2022]

Neuromorphic Integrated Sensing and Communications​

Jiechen Chen, Nicolas Skatchkovsky, Osvaldo Simeone


V. CONCLUSIONS In this paper, we have proposed a novel ISAC solution that leverages the synergy of neuromorphic computing and IR transmission for both data transmission and radar detection. Data are encoded on an IR waveform that is used for the dual purpose of data decoding and target sensing. A single- or dualSNN receiver architecture is considered to estimate data and the presence/absence of a target. Experiments have demonstrated the advantage of the proposed neuromorphic ISAC (NISAC) over conventional separate sensing and communications in terms of normalized test throughput and radar test detection error.

Regarding published article:

Nicolas Skatchkovsky Principal supervisor is

Professor Osvaldo Simeone​

21 April 2022

Research into smart radio environments wins 'outstanding paper' award​

Research into 6G recognised


Professor Osvaldo Simeone
King’s Professor Osvaldo Simeone, Professor of Information Engineering, is one of the co-authors of the winning paper in the IEEE Communications Society Outstanding Paper Award for 2022.
The research is an international collaboration between universities and industry in several countries. It looks at how reconfigurable intelligent surfaces (RISs) can enable the development of ‘smart’ radio environments that can provide uninterrupted wireless connectivity, and transmit data by recycling existing radio waves, comparing this to established methods of installing smaller-scale relay stations.
Previous generations of wireless communication systems treated the radio propagation environment, created by the specific configurations of objects between transmitter and receiver, as fixed. In contrast, 6G will aim at shaping the propagation medium via the introduction of reconfigurable intelligent surfaces (RISs) to realize the concept of "smart" radio environments. This will be done by leveraging the unique properties of metamaterials and inexpensive antennas, which will be installed on buildings, vehicles, and other stationary or moving objects.
King’s has established expertise in the development of 6G through the Centre for Telecommunications Research and played a key role in defining theoretical tools and metrics used in the study. Commenting on the award, Osvaldo said:

The award recognises an international collaboration -- spanning Europe, the UK, Israel, and Singapore and involving both academic and industry researchers -- which addresses a timely fundamental technological question of relevance for 6G. I am honoured to have been selected, and I look forward to a continued collaboration with my co-authors.”–

​

Osvaldo Simeone​

Professor of Information Engineering

Research into smart radio environments wins 'outstanding paper' award

Research into 6G recognised

www.kcl.ac.uk

 

[Adam]

SNUFA 2022

Spiking Neural networks as Universal Function Approximators

snufa.net

SNUFA 2022​

Spiking Neural networks as Universal Function Approximators​

SNUFA 2022​

Brief summary. This online workshop brings together researchers in the fields of computational neuroscience, machine learning, and neuromorphic engineering to present their work and discuss ways of translating these findings into a better understanding of neural circuits. Topics include artificial and biologically plausible learning algorithms and the dissection of trained spiking circuits toward understanding neural processing. We have a manageable number of talks with ample time for discussions.

Executive committee. Katie Schuman, Timothée Masquelier, Dan Goodman, and Friedemann Zenke.

Quick links. Register (free) Submit an abstract (before 28 Sept 2022)

Invited speakers​

• Charlotte Frenkel, TU Delft
• Priya Panda, Yale
• Yiota Poirazi, Institute of Molecular Biology and Biotechnology (IMBB)
• Yonghong Tian, Peking University

Key information​

Workshop. 9-10 November 2022, European afternoons.

Registration. Free but mandatory. Click here to register.

Abstract submission deadline. 28 September 2022. Click here to submit.

Final decisions. 12 October 2022.

Format​

• Two half days
• 4 invited talks
• 8 contributed talks
• Poster session
• Panel debate (topic to be decided, let us know if you have a good idea)

Abstract submissions​

Click here to submit. Abstracts will be made publicly available at the end of the abstract submissions deadline for blinded public comments and ratings. We will select the most highly rated abstracts for contributed talks, subject to maintaining a balance between the different fields of, broadly speaking, neuroscience, computer science and neuromorphic engineering. Abstracts not selected for a talk will be presented as posters, and there is an option to submit an abstract directly for a poster and not a talk if you prefer.

Really bad acronym for dyslexic people..

 

[Makeme 2020]

VinFast and Renesas Sign Strategic Partnership

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3. VinFast and Renesas Sign Strategic Partnership to Advance Automobile Technology

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September 26, 2022
VinFast and Renesas Sign Strategic Partnership
Hanoi, Vietnam and Tokyo, Japan – VinFast, Vietnam’s first global EV maker, and Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions, today announced that the two companies are expanding their collaboration agreement to include automotive technology development of electric vehicles (EVs) and delivery of system components. The signing ceremony of the strategic collaboration was held at VinFast’s factory in Haiphong City, Vietnam earlier this month, which was attended by VinFast’s CEO, Le Thi Thu Thuy and Renesas’ CEO, Hidetoshi Shibata.
As part of the newly expanded agreement, Renesas will provide a broader range of products to VinFast, which will include SoCs, microcontrollers, analog and power semiconductors. Renesas will also provide technical support to assist VinFast in developing future automotive applications and mobility services.
By gaining access to Renesas' leading-edge technologies and expertise in the automotive industry, VinFast will accelerate the development of new EVs and market expansion with the aim to aggressively increase its annual production and sales.
The two companies will regularly share product development roadmaps, market trends and requirements, project implementation progress as well as new cooperation opportunities.
“VinFast is on a course of market expansion worldwide and mass production to ensure the highest vehicle performance and timely delivery to customers” said Le Thi Thu Thuy, Vice Chairwoman of Vingroup and Global CEO of VinFast. “This new partnership with Renesas will give VinFast access to both advanced in-vehicle semiconductor technology as well as high-level system expertise, with the aim to accelerate the development of safe and sophisticated EVs for global markets.”
“We are committed to supporting the local industry in Vietnam through talent development and business expansion. Since founding our design center in Ho Chi Minh City in 2004, we have continued to expand our presence in Vietnam. We also established a second design center in Da Nang this April,” said Hidetoshi Shibata, President and CEO of Renesas. “The collaboration with VinFast reinforces our commitment. We are thrilled to join VinFast’s journey for their global growth beyond Vietnam. By making EVs more widely available, I am convinced we can lead a greener, safer, and more sustainable way of living.”
VinFast and Renesas have previously collaborated on automotive infotainment systems, and Renesas’ SoCs (System-on-Chips), R-Car, and analog products have already been implemented in VinFast's new VF8 and VF9 EV models.

About VinFast​

VinFast – a member of Vingroup – envisioned to drive the movement of global smart electric vehicle revolution. Established in 2017, VinFast owns a state-of-the-art automotive manufacturing complex with globally leading scalability that boasts up to 90% automation in Hai Phong, Vietnam. Strongly committed to the mission for a sustainable future for everyone, VinFast constantly innovates to bring high-quality products, advanced smart services, seamless customer experiences, and pricing strategy for all to inspire global customers to jointly create a future of smart mobility and a sustainable planet. Learn more at: https://vinfastauto.us.

About Vingroup​

Established in 1993, Vingroup is one of the leading private conglomerates in the region, with a total capitalization of $35 billion USD from three publicly traded companies (as of November 4, 2021). Vingroup currently focuses on three main areas: Technology and Industry, Services and Social Enterprise. Find out more at: https://www.vingroup.net/en.

About Renesas Electronics Corporation​

Renesas Electronics Corporation (TSE: 6723) empowers a safer, smarter and more sustainable future where technology helps make our lives easier. A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at renesas.com. Follow us on LinkedIn, Facebook, Twitter, YouTube, and Instagram.
All names of products or services mentioned in this press release are trademarks or registered trademarks of their respective owners.

---

The content in the press release, including, but not limited to, product prices and specifications, is based on the information as of the date indicated on the document, but may be subject to change without prior notice.

 

[Makeme 2020]

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New Integrated Software Development Environment Supports Multi-Chip ECUs, Reducing Development Time and Post-Design Modifications
September 27, 2022
Integrated Development Environment for Automotive SW Development
TOKYO, Japan ― Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions, today launched a new integrated development environment that allows engineers to rapidly create software for automotive ECUs (Electronic Control Units) containing multiple hardware devices. The fully integrated environment supports co-simulation, debug and trace, high-speed simulation and distributed processing software over multiple SoCs (System-on-Chips) and MCUs (Microcontrollers)—all without the need for actual hardware. This software development environment recognizes the automotive industry’s shift toward “Software First” product development, in which a vehicle’s value is increasingly defined by its software, as well as the “Shift Left” software design approach, which emphasizes software verification and validation earlier in the development cycle, before hardware is available. The first development environment tools are available now for the- R-Car S4 and RH850/U2A devices.
“Renesas is committed to providing a development environment that helps our automotive customers realize their vision for Software First, while continuing to support their evolution toward Shift Left software development," said Hirofumi Kawaguchi, Vice President of Renesas' Automotive Software Development Division. “We are confident that this development environment will help our customers transform their E/E architecture and facilitate the early development of ECUs and new products, and ultimately deliver more value.”

Integrated Development Environment for ECU Development with Multi-Device Configuration​

Renesas’ integrated development environment with multi-device support enables software development at the ECU level, adding additional value in vehicles and contributing to the Software First approach. By providing a simulation environment from early stages of product development, the platform enables verification and application development before production of actual devices and ECUs, realizing the Shift Left concept.
The integrated environment offers the following development support:
1. Co-simulation environment for multi-devices facilitating optimal system design
By integrating and connecting simulators such as the R-Car Virtual Platform, which was previously provided for single-chip individual devices such as SoCs and microcontrollers, Renesas is delivering a new simulation environment for multi-device operation. Designs can now be optimized by balancing different application functions and incorporating software verification at the systems level. A development tool that automatically generates software code for devices and a simulation environment for verification from MATLAB® /Simulink® models will also be available. These tools will allow engineers to evaluate performance and start application development before hardware and ECUs are in production.
2. Debug and trace tool for multi-devices to visualize problems
To make it easy to visualize how software operates internally, Renesas is providing a debug and trace tool that allows simultaneous and synchronized execution, execution control by breakpoints and information tracing for ECUs containing multiple devices. With this tool, users can visualize processing flows, evaluate performance profiles, and anticipate problems that may arise from operating multiple devices which are intricately linked within the same ECU. Renesas plans to implement the same functionality mentioned above (1) in the multi-device co-simulation environment so that debugging and tracing can be performed on a computer without an ECU.
3. High-speed simulator for software development that achieves rapid and large-scale simulations
Typically, in ECU-level simulations, the target software tends to be large and the simulation execution takes a long time. This new high-speed simulator is based on QEMU, an open-source virtual environment that models SoCs and microcontrollers at a high level of abstraction, enabling faster ECU-level simulation of complex software.
4. Distributed Processing Software for multi-devices that enables design without considering hardware configuration
This software enables optimal distribution of application functions to CPUs and IPs inside different SoCs and microcontrollers in an ECU, maximizing hardware performance. With this software, engineers can develop applications rapidly, without being constrained by the ECU hardware configuration. For example, developers can add an AI accelerator to an existing ECU to boost system performance, without having to re-design the application to accommodate the new device.
The new development platform is designed to reduce the impact on the environment by providing a turn-key solution that accelerates time to market and saves energy.

Availability​

• Co-simulation environment for multi-devices (Available today)
  www.renesas.com/software-tool/co-simulation-environment-multi-devices
• Debug and trace tools for multi-devices (Available today)
  www.renesas.com/software-tool/debug-and-trace-tools-multi-devices
• High-speed simulator for software development (Available in December 2022)
  www.renesas.com/software-tool/high-speed-simulator-software-development
• Distributed processing software for multi-devices (Available in December 2022)
  www.renesas.com/software-tool/distributed-processing-software-multi-devices

About Renesas Electronics Corporation​

Renesas Electronics Corporation (TSE: 6723) empowers a safer, smarter and more sustainable future where technology helps make our lives easier. A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at renesas.com. Follow us on LinkedIn, Facebook, Twitter, YouTube, and Instagram.
(Remarks) MATLAB and Simulink are registered trademarks of The MathWorks, Inc. All names of products or services mentioned in this press release are trademarks or registered trademarks of their respective owners.

 

[cosors]

I would like to bring here again a small story from my kinship to put everything in relation, because it fits better to the world events now. The great aunt became 101 years old and let life go because she no longer wanted or needed it, was healthy and her head top fit. She had achieved everything and looked at her huge clan. She told at the very end a story from her life that she kept secret until the end because she was ashamed, she was doing very well financially but not then. The great economic depression. She was supposed to buy bread for her family, which she did. A customer had previously forgotten some rolls in the bakery. She pocketed them and ate them secretly because everyone was starving. At home she handed in the bread. She didn't talk about it with anyone for almost a hundred years because she was so ashamed. These are relations that we cannot imagine today. We should all be grateful for our lives no matter how hard it is sometimes. The SP is negligible compared to this truth. I am grateful to be a part of this brilliant community. Sure it is a pity that today my TLGs fell 14% on no news but it does not matter if I can lead a fullfilled life. This little story always grounds me.
The other branch of the family had to flee from the Russians - no one was involved in the war, a Nazi or in the party - and about half of that family members died on the run. For some in this country gender-appropriate wording is still the issue of all and right now. The SP does what it does. Just patiently believe in the team. It will not disappoint. I am sure of that.
For me the concept of life is shaped by relations.

Yesterday I mentioned 14% down and today it is already balanced - offtake!
As if someone had given a nudge

 

[equanimous]

Interesting. Whats South Korea got brewing?

 

[Violin1]

I'm not sure my little order did anything for our SP but it does seem that the low 80s is a pretty good resistance point. As FF would say, just a bit under one half of one percent of the free float sold today and bounced about 5%. Now, given we are almost at the end of September, it must be time to predict revenue for the quarter lol.

I am going to say it'll be modest, maybe a million or so. No major scale up for another quarter or two. My real interest is in whether we see a line in the quarterly related to royalties. That would be something special.

Akida ballista

 

[Diogenese]

@Diogenese

Would love to hear your thoughts on this.

https://arxiv.org/pdf/2209.11891.pdf

[Submitted on 24 Sep 2022]

Neuromorphic Integrated Sensing and Communications​

Jiechen Chen, Nicolas Skatchkovsky, Osvaldo Simeone


V. CONCLUSIONS In this paper, we have proposed a novel ISAC solution that leverages the synergy of neuromorphic computing and IR transmission for both data transmission and radar detection. Data are encoded on an IR waveform that is used for the dual purpose of data decoding and target sensing. A single- or dualSNN receiver architecture is considered to estimate data and the presence/absence of a target. Experiments have demonstrated the advantage of the proposed neuromorphic ISAC (NISAC) over conventional separate sensing and communications in terms of normalized test throughput and radar test detection error.

Hi eq,

Well I was stumped first ball, the reference to IR in the abstract - not infra-red but impulse radio.

Turns out this is also referred to as UWB (ultra-wide band radio) - a bit like spread-spectrum, but different.

It is very fast, short range communication (> 500 Mb/s).

Like every schoolboy's dream, it can see through walls.

https://en.wikipedia.org/wiki/Ultra-wideband

Radar[edit]​

Ultra-wideband gained widespread attention for its implementation in synthetic aperture radar (SAR) technology. Due to its high resolution capacities using lower frequencies, UWB SAR was heavily researched for its object-penetration ability.[36][37][38] Starting in the early 1990s, the U.S. Army Research Laboratory (ARL) developed various stationary and mobile ground-, foliage-, and wall-penetrating radar platforms that served to detect and identify buried IEDs and hidden adversaries at a safe distance. Examples include the railSAR, the boomSAR, the SIRE radar, and the SAFIRE radar.[39][40] ARL has also investigated the feasibility of whether UWB radar technology can incorporate Doppler processing to estimate the velocity of a moving target when the platform is stationary.[41] While a 2013 report highlighted the issue with the use of UWB waveforms due to target range migration during the integration interval, more recent studies have suggested that UWB waveforms can demonstrate better performance compared to conventional Doppler processing as long as a correct matched filter is used.[42]

Ultra-wideband pulse Doppler radars have also been used to monitor vital signs of the human body, such as heart rate and respiration signals as well as human gait analysis and fall detection. It serves as a potential alternative to continuous-wave radar systems since it involves less power consumption and a high-resolution range profile. However, its low signal-to-noise ratio has made it vulnerable to errors.[43][44] A commercial example of this application is RayBaby, which is a baby monitor that detects breathing and heart rate to determine whether a baby is asleep or awake. Raybaby has a detection range of five meters and can detect fine movements of less than a millimeter.[45]

Ultra-wideband is also used in "see-through-the-wall" precision radar-imaging technology,[46][47][48] precision locating and tracking (using distance measurements between radios), and precision time-of-arrival-based localization approaches.[49] It is efficient, with a spatial capacity of approximately 1013 bit/s/m2.

The paper describes the use of either one or two SNNs to interpret the signals - clearly a job in which Akida could be employed to advantage.

A 2-stage Akida is already used in key-word spotting.

 

[DingoBorat]

Wait for it...
Today's results are still being tabulated

 

[krugerrands]

Just one tiny point acceleration is not Artificial Intelligence.

The industry quite bluntly lies in all its advertising when it describes a semiconductor as an Ai accelerator where the edge is concerned.

An Ai accelerator at the edge is simply compressing data to send it more efficiently to somewhere else to be processed.

SiFive X280 is as they say an accelerator full stop. The only way they can claim it to be an Intelligence Series is if they add Ai that does some processing of the sensor data before it is sent to somewhere else for action. Which is where AKIDA comes in.

Otherwise in truth it is not the Intelligence Series it is the Accelerator Series.

Now if they wanted they could add Loihi 2 to the X280 to make it intelligent but of course it is not commercially available.

Of SiFive’s published partners the only partner supplying Ai to make X280 intelligent is Brainchip.

So it is of course an add on but if you don’t add it on you don’t get intelligence you get acceleration.

It is like going into a car dealership to buy a new car and when it’s delivered there are no wheels. When you point this out the sales person says wheels are an extra. You didn’t say you wanted wheels.

Buying an Intelligence Series processor without the intelligence is pretty unintelligent.

My opinion only DYOR
FF

AKIDA BALLISTA

Haha....yes.
Distinction is important.
And unfortunately this fine point will only be appreciated by the few untill it becomes plain to see through differentiated products, where understanding is not required.

We "know" that the terms "machine learning" and "artificial intelligence" are misnomers.
This article was actually a nice little history lesson.

Very frustrating that these type of things get misrepresented.

You would almost have to come up with a new term to differentiate real AI from all that has gone before.

Much like "DLE" ( Direct lithium extraction ) in the lithium industry.
Every second wannabe producer is saying they do DLE as if DLE is a single turnkey technology.
Instead there are different flavours of this term and worse still is that it is just 1 step in the flowsheet of the chemical process to get to an end product.
Just a marketing hype term that sounds cool and allows you to gloss over the specifics...

I digress.

Yes, X280 with Akida should differentiate itself from the rest, can't wait for this to be plain to see to all.
Over 30% of my portfolio is in BRN even at current shareprice.

But in the meantime, you might have products and or people using the X280 as is, and they will still be claiming and including the wording of "can run by itself, performing inference tasks at the edge" and that does not mean it has Akida inside...... just plain pizza with no cheese.