BRN Discussion Ongoing

[Bravo]

"Best-in-class power efficiency", so they say! Whose NPU is this I wonder?

Says here the "basic R-Car X5H includes up to 32 Arm Cortex-720AE" and we know were are compatible across Arm's product range.

Renesas previously collaborated with Hailo to offer combined solutions that pair the R-Car V4H SoC with Hailo-8 AI accelerators.

However, there isn't any publicly available information indicating that Renesas and Hailo have collaborated on the R-Car X5H, at least none that I've found as yet.


View attachment 74837



Chiplets Extend Automotive SoC AI and GPU Capability

Dec. 28, 2024

Renesas’ R-Car X5H SoC, which meets ASIL B/D, provides scalable automotive compute.
William G. Wong


https://www.electronicdesign.com/print/content/55252079

• Features of the R-Car X5H automotive system-on-chip family.
• How Renesas is taking advantage of chiplets.

The R-Car X5H family is a fifth-generation automotive system-on-chip (SoC) developed by Renesas that supports ASIL B/D capabilities as well as a neural processing unit (NPU). Built on the latest 3-nm chip technology, enhanced versions of the SoC come courtesy of chiplet technology. I talked with Cyril Clocher, Senior Director of the Automotive Product Line, about the details.

High-Performance Compute for Automotive Safety-Critical Apps​

The basic R-Car X5H includes up to 32 Arm Cortex-720AE applications cores capable of delivering 1000K DMIPS of performance (Fig. 1). Real-time support is provided by half-a-dozen Arm Cortex-R52 cores with dual lockstep capability. These can deliver 60K DMIPS of performance while meeting ASIL B and ASIL D certification requirements.

Renesas
View attachment 74834




1. The Renesas R-Car X5H includes 32 Arm Cortex-720AE applications cores, six Arm Cortex-R52 cores with lockstep support, an NPU, and a GPU.

There are general-purpose DSP cores, too, along with specialized accelerators such as the image signal processor (ISP) and dense-optical-flow (DOF) hardware accelerator (HWA) for handling multi-megapixel camera video streams.
The on-chip NPU can deliver up to 400 TOPS, while the on-chip GPU generates 4 TFLOPS of performance.
The chip includes an 8-port Ethernet switch, USB 2/3 ports, and PCI Express (PCIe) that supports Gen 4 and Gen 6. Also in the mix are an on-chip dedicated NPU and GPU. The GPU can drive a car’s display panel while the NPU handles artificial-intelligence and machine-learning (AI/ML) models.

Enhanced Automotive Chips Utilize UCIe​

While the basic R-Car X5H monolithic chip is very impressive, it is designed to be enhanced using chiplets that employ Universal Chiplet Interconnect Express (UCIe) connectivity (Fig. 2). It can include up to two chiplets.

Renesas

2. The R-Car X5H can be enhanced by including an NPU and GPU chiplet.

Renesas has two types of chiplets that can be included in enhanced versions of the R-Car SoC—again, an NPU and a GPU. These are designed to augment the functionality of the built-in NPU and GPU. The chiplet and on-chip NPU are able to run a separate set of AI/ML models. Likewise, the GPU can drive additional displays.

Building a Software-Defined Vehicle​

The R-Car X5H family is destined for new automobiles including software-defined vehicles (SDVs). Thanks to the massive amount of computing power, the chip can handle everything from the advanced driver-assistance system (ADAS) to driving automation.
Renesas’ R-Car Open Access (RoX) SDV platform helps get developers up to speed by simplifying their development chores (Fig. 3). It works with a variety of pre-integrated operating systems and frameworks, tying them into the Arm Cortex-A720AE and Cortex-R52 compute arrays. It utilizes open-source software and standard. APIs. Software built on the reference stacks can be turned into products.

Renesas

3. The R-Car Open Access (RoX) SDV platform supports pre-integrated operating systems and frameworks.

Chiplets Extend Automotive SoC AI and GPU Capability

Renesas’ R-Car X5H SoC, which meets ASIL B/D, provides scalable automotive compute.

www.electronicdesign.com

I think it's great to see NimbleAI combining AKIDA 1500 with the Hailo-8 accelerator for inference processing for their prototype.

Why? Because, as mentioned in the post above, Renesas utilised Hailo-8 AI accelerators for the Renesas' R-Car V4H SoC.

So, the news from NimbleAI further bolsters my hope that our tech may be included in the upcoming Renesas R-Car X5H. Surely NimbleAI can't be the only ones to think that pairing Akida and Hailo is a good idea, can they?

What is also interesting is that IKERLAN is the coordinator of the NimbleAI project.

IKERLAN also happens to be an Associated Partner in the iSense consortium, a European Doctoral Network focused on in-situ monitoring of electromagnetic interference (EMI). Other associated partners in the consortium include - you guessed it - Renesas, as well as Airbus, Valeo, Thales, Phillips and Canon amongst others. So I live in hope that the consortium members, such as Renesas, would be aware of NimbleAI's work.

Incidentally, in relation to the iSense consortium and the in-situ monitoring of electromagnetic interference (EMI), I asked ChatGPT whether BrainChip's neuromorphic technology could help with in-situ monitoring of EMI, by way of the tech being incorporated into some sort of smart sensor and ChatGPT response to this question was extremely optimistic which you judge for yourself from the extract below.

iSense Associated Partneres

ChatGPT response

Associated Partners – iSENSE

dn-isense.eu

 

[Diogenese]

BrainChip at #CES2025: Day 3 Recap | BrainChip

BrainChip at #CES2025: Day 3 Recap Day 3 brought exciting milestones as CMO Steve Brightfield appeared live on "The Gadget Guy" discussing neuromorphic computing's critical role in advancing #EdgeAI. All Things AI podcast included conversations with Jeff Bier, founder of the Edge AI and Vision...

www.linkedin.com

View attachment 75668

Have I missed something, or did the Akida 2 FPGA just expose itself?

 

[Diogenese]

Have I missed something, or did the Akida 2 FPGA just expose itself?

So were the chips that BRN supplied to DeGirum the FPGA chips?

That would make sense as that was the stated purpose of the FPGA chips.

 

[keyeat]

BrainChip at #CES2025: Day 3 Recap | BrainChip

BrainChip at #CES2025: Day 3 Recap Day 3 brought exciting milestones as CMO Steve Brightfield appeared live on "The Gadget Guy" discussing neuromorphic computing's critical role in advancing #EdgeAI. All Things AI podcast included conversations with Jeff Bier, founder of the Edge AI and Vision...

www.linkedin.com

View attachment 75668

Great to see Pia hard at work liking this post ! Money well spent !

 

[Diogenese]

Have I missed something, or did the Akida 2 FPGA just expose itself?

All you techies, please note the enormous amount of self-restrainf displayed by the absence of any reference to flash memory.

 

[Bravo]

All you techies, please note the enormous amount of self-restrainf displayed by the absence of any reference to flash memory.

That's OK. My memory isn't all that flash either.

 

[DK6161]

Great to see Pia hard at work liking this post ! Money well spent !

Bonus shares coming!!!

 

[DingoBorat]

So were the chips that BRN supplied to DeGirum the FPGA chips?

That would make sense as that was the stated purpose of the FPGA chips.

My very rough understanding of FPGAs is that they are like Integrated Circuits, done on an electronics bread board..

They work like the final product, while being adjustable, but are basically hand made "chips" which by that very nature, are extremely low volume..

As in, you "cannot" do a "run" of them..

I know that's oversimplifying things a lot but I like to simplify things.. May even be completely off track?..

My thinking, is that it gives prospective customers, a Real World look, at what AKIDA 2.0 can do, beyond simulation, without actually being "proven" in silicon?..

Although, what makes AKIDA technology "special" has been proven, with AKD1000 and AKD1500, in two separate foundry processes.

 

[Fenris78]

An announcement regarding the sub contractor details for the US airforce radar contract would ber nice. Hopefully it's Raytheon and commercial products flow from this partnership.

 

[Pom down under]

Great to see Pia hard at work liking this post ! Money well spent !

Only cost the company a few million for the like

 

[TECH]

Good afternoon back in Australia,

I'm sure others read my posts, so wherever you are in the world, gidday !

I have just listened to the first podcast hosted by Steve Brightfield, what a relaxed professional, I loved it, he's not a journalist, he's
a veteran technology professional, having been in the industry for 35 plus years, it shows !

This next point is important, this is the positive effect Sean has had since coming on board, he has targeted (in my opinion) top class,
mature executive type staff, surrounding himself with guns, not to dissimilar to what Peter and Anil did in the early years, surrounding
themselves with top class PHD Scientists and Electrical Engineers.

Steve has brought his old mate Bill on board, they met as young blokes (35 years ago) so the trust and friendship is solid, that's
what I'm talking about, those types of relationships open up DOORS !

Listen carefully to what Bill says, within 5 minutes of logging into Degirum, Brainchip software is ready to give you benchmarks for
what you are looking for.

"Your team (Brainchip) is available to support us ASAP, you're in California, we're in Silicon Valley"

"A lot of people are trying it" (Brainchip, that is)

Are we getting any traction ?

Do we have the attention of a number of "major players" ?

Is the general tech industry finally starting to get a handle on Edge AI, and more specifically Spiking Neural Networks ?

Is/Was CES 2025 all about AI and weeding out the hype and getting down to the "Real Disruptors" who are the "Real Deal"?

Forget the current share price, Bottsie is having a field day, buying and selling to itself, do you think all our partners and current
engagements give a S... about the day to day bullshit, they are engaged with a company that has the goods, and the ones who
have the "real investment dollars" are getting to know it, faster and faster as this "evolutionary game" plays out !!

Talk about the Nasdaq is a total fantasy for us, in my opinion it will only happen in a take over scenario plays out and the name
Brainchip will sadly be a distant memory, sorry, but that's how I see it over the next 5 years.

More to come..........have a top weekend.......Tech.

 

[DingoBorat]

Good afternoon back in Australia,

I'm sure others read my posts, so wherever you are in the world, gidday !

I have just listened to the first podcast hosted by Steve Brightfield, what a relaxed professional, I loved it, he's not a journalist, he's
a veteran technology professional, having been in the industry for 35 plus years, it shows !

This next point is important, this is the positive effect Sean has had since coming on board, he has targeted (in my opinion) top class,
mature executive type staff, surrounding himself with guns, not to dissimilar to what Peter and Anil did in the early years, surrounding
themselves with top class PHD Scientists and Electrical Engineers.

Steve has brought his old mate Bill on board, they meet as young blokes (35 years ago) so the trust and friendship is solid, that's
what I'm talking about, those types of relationships open up DOORS !

Listen carefully to what Bill says, within 5 minutes of logging into Degirum, Brainchip software is ready to give you benchmarks for
what you are looking for.

"Your team (Brainchip) is available to support us ASAP, you're in California, we're in Silicon Valley"

"A lot of people are trying it" (Brainchip, that is)

Are we getting any traction ?

Do we have the attention of a number of "major players" ?

Is the general tech industry finally starting to get a handle on Edge AI, and more specifically Spiking Neural Networks ?

Is/Was CES 2025 all about AI and weeding out the hype and getting down to the "Real Disruptors" who are the "Real Deal"?

Forget the current share price, Bottsie is having a field day, buying and selling to itself, do you think all our partners and current
engagements give a S... about the day to day bullshit, they are engaged with a company that has the goods, and the ones who
have the "real investment dollars" are getting to know it, faster and faster as this "evolutionary game" plays out !!

Talk about the Nasdaq is a total fantasy for us, in my opinion it will only happen in a take over scenario plays out and the name
Brainchip will sadly be a distant memory, sorry, but that's how I see it over the next 5 years.

More to come..........have a top weekend.......Tech.

I disagree that a NASDAQ listing, is a "total fantasy" Tech ...

It is, while we are unprofitable.

But with strong profits down the track (hopefully within the next 2 to 5 years, the sooner the better) I think a NASDAQ listing, would then become a certainty.

 

[Diogenese]

Anastasi does IBM analog NN:



Discussion of analog error from about 10:00

13.30: 92.8% accuracy

 

[TECH]

I disagree that a NASDAQ listing, is a "total fantasy" Tech ...

It is, while we are unprofitable.

But with strong profits down the track (hopefully within the next 2 to 5 years, the sooner the better) I think a NASDAQ listing, would then become a certainty.

Fair enough Dingo...but I think you may have misread what I was trying to say.

To gain entry onto the Nasdaq we have to overcome a number of hurdles, one which you have eluded to is "revenue" as in "profit."

I do believe that our technology will ultimately end up on the big tech boards of the Nasdaq, but NOT as Brainchip Holdings Ltd, but
under another name of a potential suitor, who will pounce when they consider we are gaining to much of the market share and need
to gobble us up...........so yes the Nasdaq, but not as Brainchip on the Nasdaq........in my opinion of course.

Cheers Tech.

 

[7für7]

Fair enough Dingo...but I think you may have misread what I was trying to say.

To gain entry onto the Nasdaq we have to overcome a number of hurdles, one which you have eluded to is "revenue" as in "profit."

I do believe that our technology will ultimately end up on the big tech boards of the Nasdaq, but NOT as Brainchip Holdings Ltd, but
under another name of a potential suitor, who will pounce when they consider we are gaining to much of the market share and need
to gobble us up...........so yes the Nasdaq, but not as Brainchip on the Nasdaq........in my opinion of course.

Cheers Tech.

As long as I get my millions they can do what they want after that.. if not, I will be happy to hold long

 

[DingoBorat]

Fair enough Dingo...but I think you may have misread what I was trying to say.

To gain entry onto the Nasdaq we have to overcome a number of hurdles, one which you have eluded to is "revenue" as in "profit."

I do believe that our technology will ultimately end up on the big tech boards of the Nasdaq, but NOT as Brainchip Holdings Ltd, but
under another name of a potential suitor, who will pounce when they consider we are gaining to much of the market share and need
to gobble us up...........so yes the Nasdaq, but not as Brainchip on the Nasdaq........in my opinion of course.

Cheers Tech.

Fair enough too Tech

Any number of scenarios could play out and any, which involve the AKIDA/TENNs technologies being "market" successful, will make everyone here, with significant holdings, extremely happy.

But still (and as you have noted "sadly") I'd much prefer to have all that and see the name "BrainChip" up in shining lights.





But not a billionaire, he dreaming..

Travie McCoy Net Worth

What is Travie McCoy's net worth?

www.celebritynetworth.com

"Travie McCoy is an American singer, rapper, and songwriter who has a net worth of $2 million."

 

[Taproot]

Have I missed something, or did the Akida 2 FPGA just expose itself?

Nice pick up.
That's exciting.
Hopefully a little more information is made available.
Who manufactured these chips ? Intel ? or Xilinx ?
How many have been produced ?
Maybe we'll learn more about costs associated in the upcoming quarterly.
In any event " Bloody Bagus Sekali "
So, Akida 2 FPGA's and a room full of blokes from RTX,
Nooice.

 

[Diogenese]

My very rough understanding of FPGAs is that they are like Integrated Circuits, done on an electronics bread board..

View attachment 75683

They work like the final product, while being adjustable, but are basically hand made "chips" which by that very nature, are extremely low volume..

As in, you "cannot" do a "run" of them..

I know that's oversimplifying things a lot but I like to simplify things.. May even be completely off track?..

My thinking, is that it gives prospective customers, a Real World look, at what AKIDA 2.0 can do, beyond simulation, without actually being "proven" in silicon?..

Although, what makes AKIDA technology "special" has been proven, with AKD1000 and AKD1500, in two separate foundry processes.

Hi DB,

I can see your soldering iron is a bit rusty.

As you say, a gate array is an prefab IC with bunches of different logic gates and registers with selectable interconnexions.

The Programmable part means that the user can choose the interconnexions. Once upon a time, you only got one shot at proramming the interconnexions, so it was permanently programmed which was usually done on a programming device before the gate array was installed on a circuit board (eg, fusable links).

Field programmability means that the gate array interconnexions can be chosen when the FPGA is installed.

So for example, there may be a mesh network similar to that used in Akida interconnecting the gates and registers where the interconnexions are controlled by a CPU.

US2016342722A1 METHOD AND DEVICE FOR PROGRAMMING A FPGA

A method of programming a FPGA, wherein the FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the method comprises the steps of: providing a high-level configuration file containing: first data defining a set of macrocells and their relative positions; second data defining a configuration of the hardware blocks of the macrocells; and third data defining interconnections between the macrocells; wherein said high-level configuration file contains neither data defining an absolute position of the macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; converting said high-level configuration file into a bitstream file; and uploading the bitstream file into the FPGA. A semiconductor chip comprising a FPGA and a device configured for programming the FPGA are provided.

US2024020537A1 METHODOLOGY TO GENERATE EFFICIENT MODELS AND ARCHITECTURES FOR DEEP LEARNING 20210715

A system and method of generating an efficient neural network model architecture and an efficient processor for deep learning in an artificial intelligence (AI) processor are provided. The system and method to create the processor architecture as a companion to the neural network model by composing a plurality of processor architectures to enable architectural exploration. The compilation can be implemented for any arbitrary spatial processor architecture using either ASIC or FPGA devices. The processor architecture can be uniquely defined for a selected ML or AI model without having to update the software compiler.

Because the layout is not optimized as in an ASIC, the performance will be significntly below that of an ASIC, but still better than a software simulation.

 

[JDelekto]

My very rough understanding of FPGAs is that they are like Integrated Circuits, done on an electronics bread board..

View attachment 75683

They work like the final product, while being adjustable, but are basically hand made "chips" which by that very nature, are extremely low volume..

As in, you "cannot" do a "run" of them..

I know that's oversimplifying things a lot but I like to simplify things.. May even be completely off track?..

My thinking, is that it gives prospective customers, a Real World look, at what AKIDA 2.0 can do, beyond simulation, without actually being "proven" in silicon?..

Although, what makes AKIDA technology "special" has been proven, with AKD1000 and AKD1500, in two separate foundry processes.

By using FPGAs, they can update them after they have been deployed. This allows them to make tweaks for either optimization or fixing any issues that exist. In some cases, FPGAs can perform better than a general-purpose processor and include other dedicated hardware components.

Of course, they can be more expensive than pre-built hardware and more complicated to develop since they require people knowledgeable of the languages used to program them. Typically VHDL and Verilog languages are used for programming these (I had the opportunity to use Verilog for my labs in college).

I see it as an advantage to allow potential customers to implement solutions quickly (without the cost of waiting for a large batch of chips) using BrainChip's neural fabric and other functional blocks on the FPGA (like a RISC V implementation).

 

[DingoBorat]

Hi DB,

I can see your soldering iron is a bit rusty.

As you say, a gate array is an prefab IC with bunches of different logic gates and registers with selectable interconnexions.

The Programmable part means that the user can choose the interconnexions. Once upon a time, you only got one shot at proramming the interconnexions, so it was permanently programmed which was usually done on a programming device before the gate array was installed on a circuit board (eg, fusable links).

Field programmability means that the gate array interconnexions can be chosen when the FPGA is installed.

So for example, there may be a mesh network similar to that used in Akida interconnecting the gates and registers where the interconnexions are controlled by a CPU.

US2016342722A1 METHOD AND DEVICE FOR PROGRAMMING A FPGA

View attachment 75689

A method of programming a FPGA, wherein the FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the method comprises the steps of: providing a high-level configuration file containing: first data defining a set of macrocells and their relative positions; second data defining a configuration of the hardware blocks of the macrocells; and third data defining interconnections between the macrocells; wherein said high-level configuration file contains neither data defining an absolute position of the macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; converting said high-level configuration file into a bitstream file; and uploading the bitstream file into the FPGA. A semiconductor chip comprising a FPGA and a device configured for programming the FPGA are provided.


Because the layout is not optimized as in an ASIC, the performance will be significntly below that of an ASIC, but still better than a software simulation.

Ah yes, of course!
Now I understand, completely..


No wonder Anastasi won't return "my" calls ...