To further expand on my post now I have some time to grab the info.
The snips below are from a NASA paper Aug last year that outlines the RadNeuro Project that we know we have been involved in with other partners and the hardware issues.
NASA refers to neuromorphic chips / computing as NMC and can see why someone like Alphacore etc may want to get a rad hard chip in there....how our SNN IP would be affected (if at all)....above my pay grade @Diogenese
Sorry D...caught up with Chelsea again
Original paper HERE
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Julian says "hi".
"The most important function to preserve in avionics is the memory, which suffers bit upsets that may not be detectable
or correctable."So there may be a place for MemRistors/ReRAM because they are more naturally rad-hard and do not store information in the same way as CMOS bits are stored.
In other words, a hybrid technology of CMOS on FDSOI and ReRAM may be a solution. Some of my almost fully depleted neurons keep spiking random scintillations of the ghostly outline of patents for such a hybrid circuit
This Intel patent contemplates using ReRAM with MOSFET/CMOS circuits:
WO2019005057A1 NON-VOLATILE LOGIC CIRCUIT EMPLOYING LOW-POWER MOSFET ENABLED BY NON-VOLATILE LATCHED OUTPUTS
Techniques are disclosed for forming a non-volatile hybrid logic circuit employing low-power MOSFET enabled by non-volatile latched outputs. The hybrid arrangement is able to achieve both circuit-level non-volatility and relatively lower power levels, neither of which can be attained using MOSFET/CMOS or non-volatile logic/memory elements on their own. Further, standard MOSFET/CMOS alone cannot be used with relatively low threshold voltages (VTs) due to leakage currents and lack of non-volatility during power gating, for example. Accordingly, the non-volatile elements of the hybrid circuit serve as flip-flops or register files to provide non-volatile latched outputs for preserving the state of the logic circuit even when not receiving power. Thus, in the hybrid circuit arrangement, low-VDD, low-VT MOSFET devices are operatively coupled with non-volatile logic/memory elements (e.g., spintronic devices, ferroelectric devices, magnetoresistive devices) to enable energy efficient, low-VDD, low-VT, non-volatile operation for a logic circuit.
the non-volatile element may include at least one of a spin-torque switched magnet, spin-hall effect- switched magnet, ferroelectric field-effect transistor (FeFET), ferroelectric capacitor, magnetic tunnel junction (MTJ), resistive random-access memory (ReRAM or RRAM), or magneto-electric-switched magnet.
Western Digital:
WO2023064005A1 HYBRID MEMORY MANAGEMENT OF NON-VOLATILE MEMORY (NVM) DEVICES FOR USE WITH RECURRENT NEURAL NETWORKS
Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.
Neural Turing Machines (NTMs), or more generally Memory Augmented Neural Networks (MANNs), are types of recurrent neural networks. An NTM has a neural network controller coupled to external memory resources with which the controller interacts using attentional mechanisms (e.g. mechanisms that focus the attention of the network on particular portions of data stored in the external memory). NTMs have the potential to accelerate the manner by which RNNs process information. There is an on-going need to provide improvements within NTMs, MANNs, and other RNNs, and with devices that are configured to implement NTMs, MANNs, and other RNNs.
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