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BRN Discussion Ongoing
- Thread starter TechGirl
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Lassen Peak have several patent applications, all totally innocent of neural networks. It's basically a photo-fit ID system, so clearly Akida would supercharge it.
The most recently published is:
WO2022250862A1 SYSTEMS AND METHODS FOR NONINVASIVE DETECTION OF IMPERMISSIBLE OBJECTS USING DECOUPLED ANALOG AND DIGITAL COMPONENTS Priority: US202163192540P·2021-05-24; US202217734079A·2022-05-01
A system for scanning targets for concealed objects comprises a set of analog imaging components of a portable radar system with both a ranging resolution and lateral resolution sufficient to detect an object concealed on a person, where the analog imaging components are contained with a first housing and in communication with digital processing components contained in a second housing, where the digital processing components are configured to receive imaging information from the analog components for processing. Each housing is configured to be attached to a user's article of equipment.
[0024] For example, lens 120 can be a Luneberg lens of the type or types described in U.S. Patent Application No. 63/161,323, the contents of which are hereby incorporated in their entirety. [024] In an embodiment, core processing system 102 includes processor 103 and custom logic 104. Processor 103 is configured to process instructions to render or display images, initiate a scan, process the results of a scan, alert the user, and provide the results of an object match, if any, to the user. Processor 103 can be any of a variety and combination of processors, and can be distributed among various types and pieces of hardware found on the apparatus, or can include hardware distributed across a network. Processor 103 can be an ARM (or other RISC-based) processor. Additionally, such processors can be implemented, for example, as hardware modules such as embedded microprocessors, Application Specific Integrated Circuits (“ASICs”), and Programmable Logic Devices, including flash memory (“PLDs). Some such processors can have multiple instruction executing units or cores. Such processors can also be implemented as one or more software modules in programming languages as Java, C++, C, assembly, a hardware description language, or any other suitable programming language. A processor according to some embodiments includes media and program code (which also can be referred to as code) specially designed and constructed for the specific purpose or purposes. Custom logic 104 can include one or more Field Programmable Gate Array(s) (FPGA) or any type of PLD for custom logic to support processing offload from Processor 103. In an embodiment, the term “processing offload” includes digital signal processing and digital beam forming.
Fact Finder
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Why stop there what about heart rate, blood pressure, perspiration and blood sugar even muscle tensing not to mention rapid eye movements and pupil dilation.
Fact Finder
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Don’t forget 404.
Thanks Learning.
Hi FF,
Figure 4 is a flow chart, not a circuit diagram, so each step is shown in an individual box:
[027] Memory 107 can be used to store, in computer code, artificial intelligence (“AI”) instructions, AI algorithms, a catalog of images, device configuration, an allowable, calculated, or predetermined user workflow, conditions for altering, device status, device and scanning configuration, and other metadata resulting from the scanning process. Memory 107 can be a read-only memory (“ROM”); a random-access memory (RAM) such as, for example, a magnetic disk drive, and/or solid-state RAM such as static RAM (“SRAM) or dynamic RAM (“DRAM), and/or FLASH memory or a solid-data disk (“SSD), or a magnetic, or any known type of memory. In some embodiments, a memory can be a combination of memories. For example, a memory can include a DRAM cache coupled to a magnetic disk drive and an SSD. Memory 107 can also include processor-readable media such as magnetic storage media such as hard disks, floppy disks, and magnetic tape; optical storage media such as Compact Disc/Digital Video Discs (“CD/DVDs), Compact Disc-Read Only Memories (“CD-ROMs), and holographic devices: magneto-optical storage media such as floptical disks; Solid state memory such as SSDs and FLASH memory; and ROM and RAM devices and chips.
[045] Fig. 3 is a flowchart of a method for creating a dataset of images to be used for imaging and detection, according to an embodiment. At 301, one or more images are taken. At 302, the images are sent to a processor for processing. The image or images received at the processor are increased in size by a predetermined amount creating a set of larger images, at 303. In an embodiment, the images are increased in size to achieve finer blending of the image stack in order to extract the high frequency data that is embedded in the low frequency data hidden in the aliasing.
[046] At 304, at least a subset of images in the set of larger images are aligned, according to an embodiment. In an embodiment, at 305, the layers are averaged with linear opacity 1, .5, .25, .125, and so on, allowing images, in an embodiment, to be blended evenly, making use of the aliasing.
[047] At 306, in an embodiment, the image stack, the plurality of images being combined, is sharpened using a predetermined radius. At 307, according to an embodiment, the final super image is resized. One skilled in the art will understand that the output can be resized to any desirable size using any practicable resampling method that provides an appropriate image. At 308, the super image is used to create the final image (seen in 206 from Fig. 2). Once the super image is created, the image is further processed, as detailed in Fig. 4, discussed below.
[048] Fig. 4 is a flow chart of a method for processing the existing data to create a final image. At 401, an optical image is created and mapped to the super image creating a filtered image. In an embodiment, the apparatus uses a separate camera to create an optical image used as a base image configured to be mapped to the super image, according to an embodiment. In an embodiment, the separate camera is a digital camera using a CCD sensor, or a CMOS sensor, or any practicable sensor.
Seems to be doing a lot of superfluous pre-fiddling with the sensor data.
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We've been there before for school security - did not end happily.
Fact Finder
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So @Diogenese is the Ai Engine located at 104.
Steve10
Regular
Renesas' new ARM Cortex-M85 AI chip should sell for more than $30 for volume.
The Renesas RA4 series sell for approx. $5 for volume.
The Renesas RA6 series sell for approx. $20 for volume.
The Renesas AI MPU chips with ARM Cortex-M55 sell for approx. $30 per chip.
The above are prices from Mouser electronics, a global distributor of semiconductors & electronics with over $4B in annual revenue.
Most likely Mouser Electronics will have at least 50-100% mark up so a chip they sell for $30 was most likely sold for $15-20 by Renesas.
BRN revenue should be $15-20 x 2-3% royalty = 30-60c per chip via Renesas. LDN a few years ago mentioned about $20 per chip.
Other suppliers of chips with BRN IP should have similar pricing.
Many products from all the big names with pricing at Mouser Electronics.
New products by manufacturer
New products by category
New products by week
The Renesas RA4 series sell for approx. $5 for volume.
The Renesas RA6 series sell for approx. $20 for volume.
The Renesas AI MPU chips with ARM Cortex-M55 sell for approx. $30 per chip.
The above are prices from Mouser electronics, a global distributor of semiconductors & electronics with over $4B in annual revenue.
Most likely Mouser Electronics will have at least 50-100% mark up so a chip they sell for $30 was most likely sold for $15-20 by Renesas.
BRN revenue should be $15-20 x 2-3% royalty = 30-60c per chip via Renesas. LDN a few years ago mentioned about $20 per chip.
Other suppliers of chips with BRN IP should have similar pricing.
Many products from all the big names with pricing at Mouser Electronics.
New products by manufacturer
New products by category
New products by week
It's all done with mirrors (or CNN)
[027] Memory 107 can be used to store, in computer code, artificial intelligence (“AI”) instructions, AI algorithms, a catalog of images, device configuration, an allowable, calculated, or predetermined user workflow, conditions for altering, device status, device and scanning configuration, and other metadata resulting from the scanning process. Memory 107 can be a read-only memory (“ROM”); a random-access memory (RAM) such as, for example, a magnetic disk drive, and/or solid-state RAM such as static RAM (“SRAM) or dynamic RAM (“DRAM), and/or FLASH memory or a solid-data disk (“SSD), or a magnetic, or any known type of memory. In some embodiments, a memory can be a combination of memories. For example, a memory can include a DRAM cache coupled to a magnetic disk drive and an SSD. Memory 107 can also include processor-readable media such as magnetic storage media such as hard disks, floppy disks, and magnetic tape; optical storage media such as Compact Disc/Digital Video Discs (“CD/DVDs), Compact Disc-Read Only Memories (“CD-ROMs), and holographic devices: magneto-optical storage media such as floptical disks; Solid state memory such as SSDs and FLASH memory; and ROM and RAM devices and chips.
D
Deleted member 118
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Getupthere
Regular
Amazing how only 3 years ago you could not find anything about brainchip on the web.
Now we are everywhere.
Our time has come BRN team!
Now we are everywhere.
Our time has come BRN team!
Falling Knife
Regular
This is akin to the bush fire detection I vaguely recal BRN ebing excited about some time ago
Might pay to tune in Fireside Chat
here are 2 chapter offered
for revuew and some wording that did peek interest but TBH to dry a read for my attention span to go the journey.
Happy reading
Might pay to tune in Fireside Chat
here are 2 chapter offered
for revuew and some wording that did peek interest but TBH to dry a read for my attention span to go the journey.
Happy reading
Steve10
Regular
Guess who owns Mouser Electronics?
Mouser Electronics is a worldwide leading authorized distributor of semiconductors and electronic components from over 1,200 manufacturer brands, with local sales and service centers located around the globe. We specialize in the rapid introduction of new products and technologies for design engineers and buyers. Our extensive product offering includes semiconductors, interconnects, passives, and electromechanical components.
In 2007, Mouser became a part of the Warren Buffett Berkshire Hathaway family of companies. Today, Buffett's holdings include insurance and finance subsidiaries and a host of almost fifty businesses ranging from jewelry and furniture to manufactured homes.
Mouser Electronics is a worldwide leading authorized distributor of semiconductors and electronic components from over 1,200 manufacturer brands, with local sales and service centers located around the globe. We specialize in the rapid introduction of new products and technologies for design engineers and buyers. Our extensive product offering includes semiconductors, interconnects, passives, and electromechanical components.
In 2007, Mouser became a part of the Warren Buffett Berkshire Hathaway family of companies. Today, Buffett's holdings include insurance and finance subsidiaries and a host of almost fifty businesses ranging from jewelry and furniture to manufactured homes.
Hii FF,
Yes, 404 describes some action in the custom logic 104.
Remember Simon Thorpe's presentation where the system recognized patterns in a field of seemingly pseudo random dots.
I think that Akida could probably dispense with all the pre-processing malarkey in Fig 3 if the model library had the images in the same form.
Custom logic 104 can include one or more Field Programmable Gate Array(s) (FPGA) or any type of PLD for custom logic to support processing offload from Processor 103. In an embodiment, the term “processing offload” includes digital signal processing and digital beam forming.
Several of their patents use the same set of drawings and much of the description is also repeated.
WO2021262379A1 SYSTEMS AND METHODS FOR NONINVASIVE DETECTION OF IMPERMISSIBLE OBJECTS US202063043779P·2020-06-25; US202117243563A·2021-04-28
has an earliest priority date of 25 June 2020.
There is no suggestion in the patents that SNN is used. There is nothing to suggest that, in June 2020, a person of ordinary skill in the technology would have understood a FPGA or PLD as encompassing a digital SNN.
D
Deleted member 2799
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Insane disclosures for a Sunday afternoon ladies and gentlemen! Thank you all for the informations!
Space Cadet
Regular
Does this mean anything to anyone? Dodgy Knees?
https://greenwaves-technologies.com/wp-content/uploads/2023/02/GAP9-Product-Brief-V1_14_non_NDA.pdf
SC
Fact Finder
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How ordinary is ordinary. Brainchip had released there IP in May, 2019 to select customers which likely included NASA and had an FPGA and published a paper using the FPGA and also had the live demo with Tata Consulting Services on 14.12.19.
Fact Finder
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GAP9 is a unique combination of a powerful low power microcontroller, a programmable compute cluster with a hardware neural network accelerator and sample by sample audio filtering unit.
This combination of homogeneous processing units with integrated hardware acceleration blocks achieves a perfect balance between ultra low power consumption and latency and flexibility and ease of use.
All the 10 cores in GAP9 are based on the RISC-V Instruction Set Architecture extended with custom instructions automatically used by the GAP toolchain. The compute cluster is perfectly adapted to handling combinations of neural network and digital signal processing tasks delivering programmable compute power at extreme energy efficiency.
The fact that they use RISC-V certainly does not diminish the chance that the hardware NN accelerator is Akida, but it would have been nice if they had mentioned SiFive.
"Select" customers would rule them out as being "ordinary". The onus is on the patentee to fully disclose the best method of implementing the invention. You cannot have "trade secrets" in a patent (from the latin "patio", ie, where everyone can see it).How ordinary is ordinary. Brainchip had released there IP in May, 2019 to select customers which likely included NASA and had an FPGA and published a paper using the FPGA and also had the live demo with Tata Consulting Services on 14.12.19.
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