BRN Discussion Ongoing

Diogenese

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I wonder if you could also add in a facial monitoring sensor that can also assist in the identification of the nervous nelly!

This has a so many spinoffs.

Pattern recognition and probably out comes can assist in many fields.

Let's hope the Ogar is gental.
We've been there before for school security - did not end happily.
 
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Hi FF,

Figure 4 is a flow chart, not a circuit diagram, so each step is shown in an individual box:

View attachment 32620

View attachment 32621


[048] Fig. 4 is a flow chart of a method for processing the existing data to create a final image. At 401, an optical image is created and mapped to the super image creating a filtered image. In an embodiment, the apparatus uses a separate camera to create an optical image used as a base image configured to be mapped to the super image, according to an embodiment. In an embodiment, the separate camera is a digital camera using a CCD sensor, or a CMOS sensor, or any practicable sensor.

Seems to be doing a lot of superfluous pre-fiddling with the sensor data.
So @Diogenese is the Ai Engine located at 104.
 
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Steve10

Regular
Renesas' new ARM Cortex-M85 AI chip should sell for more than $30 for volume.


1679209466103.png



The Renesas RA4 series sell for approx. $5 for volume.

The Renesas RA6 series sell for approx. $20 for volume.

The Renesas AI MPU chips with ARM Cortex-M55 sell for approx. $30 per chip.

The above are prices from Mouser electronics, a global distributor of semiconductors & electronics with over $4B in annual revenue.

Most likely Mouser Electronics will have at least 50-100% mark up so a chip they sell for $30 was most likely sold for $15-20 by Renesas.

BRN revenue should be $15-20 x 2-3% royalty = 30-60c per chip via Renesas. LDN a few years ago mentioned about $20 per chip.

Other suppliers of chips with BRN IP should have similar pricing.

Many products from all the big names with pricing at Mouser Electronics.

New products by manufacturer

New products by category

New products by week
 
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Diogenese

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So @Diogenese is the Ai Engine located at 104.
It's all done with mirrors (or CNN)

[027] Memory 107 can be used to store, in computer code, artificial intelligence (“AI”) instructions, AI algorithms, a catalog of images, device configuration, an allowable, calculated, or predetermined user workflow, conditions for altering, device status, device and scanning configuration, and other metadata resulting from the scanning process. Memory 107 can be a read-only memory (“ROM”); a random-access memory (RAM) such as, for example, a magnetic disk drive, and/or solid-state RAM such as static RAM (“SRAM) or dynamic RAM (“DRAM), and/or FLASH memory or a solid-data disk (“SSD), or a magnetic, or any known type of memory. In some embodiments, a memory can be a combination of memories. For example, a memory can include a DRAM cache coupled to a magnetic disk drive and an SSD. Memory 107 can also include processor-readable media such as magnetic storage media such as hard disks, floppy disks, and magnetic tape; optical storage media such as Compact Disc/Digital Video Discs (“CD/DVDs), Compact Disc-Read Only Memories (“CD-ROMs), and holographic devices: magneto-optical storage media such as floptical disks; Solid state memory such as SSDs and FLASH memory; and ROM and RAM devices and chips.
 
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D

Deleted member 118

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Renesas' new ARM Cortex-M85 AI chip should sell for more than $30 for volume.


View attachment 32617


The Renesas RA4 series sell for approx. $5 for volume.

The Renesas RA6 series sell for approx. $20 for volume.

The Renesas AI MPU chips with ARM Cortex-M55 sell for approx. $30 per chip.

The above are prices from Mouser electronics, a global distributor of semiconductors & electronics with over $4B in annual revenue.

Most likely Mouser Electronics will have at least 50-100% mark up so a chip they sell for $30 was most likely sold for $15-20 by Renesas.

BRN revenue should be $15-20 x 2-3% royalty = 30-60c per chip via Renesas. LDN a few years ago mentioned about $20 per chip.

Other suppliers of chips with BRN IP should have similar pricing.

Many products from all the big names with pricing at Mouser Electronics.

New products by manufacturer

New products by category

New products by week
 
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Getupthere

Regular
Amazing how only 3 years ago you could not find anything about brainchip on the web.

Now we are everywhere.

Our time has come BRN team!
 
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This is akin to the bush fire detection I vaguely recal BRN ebing excited about some time ago

1679212597326.png


Might pay to tune in Fireside Chat


here are 2 chapter offered


for revuew and some wording that did peek interest but TBH to dry a read for my attention span to go the journey.
1679214074934.png


1679214087809.png

1679214096553.png

1679214102359.png

Happy reading
 
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Steve10

Regular
Guess who owns Mouser Electronics?

Mouser Electronics is a worldwide leading authorized distributor of semiconductors and electronic components from over 1,200 manufacturer brands, with local sales and service centers located around the globe. We specialize in the rapid introduction of new products and technologies for design engineers and buyers. Our extensive product offering includes semiconductors, interconnects, passives, and electromechanical components.

In 2007, Mouser became a part of the Warren Buffett Berkshire Hathaway family of companies. Today, Buffett's holdings include insurance and finance subsidiaries and a host of almost fifty businesses ranging from jewelry and furniture to manufactured homes.
 
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Diogenese

Top 20
So @Diogenese is the Ai Engine located at 104.

It's all done with mirrors (or CNN)

[027] Memory 107 can be used to store, in computer code, artificial intelligence (“AI”) instructions, AI algorithms, a catalog of images, device configuration, an allowable, calculated, or predetermined user workflow, conditions for altering, device status, device and scanning configuration, and other metadata resulting from the scanning process. Memory 107 can be a read-only memory (“ROM”); a random-access memory (RAM) such as, for example, a magnetic disk drive, and/or solid-state RAM such as static RAM (“SRAM) or dynamic RAM (“DRAM), and/or FLASH memory or a solid-data disk (“SSD), or a magnetic, or any known type of memory. In some embodiments, a memory can be a combination of memories. For example, a memory can include a DRAM cache coupled to a magnetic disk drive and an SSD. Memory 107 can also include processor-readable media such as magnetic storage media such as hard

disks, floppy disks, and magnetic tape; optical storage media such as Compact Disc/Digital Video Discs (“CD/DVDs), Compact Disc-Read Only Memories (“CD-ROMs), and holographic devices: magneto-optical storage media such as floptical disks; Solid state memory such as SSDs and FLASH memory; and ROM and RAM devices and chips
.

Hii FF,

Yes, 404 describes some action in the custom logic 104.

Remember Simon Thorpe's presentation where the system recognized patterns in a field of seemingly pseudo random dots.

I think that Akida could probably dispense with all the pre-processing malarkey in Fig 3 if the model library had the images in the same form.

Custom logic 104 can include one or more Field Programmable Gate Array(s) (FPGA) or any type of PLD for custom logic to support processing offload from Processor 103. In an embodiment, the term “processing offload” includes digital signal processing and digital beam forming.

Several of their patents use the same set of drawings and much of the description is also repeated.

WO2021262379A1 SYSTEMS AND METHODS FOR NONINVASIVE DETECTION OF IMPERMISSIBLE OBJECTS US202063043779P·2020-06-25; US202117243563A·2021-04-28

has an earliest priority date of 25 June 2020.

There is no suggestion in the patents that SNN is used. There is nothing to suggest that, in June 2020, a person of ordinary skill in the technology would have understood a FPGA or PLD as encompassing a digital SNN.
 
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Deleted member 2799

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Insane disclosures for a Sunday afternoon ladies and gentlemen! Thank you all for the informations!
 
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Hii FF,

Yes, 404 describes some action in the custom logic 104.

Remember Simon Thorpe's presentation where the system recognized patterns in a field of seemingly pseudo random dots.

I think that Akida could probably dispense with all the pre-processing malarkey in Fig 3 if the model library had the images in the same form.

Custom logic 104 can include one or more Field Programmable Gate Array(s) (FPGA) or any type of PLD for custom logic to support processing offload from Processor 103. In an embodiment, the term “processing offload” includes digital signal processing and digital beam forming.

Several of their patents use the same set of drawings and much of the description is also repeated.

WO2021262379A1 SYSTEMS AND METHODS FOR NONINVASIVE DETECTION OF IMPERMISSIBLE OBJECTS US202063043779P·2020-06-25; US202117243563A·2021-04-28

has an earliest priority date of 25 June 2020.

There is no suggestion in the patents that SNN is used. There is nothing to suggest that, in June 2020, a person of ordinary skill in the technology would have understood a FPGA or PLD as encompassing a digital SNN.
How ordinary is ordinary. Brainchip had released there IP in May, 2019 to select customers which likely included NASA and had an FPGA and published a paper using the FPGA and also had the live demo with Tata Consulting Services on 14.12.19. 😎
 
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Hi Proga,

In my opinion, the balance of probabilities is that Greenwaves do not use Akida.

The GAP9 has a shared memory.

It also has parallel architecture for software AI.

The only glimmer of hope is the cooperative AI accelerator (NE16), but the blurb states that "all 10 cores ... are based on the RISC-V Instruction Set Architecture".

I don't see that you would use software AI if you had Akida.

https://greenwaves-technologies.com.../Product-Brief-GAP9-Sensors-General-V1_14.pdf
View attachment 23295


GAP9 is a unique combination of a powerful low power microcontroller, a programmable compute cluster with a hardware neural network accelerator and sample by sample audio filtering unit.


All the 10 cores in GAP9 are based on the RISC-V Instruction Set Architecture extended with custom instructions automatically used by the GAP toolchain. The compute cluster is perfectly adapted to handling combinations of neural network and digital signal processing tasks delivering programmable compute power at extreme energy efficiency.
This is what @Diogenese said last year about Greenwaves.😎
 
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Diogenese

Top 20


1679216138444.png


GAP9 is a unique combination of a powerful low power microcontroller, a programmable compute cluster with a hardware neural network accelerator and sample by sample audio filtering unit.
This combination of homogeneous processing units with integrated hardware acceleration blocks achieves a perfect balance between ultra low power consumption and latency and flexibility and ease of use.
All the 10 cores in GAP9 are based on the RISC-V Instruction Set Architecture extended with custom instructions automatically used by the GAP toolchain. The compute cluster is perfectly adapted to handling combinations of neural network and digital signal processing tasks delivering programmable compute power at extreme energy efficiency
.

The fact that they use RISC-V certainly does not diminish the chance that the hardware NN accelerator is Akida, but it would have been nice if they had mentioned SiFive.
How ordinary is ordinary. Brainchip had released there IP in May, 2019 to select customers which likely included NASA and had an FPGA and published a paper using the FPGA and also had the live demo with Tata Consulting Services on 14.12.19. 😎
"Select" customers would rule them out as being "ordinary". The onus is on the patentee to fully disclose the best method of implementing the invention. You cannot have "trade secrets" in a patent (from the latin "patio", ie, where everyone can see it).
 
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Words from the CTO of Accenture (although there is a disclaimer they are his opinion and not Accentures).

1679218075176.png



 
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View attachment 32628

GAP9 is a unique combination of a powerful low power microcontroller, a programmable compute cluster with a hardware neural network accelerator and sample by sample audio filtering unit.
This combination of homogeneous processing units with integrated hardware acceleration blocks achieves a perfect balance between ultra low power consumption and latency and flexibility and ease of use.
All the 10 cores in GAP9 are based on the RISC-V Instruction Set Architecture extended with custom instructions automatically used by the GAP toolchain. The compute cluster is perfectly adapted to handling combinations of neural network and digital signal processing tasks delivering programmable compute power at extreme energy efficiency
.

The fact that they use RISC-V certainly does not diminish the chance that the hardware NN accelerator is Akida, but it would have been nice if they had mentioned SiFive.

"Select" customers would rule them out as being "ordinary". The onus is on the patentee to fully disclose the best method of implementing the invention. You cannot have "trade secrets" in a patent (from the latin "patio", ie, where everyone can see it).
So what do you call a patio with a privacy fence.😂🤡🤣
 
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TasTroy77

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Anyone up for knitting an AKIDA powered jumper for me for Christmas.

The following paper is another of those industries that do not yet exist AKIDA powered textiles:

“V. NEUROMORPHIC COMPUTING PROPERTIES
Neuromorphic computing concept originated in the 1980’s. Taking inspiration from computer science, mathematics to bio-inspired models of neural network. This emerging inter- disciplinary research field has the potential to disrupt tradi- tional computing methods and architectural implementations leading to a more centralized and combined memory and computational driven approach, moving away from the von Neumann architectural approach with separate memory and computing capabilities and high compute power needs. Such inspiration coming from the working of the human brain paves the way for new and more fault tolerant layered and parallel architectural designs and layouts.
FIGURE 7. Timeline of technological advancements in Neuromorphic Computing
In order to understand what aspects of neuromorphic computing can inspire innovative advancements in the next generation of smart etextiles and on-garment edge based intelligence, we will first highlight the core key architectural elements of importance within neuromorphic computing and assess their potential within an etextiles domain. Neuromor- phic computing core architecture is based on the concept of communicating through event driven spikes generated through simple processing structures represented by synapses and neurons. Ongoing research is pushing the production possibilities using complementary metal oxide semiconduc- tor (CMOS) technology to develop neuromorphic spiking neural network hardware implementations [45][46][47]. Key properties such as size, weight, low power consumption, and modular design (scalability) are dominating the research areas of focus linked to such technologies. Over the years advancements in CMOS technology has driven smaller and more power efficient systems with the capability to mass produce. Such technology combined with advanced machine learning techniques has directly lead to the simulation and implementation of silicon based neurons, otherwise defined as neuromorphic computing.
[Fig 7] highlights advancements, with Brainchip (https://brainchip.com/) announcement in 2022 claiming to be the worlds first commercial producer of a Neuromorphic AI processor ‘Akida’ that has the capability to mimic the working of the human brain and process data with high precision and energy efficiency. Akida being an event-based AI neural processor featuring 1.2 million neurons and 10 billion synapse.”


My opinion only DYOR
FF

AKIDA BALLISTA

PS: Navy blue, crew neck, Cable knitt to go with jeans. Thanks.
 
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Diogenese

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Jchandel

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