BRN Discussion Ongoing

Looking forward to hearing something solid in brn favour.
 
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manny100

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From a recent video interview with Steve Brighfield.
"The primary difference between brain chip and the Intel and the IBM solutions was they were analog. So they truly tried to match the analog waveforms of the brain, whereas the brain chip made a digital equivalent of the analog waveform. So now you could easily manufacture a computer, digital computer chip using the approach. The chips that you, the analog chips that are made today for neuromorphics, they're notorious for, you know, you have to have them biased and temperature stabilized, and there's all the problems with analog, which is the reason we don't have a lot of analog computers today, or the problems that they're faced with their neuromorphic chips."
"There are other companies that are producing analog Neuromorphic chips, but they're kind of dedicated for a specific market second, like speech wake-up, right? Or a biological wake-up. So they're like function-specific Neuromorphic chips. We have a very digital programmable chip that can use any kind of sensor, so we're kind of unique in that aspect. Build the future of multi-agent software with agency. "
My bold above.
 
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manny100

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Another quote from Steve Brightfield.
"I think we're trying to ride the neuromorphic computing and brain chip in particular is trying to ride the coattails of the overall market moving to the edge. And when we look at market research reports from companies, they're saying about 10% of these edge products embedded devices are running some AI software on them. But within the next four years, four to five years, 30 to 35% of those products will have AI on. And I think if we look out, the next five years, 90% of them will have it all embedded in it. And there will be a neuromorphic computing in probably half of those devices. Because it's going to be more generally available. "
 
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Guzzi62

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From a recent video interview with Steve Brighfield.
"The primary difference between brain chip and the Intel and the IBM solutions was they were analog. So they truly tried to match the analog waveforms of the brain, whereas the brain chip made a digital equivalent of the analog waveform. So now you could easily manufacture a computer, digital computer chip using the approach. The chips that you, the analog chips that are made today for neuromorphics, they're notorious for, you know, you have to have them biased and temperature stabilized, and there's all the problems with analog, which is the reason we don't have a lot of analog computers today, or the problems that they're faced with their neuromorphic chips."
"There are other companies that are producing analog Neuromorphic chips, but they're kind of dedicated for a specific market second, like speech wake-up, right? Or a biological wake-up. So they're like function-specific Neuromorphic chips. We have a very digital programmable chip that can use any kind of sensor, so we're kind of unique in that aspect. Build the future of multi-agent software with agency. "
My bold above.
Sadly, Steve got that wrong!

Intel's Loihi 2 is fully digital.


 
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manny100

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perceptron

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So to clarify one last time, I am not asking what it costs BrainChip to manufacture the chips, nor am I asking for a margin analysis.

I am pointing out that we cannot determine the revenue from these orders because the announcement states customers will be charged anywhere between $4 and $50 per chip, depending on volume.

What the announcement does not disclose however, is where on that sliding scale these orders actually sit.

Specifically, 1) what volume qualifies as a high volume order 2) at what quantity does pricing move from $50 to $10 to $4? 3) where does an order of 10,000 units or 1,200 units fall on that curve?

Without that information, revenue could be materially different under perfectly reasonable interpretations.

To illustrate by way of demonstration only:
  • If BrainChip considers anything above 5,000 units to be a volume order, then 11,200 units could be priced at $4, generating roughly $45k in revenue.
  • If instead “volume” means anything exceeding 50,000 units, then the same 11,200 units could be priced far higher — say $20–$30 per chip, resulting in $224k–$336k of revenue.

My point is that until the company clarifies how the volume pricing tiers actually work, any attempt to calculate revenue from these orders is pure guesswork.
Appreciate your reply Bravo. So the foundry is only charging it's customer's the variable costs associated to produce any number of chips while excluding their fixed costs such capital expenditure, taxes, salaries and the many other costs that remain constant for any given amount of chips ordered.
 

Diogenese

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From a recent video interview with Steve Brighfield.
"The primary difference between brain chip and the Intel and the IBM solutions was they were analog. So they truly tried to match the analog waveforms of the brain, whereas the brain chip made a digital equivalent of the analog waveform. So now you could easily manufacture a computer, digital computer chip using the approach. The chips that you, the analog chips that are made today for neuromorphics, they're notorious for, you know, you have to have them biased and temperature stabilized, and there's all the problems with analog, which is the reason we don't have a lot of analog computers today, or the problems that they're faced with their neuromorphic chips."
"There are other companies that are producing analog Neuromorphic chips, but they're kind of dedicated for a specific market second, like speech wake-up, right? Or a biological wake-up. So they're like function-specific Neuromorphic chips. We have a very digital programmable chip that can use any kind of sensor, so we're kind of unique in that aspect. Build the future of multi-agent software with agency. "
My bold above.
Hi manny,

I'd like your thoughts/corrections to the following.

Tony Lewis mentioned that Akida 3 and GenAI will have a flexible hardware switched communication mesh whereas Akida 1 & 2 have a packet switched type comms mesh, and I'm trying to understand the advantages of the H/W switch.

The packet switched version requires that each event/spike includes an address header to direct it to the destination neuron. This entails transmitting additional bits with each event. increasing latency and power usage.

Thus for a many-to-many neuron connexion, there must be a transistor switch matrix (~ a crossbar switch?). But this only requires one switch per destination neuron compared with a requirement for the header to include the address of each destination neuron. For example, if there were 256 possible destination neurons, then the header would need to include 8 bits per destination neuron. So for 8 destination neurons for example, that would be 64 additional bits (ignoring any protocol overhead). (There may well be a more efficient protocol for this it, but that is above my pay grade).

In contrast, for a hardware switching matrix, only one transistor needs to switch per destination neuron, so, in the above example, that would be 8 switch operations.

In addition, the packet switched mesh protocol needs a larger collision avoidance buffer, to ensure only 1 event is transmitted at a time.

Obviously, the H/W switch will still require additional power/time to set up the switch connexions, but I assume this is a one off for each task.
 
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Diogenese

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manny100

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Hi manny,

I'd like your thoughts/corrections to the following.

Tony Lewis mentioned that Akida 3 and GenAI will have a flexible hardware switched communication mesh whereas Akida 1 & 2 have a packet switched type comms mesh, and I'm trying to understand the advantages of the H/W switch.

The packet switched version requires that each event/spike includes an address header to direct it to the destination neuron. This entails transmitting additional bits with each event. increasing latency and power usage.

Thus for a many-to-many neuron connexion, there must be a transistor switch matrix (~ a crossbar switch?). But this only requires one switch per destination neuron compared with a requirement for the header to include the address of each destination neuron. For example, if there were 256 possible destination neurons, then the header would need to include 8 bits per destination neuron. So for 8 destination neurons for example, that would be 64 additional bits (ignoring any protocol overhead). (There may well be a more efficient protocol for this it, but that is above my pay grade).

In contrast, for a hardware switching matrix, only one transistor needs to switch per destination neuron, so, in the above example, that would be 8 switch operations.

In addition, the packet switched mesh protocol needs a larger collision avoidance buffer, to ensure only 1 event is transmitted at a time.

Obviously, the H/W switch will still require additional power/time to set up the switch connexions, but I assume this is a one off for each task.
Hi Dio, its above my paygrade but Gen 3 is an upgrade so it has to be an improvement.
Appears ditching the packets will likely improve latency and reduce power costs. It would be designed to work well/better with GenAI.
Basically a guess based on why do it if it's not better and they are key areas.
 
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