BRN Discussion Ongoing

[JB49]

Innovative robot navigation inspired by brain function boosts efficiency and accuracy

A QUT research team has taken inspiration from the brains of insects and animals for more energy-efficient robotic navigation.

www.qut.edu.au

They used Intel unfortunately, but still thought I'd share. Would be nice if an Australian Uni would support an Australian company instead!!

 

[Diogenese]

These things obviously take time to develop. A lot longer than any of us anticipated.
Here is the original SBIR award for N202-099.
May 6 2020
Mentions IBM and Intel. No mention of BrainChip at this point.
Interesting little spiel highlighted below. I wonder if this research / work ended up with having anything to do with the Perth office getting closed down and certain people retiring or removing themselves from BrainChip. ?



Implementing Neural Network Algorithms on Neuromorphic Processors

Navy SBIR 20.2 - Topic N202-099

Naval Air Systems Command (NAVAIR) - Ms. Donna Attick navairsbir@navy.mil

Opens: June 3, 2020 - Closes: July 2, 2020 (12:00 pm ET)





N202-099 TITLE: Implementing Neural Network Algorithms on Neuromorphic Processors



RT&L FOCUS AREA(S): Artificial Intelligence/ Machine Learning, General Warfighting Requirements (GWR)

TECHNOLOGY AREA(S): Air Platform



OBJECTIVE: Deploy Deep Neural Network algorithms on near-commercially available Neuromorphic or equivalent Spiking Neural Network processing hardware.



DESCRIPTION: Biological inspired Neural Networks provide the basis for modern signal processing and classification algorithms. Implementation of these algorithms on conventional computing hardware requires significant compromises in efficiency and latency due to fundamental design differences. A new class of hardware is emerging that more closely resembles the biological Neuron/Synapse model found in Nature and may solve some of these limitations and bottlenecks. Recent work has demonstrated significant performance gains using these new hardware architectures and have shown equivalence to converge on a solution with the same accuracy [Ref 1].



The most promising of the new class are based on Spiking Neural Networks (SNN) and analog Processing in Memory (PiM), where information is spatially and temporally encoded onto the network. A simple spiking network can reproduce the complex behavior found in the Neural Cortex with significant reduction in complexity and power requirements [Ref 2]. Fundamentally, there should be no difference between algorithms based on Neural Network and current processing hardware. In fact, the algorithms can easily be transferred between hardware architectures [Ref 4]. The performance gains, application of neural networks and the relative ease of transitioning current algorithms over to the new hardware motivates the consideration of this topic.�

�

Hardware based on Spiking Neural Networks (SNN) are currently under development at various stages of maturity. Two prominent examples are the IBM True North and the INTEL Loihi Chips, respectively. The IBM approach uses conventional CMOS technology and the INTEL approach uses a less mature memrisistor architecture. Estimated efficiency performance increase is greater than 3 orders of magnitude better than state of the art Graphic Processing Unit (GPUs) or Field-programmable gate array (FPGAs). More advanced architectures based on an all-optical or photonic based SNN show even more promise. Nano-Photonic based systems are estimated to achieve 6 orders of magnitude increase in efficiency and computational density; approaching the performance of a Human Neural Cortex. The primary goal of this effort is to deploy Deep Neural Network algorithms on near-commercially available Neuromorphic or equivalent Spiking Neural Network processing hardware. Benchmark the performance gains and validate the suitability to warfighter application.



Work produced in Phase II may become classified. Note: The prospective contractor(s) must be U.S. owned and operated with no foreign influence as defined by DoD 5220.22-M, National Industrial Security Program Operating Manual, unless acceptable mitigating procedures can and have been implemented and approved by the Defense Counterintelligence and Security Agency (DCSA). The selected contractor and/or subcontractor must be able to acquire and maintain a secret level facility and Personnel Security Clearances. This will allow contractor personnel to perform on advanced phases of this project as set forth by DCSA and NAVAIR in order to gain access to classified information pertaining to the national defense of the United States and its allies; this will be an inherent requirement. The selected company will be required to safeguard classified material IAW DoD 5220.22-M during the advanced phases of this contract.



PHASE I: Develop an approach for deploying Neural Network algorithms and identify suitable hardware, learning algorithm framework and benchmark testing and validation methodology plan. Demonstrate performance enhancements and integration of technology as described in the description above. The Phase I effort will include plans to be developed under Phase II.



PHASE II: Transfer government furnished algorithms and training data running on a desktop computing environment to the new hardware environment. An example algorithm development frame for this work would be TensorFlow. Some modification of the framework and/or algorithms may be required to facilitate transfer. Some optimization will be required and is expected to maximize the performance of the algorithms on the new hardware. This optimization should focus on throughput, latency, and power draw/dissipation. Benchmark testing should be conducted against these metrics. Develop a transition plan for Phase III.



It is probable that the work under this effort will be classified under Phase II (see Description section for details).



PHASE III DUAL USE APPLICATIONS: Optimize algorithm and conduct benchmark testing. Adjust algorithms as needed and transition to final hardware environment. Successful technology development could benefit industries that conduct data mining and high-end processing, computer modeling and machine learning such as manufacturing, automotive, and aerospace industries.



REFERENCES:

1. Ambrogio, S., Narayanan, P., Tsai, H., Shelby, R., Boybat, I., Nolfo, C., . . . Burr, G. �Equivalent-Accuracy Accelerated Neural-Network Training Using Analogue Memory.� Nature, June 6, 2018, pp. 60-67. https://www.nature.com/articles/s41586-018-0180-5



2. Izhikevich, E. �Simple Model of Spiking Neurons.� IEEE Transactions on Neural Networks, 2003, pp. 1569-1572. https://ieeexplore.ieee.org/document/1257420



3. Diehl, P., Zarrella, G., Cassidy, A., Pedroni, B. & Neftci, E. �Conversion of Artificial Recurrent Neural Networks to Spiking Neural Networks for Low-Power Neuromorphic Hardware.� Cornell University, 2016. https://arxiv.org/abs/1601.04187



4. Esser, S., Merolla, P., Arthur, J., Cassidy, A., Appuswamy, R., Andreopoulos, A., . . . Modha, D. �Convolutional Networks for Fast, Energy-Efficient Neuromorphic Computing.� IBM Research: Almaden, May 24, 2016. https://arxiv.org/pdf/1603.08270.pdf



5. Department of Defense. National Defense Strategy 2018. United States Congress. https://dod.defense.gov/Portals/1/Documents/pubs/2018-National-Defense-Strategy-Summary.pdf



KEYWORDS: Neural Networks, Neuromorphic, Processor, Algorithm, Spiking Neurons, Machine Learning



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​

** TOPIC NOTICE **​

The Navy Topic above is an "unofficial" copy from the overall DoD 20.2 SBIR BAA. Please see the official DoD DSIP Topic website at rt.cto.mil/rtl-small-business-resources/sbir-sttr/ for any updates. The DoD issued its 20.2 SBIR BAA on May 6, 2020, which opens to receive proposals on June 3, 2020, and closes July 2, 2020 at 12:00 noon ET. Direct Contact with Topic Authors. During the pre-release period (May 6 to June 2, 2020) proposing firms have an opportunity to directly contact the Technical Point of Contact (TPOC) to ask technical questions about the specific BAA topic. Questions should be limited to specific information related to improving the understanding of a particular topic�s requirements. Proposing firms may not ask for advice or guidance on solution approach and you may not submit additional material to the topic author. If information provided during an exchange with the topic author is deemed necessary for proposal preparation, that information will be made available to all parties through SITIS (SBIR/STTR Interactive Topic Information System). After the pre-release period, questions must be asked through the SITIS on-line system as described below. SITIS Q&A System. Once DoD begins accepting proposals on June 3, 2020 no further direct contact between proposers and topic authors is allowed unless the Topic Author is responding to a question submitted during the Pre-release period. However, proposers may submit written questions through SITIS at www.dodsbirsttr.mil/submissions/login, login and follow instructions. In SITIS, the questioner and respondent remain anonymous but all questions and answers are posted for general viewing. Topics Search Engine: Visit the DoD Topic Search Tool at www.dodsbirsttr.mil/topics-app/ to find topics by keyword across all DoD Components participating in this BAA. Help: If you have general questions about DoD SBIR program, please contact the DoD SBIR Help Desk at 703-214-1333 or via email at DoDSBIRSupport@reisystems.com

Hi Taproot,

The bit about optical/photonic SNNs squares the circle with our friends Bascom Hunter who have been working on this tech for 15 years.

Hardware based on Spiking Neural Networks (SNN) are currently under development at various stages of maturity. Two prominent examples are the IBM True North and the INTEL Loihi Chips, respectively. The IBM approach uses conventional CMOS technology and the INTEL approach uses a less mature memrisistor architecture. Estimated efficiency performance increase is greater than 3 orders of magnitude better than state of the art Graphic Processing Unit (GPUs) or Field-programmable gate array (FPGAs). More advanced architectures based on an all-optical or photonic based SNN show even more promise. Nano-Photonic based systems are estimated to achieve 6 orders of magnitude increase in efficiency and computational density; approaching the performance of a Human Neural Cortex. The primary goal of this effort is to deploy Deep Neural Network algorithms on near-commercially available Neuromorphic or equivalent Spiking Neural Network processing hardware. Benchmark the performance gains and validate the suitability to warfighter application.

What I find significant is they they have gone with processor board with 5 Akida 1000s.

The problem is that, after Phase I, the security gets more and more restrictive = NDA to the power of CIA/National Security Council so:-


https://au.video.search.yahoo.com/s...=251d01e90e59e62f4b44a6ab7e455acd&action=view

 

[JB49]

Loading…

airdrive.eventsair.com

31st International Conference on Neural Information Processing

Appears to be a lot of spiking neural networks. Specifically relating to biomedical application, emotion analysis and earthquake prediction. Nothing specific on Brainchip from what I could see.

 

[Taproot]

Phase 2.
End date = 18/08/2025

Implementing Neural Network Algorithms on Neuromorphic Processors | SBIR.gov

legacy.www.sbir.gov

This bloke founded BH 2010
Paul Prucnal

Paul R. Prucnal (born 1953) is an American electrical engineer. He is a professor of electrical engineering at Princeton University. He is best known for his seminal work in Neuromorphic Photonics,[1] optical code division multiple access (OCDMA) and the invention of the terahertz optical asymmetric demultiplexor (TOAD).[2] He is currently a fellow of IEEE for contributions to photonic switching and fiber-optic networks,[3] Optical Society of America and National Academy of Inventors.[4][5][6]

Life and career​

[edit]
Prucnal received his A.B. In mathematics and physics from Bowdoin College in 1974, graduating summa cum laud, where he also studied piano with William Eves, a pupil of Robert Casadesus. He then earned M.S., M.Phil. and Ph. D. degrees in electrical engineering from Columbia University in 1976, 1978 and 1979, respectively,[4] where he did his doctoral work with Malvin Carl Teich.[7] After his doctorate, Prucnal joined the faculty at Columbia University in 1979. As a member of the Columbia Radiation Laboratory, he performed groundbreaking work in OCDMA[8] and self-routed photonic switching. In 1988, he joined the faculty at Princeton University.

His developmental research on optical CDMA initiated a new research field[9] in which more than 1000 papers have since been published, exploring applications ranging from information security[10] to communication speed and bandwidth.[11] In 1993, he invented the "Terahertz Optical Asymmetric Demultiplexer,"[12][13] the first optical switch capable of processing terabit per second (Tb/s) pulse trains.[14][15] With support from DARPA in the 1990s, his group was the first to demonstrate an all-optical 100 gigabit/sec photonic packet switching node and optical multiprocessor interconnect.[16]

Prucnal is author of the book, Neuromorphic Photonics,[1] and editor of the book, Optical Code Division Multiple Access: Fundamentals and Applications.[17] He was an Area Editor of IEEE Transactions on Communications. He has authored or co-authored more than 350 journal articles and book chapters and holds 28 U.S. patents. He is a fellow of the Institute of Electrical and Electronics Engineers (IEEE), the Optical Society of America (OSA) and the National Academy of Inventors (NAI), and a member of honor societies including Phi Beta Kappa and Sigma Xi. He was the recipient of the 1990 Rudolf Kingslake Medal[18] for his paper entitled "Self-routing photonic switching with optically-processed control" and has won multiple teaching awards at Princeton.[4]

He has been instrumental in founding the field of Neuromorphic Photonics[1] and developing the "photonic neuron", a high speed optical computing device modeled on neural networks,[19] as well as integrated optical circuits to improve wireless signal quality by cancelling radio interference. [20][21]

 

[Taproot]

Hi Taproot,

The bit about optical/photonic SNNs squares the circle with our friends Bascom Hunter who have been working on this tech for 15 years.

Hardware based on Spiking Neural Networks (SNN) are currently under development at various stages of maturity. Two prominent examples are the IBM True North and the INTEL Loihi Chips, respectively. The IBM approach uses conventional CMOS technology and the INTEL approach uses a less mature memrisistor architecture. Estimated efficiency performance increase is greater than 3 orders of magnitude better than state of the art Graphic Processing Unit (GPUs) or Field-programmable gate array (FPGAs). More advanced architectures based on an all-optical or photonic based SNN show even more promise. Nano-Photonic based systems are estimated to achieve 6 orders of magnitude increase in efficiency and computational density; approaching the performance of a Human Neural Cortex. The primary goal of this effort is to deploy Deep Neural Network algorithms on near-commercially available Neuromorphic or equivalent Spiking Neural Network processing hardware. Benchmark the performance gains and validate the suitability to warfighter application.

What I find significant is they they have gone with processor board with 5 Akida 1000s.

The problem is that, after Phase I, the security gets more and more restrictive = NDA to the power of CIA/National Security Council so:-


https://au.video.search.yahoo.com/s...=251d01e90e59e62f4b44a6ab7e455acd&action=view

Yep, add them to the Secret Squirrel Club.

The phrase "Secret Squirrel stuff" is used by people working in U.S. intelligence to lightheartedly describe material that is highly classified, usually as a non-answer to a question.

At least we know now, a previously unknown known.
Exciting stuff and a much needed shot in the arm.

 

[ndefries]

Too true....Ant61.

Shame they lost contact before they could prove up Akida....at least it wasn't an Akida issue.

It does mean aliens can steal akida now without an IP licence.

 

[Fullmoonfever]

It does mean aliens can steal akida now without an IP licence.

Yes that's a point ...but then they have to reverse engineer it first

 

[Diogenese]

Yes that's a point ...but then they have to reverse engineer it first

Akida can reverse engineer itself!

 

[DingoBorat]

Whilst we'd all like to see additional IP licences etc, I take some positives that there are now at least 3 companies we know of that have done the groundwork, development etc and passed the POC stage to offer end products.

That does reveal some progress imo.

Like any business, they obviously need to go to mkt and see what traction they get and if demand / contracts are there, then ramp up for production which I suspect would see supply of Akida through someone like MegaChips or maybe a direct licence with BRN at that point.

That is what I am envisioning anyway.

The 3 products are in 3 different mkts as well which is good.

Bascom Hunter Snap Card

VVDN Edge Box

Quantum Ventura CyberNeuro-RT

Hey this Bascom Hunter Snap card is news to me..
When did we find out about that?

With 5 AKIDA 1000 chips per unit, a production run is surely on the cards at some point?

There can't be "that" many of them floating around, with them also going into the VVDN Edge boxes (at 2 a piece)..

 

[manny100]

Hi Taproot,

The bit about optical/photonic SNNs squares the circle with our friends Bascom Hunter who have been working on this tech for 15 years.

Hardware based on Spiking Neural Networks (SNN) are currently under development at various stages of maturity. Two prominent examples are the IBM True North and the INTEL Loihi Chips, respectively. The IBM approach uses conventional CMOS technology and the INTEL approach uses a less mature memrisistor architecture. Estimated efficiency performance increase is greater than 3 orders of magnitude better than state of the art Graphic Processing Unit (GPUs) or Field-programmable gate array (FPGAs). More advanced architectures based on an all-optical or photonic based SNN show even more promise. Nano-Photonic based systems are estimated to achieve 6 orders of magnitude increase in efficiency and computational density; approaching the performance of a Human Neural Cortex. The primary goal of this effort is to deploy Deep Neural Network algorithms on near-commercially available Neuromorphic or equivalent Spiking Neural Network processing hardware. Benchmark the performance gains and validate the suitability to warfighter application.

What I find significant is they they have gone with processor board with 5 Akida 1000s.

The problem is that, after Phase I, the security gets more and more restrictive = NDA to the power of CIA/National Security Council so:-


https://au.video.search.yahoo.com/s...=251d01e90e59e62f4b44a6ab7e455acd&action=view

There is a poster on the crapper peddling that a DOD contract would preclude BRN from other non defence contracts due to secrecy etc..
That is why they are calling it the crapper.

 

[Guzzi62]

Hey this Bascom Hunter Snap card is news to me..
When did we find out about that?

With 5 AKIDA 1000 chips per unit, a production run is surely on the cards at some point?

There can't be "that" many of them floating around, with them also going into the VVDN Edge boxes (at 2 a piece)..

I think it's a low volume card for limited purpose, hardened and all, so likely not cheap as well.

The most important is IMO that they choose the chip in the first place.

 

[Taproot]

Is this current brochure? I can’t find it on their website. Can you post the link please.

ASIC Solutions

ASICs are exceptionally well-suited for machine learning tasks that require a lot of computational power, such as deep learning and neural network training.

bascomhunter.com

 

[Fullmoonfever]

Hey this Bascom Hunter Snap card is news to me..
When did we find out about that?

With 5 AKIDA 1000 chips per unit, a production run is surely on the cards at some point?

There can't be "that" many of them floating around, with them also going into the VVDN Edge boxes (at 2 a piece)..

Hey DB

@FuzM discovered and kindly posted it yesterday.

We all just went dot joining off the back of that

Though, I think it was maybe @Taproot who highlighted that @uiux was also all over BH early on looking for links.

BRN Discussion Ongoing

I am not looking for the moon but just something positive on the back of multiple comments from the company. Nothing more, nothing less. But there are plenty of positive things happening. Most people, however, tend to focus on the negatives. And that’s something that can literally change at any...

thestockexchange.com.au

 

[Taproot]

Hey DB

@FuzM discovered and kindly posted it yesterday.

We all just went dot joining off the back of that

Though, I think it was maybe @Taproot who highlighted that @uiux was also all over BH early on looking for links.

BRN Discussion Ongoing

I am not looking for the moon but just something positive on the back of multiple comments from the company. Nothing more, nothing less. But there are plenty of positive things happening. Most people, however, tend to focus on the negatives. And that’s something that can literally change at any...

thestockexchange.com.au

Actually !, to clarify my own post,
All credit needs to go to @Quatrojos for the original Bascom Hunter dot join.
@uiux started the Bascom thread as well as many other threads to organise his extensive research.
@FuzM put the nail in the coffin.

 

[Bravo]

Well, I've just performed my late night community service over on the Crapper.

Posted here for posterity since it will, no doubt, have an extremely limited life span over there.

 

[Taproot]

Just in case you missed it earlier.

ASIC Solutions

ASICs are exceptionally well-suited for machine learning tasks that require a lot of computational power, such as deep learning and neural network training.

bascomhunter.com

 

[charles2]

Intel news


(Reuters) -Chipmaker Intel said on Monday CEO Pat Gelsinger retired from the chipmaker, effective Dec. 1.
The company named CFO David Zinsner and senior executive Michelle Johnston Holthaus as interim co-chief executive officers while its board conducted a search for a new CEO.
Shares of the company rose nearly 3% in premarket trading.

 

[Fullmoonfever]

Current ESA project with the "Prime Contractor" at the end. Wonder what neuromorphic Edgx might be using

Approaching the Phase Completion Review stage.

Neuromorphic AI Onboard

Our mission is to connect Europe. We join engineers, entrepreneurs and investors to forge strong links between institutions, industries, and businesses.

connectivity.esa.int

Neuromorphic AI Onboard​

• Competitiveness & Growth

• Status
  Ongoing
• Status date
  2024-10-08

Objectives
The proposed activity entails the definition (definition phase) of an onboard neuromorphic AI data processing unit designed for satellite communication (satcom) Low Earth Orbit (LEO) constellations, targeting smallsats. The activity contains three main high level chapters:

1. Identification of potential neuromorphic satcom applications and scenarios.
2. Preliminary benchmarking of neuromorphic algorithms.
3. Define the product architecture, user requirements and technical specifications.

The objectives of the Definition Phase are as follows:

1. Consolidate user requirements and technical specifications: Gather and refine detailed user requirements and technical specifications to ensure that all stakeholder needs are clearly understood and documented.
2. Establish a technical baseline: Develop a foundational technical framework that will serve as the reference point for all subsequent development activities.
3. Complete an initial design concept: Create a preliminary design concept that outlines the overall architecture and key components of the product, ensuring alignment with user requirements and technical specifications.
4. Assess system-level performance: Evaluate the initial design to identify potential performance issues and areas for improvement, ensuring that the system meets expected performance standards.
5. Consolidate the initial business case: Develop and refine the business case for the project, including an analysis of market needs, potential revenue streams, cost estimates, and return on investment projections.

These objectives aim to lay a solid foundation for the subsequent phases of the project, ensuring that all necessary requirements and constraints are understood and addressed early in the development process.
Challenges

The key challenges of the project include integrating diverse processing elements into a cohesive system, ensuring high performance with low power consumption, and overcoming the limitations of traditional computing architectures. Addressing the harsh space environment requirements, such as radiation tolerance and reliability, is critical. Developing a flexible and user-friendly framework for rapid customisation and deployment of AI models, achieving real-time data processing and onboard learning, and ensuring the system's robustness against radiation-induced errors are significant hurdles to overcome.
Benefits

The proposed onboard data processing unit offers significant advantages over existing competitor systems. It integrates a flexible, heterogeneous computing platform, combining traditional and neuromorphic processing elements to enhance real-time data processing and reduce latency. This results in a high performance-to-watt ratio and low Size, Weight, and Power (SWaP) characteristics, crucial for space applications. The system's design allows for easy customisation and rapid deployment of AI models, providing superior flexibility. It addresses existing bottlenecks in data processing, ensuring faster, more efficient operations. Overall, the DPU’s robust, reliable performance in space environments sets it apart from current AI processing solutions, offering a competitive edge in satellite communications.
Features

The product includes a high-performance processing system combining traditional and neuromorphic computing elements to ensure efficient and real-time data processing. The modular design allows for flexible and scalable integration into various satellite architectures.

Key components include high-speed and low-speed interfaces for versatile connectivity and dual storage options for handling large data volumes. The system is built to withstand the harsh conditions of space, with robust hardware and software designed for reliability and resilience. The DPU supports easy customisation and rapid deployment of AI models, facilitating continuous updates and improvements. This combination of advanced processing capabilities, flexible design, and robust construction ensures superior performance and adaptability in space applications.
System Architecture

The system architecture to be developed consists of a modular design with two main interconnected boards: the core board and the neuron board. The core board is responsible for handling high-performance computing tasks, while the neuron board focuses on efficient, low-power AI processing. The architecture integrates multiple processing units, including CPUs, GPUs, AI accelerators and NPU’s, to support diverse and intensive computational requirements. It includes various high-speed and low-speed interfaces for flexible connectivity and robust storage solutions to manage large data volumes. Designed to withstand harsh space environments, the system incorporates safety and reliability features. The software framework facilitates easy deployment and updates, ensuring the system can adapt to evolving mission needs and technological advancements.
Plan

The Definition Phase of the project includes two key milestones. The first is the Mid-Term Review, where use cases are analysed, a shortlist is selected and proposed, and a revised set of product requirements along with the DPU architecture is presented. Additionally, a preliminary analysis of neuromorphic processors and algorithms is performed.

The second milestone is the Phase Completion Review, which involves consolidating the business case, proposing the hardware and software architecture for the product, and completing the analysis of the neuromorphic processor. This phase also includes preliminary benchmarking of neuromorphic algorithms and demonstrations of selected use cases.
Current status

The project is approaching the Phase Completion Review. Achievements include the analysis and selection of use cases, a revised set of product requirements, and the initial DPU architecture. Trade-off and selection of neuromorphic processors and algorithms has been conducted, with the overall hardware and software architecture now proposed. The business plan has been consolidated. Preliminary benchmarking of algorithms with demonstrations of selected use cases have been designed.

Documentation​

Documentation may be requested

Prime Contractor​

EDGX​

Belgium
https://www.edgx.space/

Last update
2024-12-02 13:41

 

[AKM]

Can someone explain this decision please?

Mercedes taps Intel Loihi2 for neuromorphic AI

Mercedes is using the Intel Liohi 2 for neuromorphic computing to improve the performance of forward-facing automotive radar systems.

www.eenewseurope.com

 

[Dallas]

Jeff Bezos investiert in Nvidia-Angreifer Tenstorrent - die große Wette

Tenstorrent wird als Angreifer auf die KI-Marktmacht von Nvidia gehandelt. Jetzt investiert Jeff Bezos 700 Millionen Dollar investiert.

finanzmarktwelt.de