The system features USB 3.0 and micro-USB ports, HDMI, 4GB LPDDR4 memory, 32GB eMMC with up to 1TB micro-SDXC expansion, dual-band Wi-Fi, and two gigabit Ethernet ports for external camera connections, all within a compact, passively-cooled chassis, powered by 12V DC .
Hi Tfm,https://www.tomshardware.com/tech-i...p-claim-625-times-less-power-41-times-smaller
This is quite interesting. I know Samsung has been sniffing around Brainchip at past presentations etc. and Brainchip used a Samsung DVS camera in a demonstration back in 2018/19 ish.
I wonder what this neuromorphic “not off the shelf secret sauce” is that they have used in this test chip?
The second thing that caught my attention is the C transformers talked about. I don’t know what C transformers is exactly, but I think it is safe to say it has something to do with Transformers which is one of the key new features added to the Akida 2.0 architecture based on costumer requests.
@Diogenese can you potentially have a better look at this test chip and see if you can see anything of interest?
To quote Dirty Harry: "I'm sorta wondering myself ..."
I've posted about KAIST a couple of times in the last week or so:
From the Tom's hardware article:
Korean researchers power-shame Nvidia with new neural AI chip — claim 625 times less power draw, 41 times smaller | Tom's Hardware (tomshardware.com)
![www.tomshardware.com](/proxy.php?image=https%3A%2F%2Fcdn.mos.cms.futurecdn.net%2F76WZy692s3CX7WZakbWLEJ-1200-80.jpg&hash=3660052341db5f515a9f34a35ce97a30&return_error=1)
Korean researchers power-shame Nvidia with new neural AI chip — claim 625 times less power draw, 41 times smaller
Claim Samsung-fabbed chip is the first ultra-low power LLM processor.
A team of scientists from the Korea Advanced Institute of Science and Technology (KAIST) detailed their 'Complementary-Transformer' AI chip during the recent 2024 International Solid-State Circuits Conference (ISSCC). The new C-Transformer chip is claimed to be the world's first ultra-low power AI accelerator chip capable of large language model (LLM) processing.
...
The architecture of the C-Transformer chip is interesting to look at and is characterized by three main functional feature blocks. Firstly, there is a Homogeneous DNN-Transformer / Spiking-transformer Core (HDSC) with a Hybrid Multiplication-Accumulation Unit (HMAU) to efficiently process the dynamically changing distribution energy. Secondly, we have an Output Spike Speculation Unit (OSSU) to reduce the latency and computations of spike domain processing. Thirdly, the researchers implemented an Implicit Weight Generation Unit (IWGU) with Extended Sign Compression (ESC) to reduce External Memory Access (EMA) energy consumption.
I haven't found the KAIST C-transformer patent, so it may still be under wraps. Consequently, I can't find any detail of the C-Transformer.
A couple of their earlier patent applications:
US2023098672A1 ENERGY-EFFICIENT RETRAINING METHOD OF GENERATIVE NEURAL NETWORK FOR DOMAIN-SPECIFIC OPTIMIZATION 20210924
YOO HOI JUN [KR]; KIM SO YEON [KR]
The main claim relates to retaining a generative NN:
1 . An energy-efficient retraining method of a generative neural network for domain-specific optimization, the energy-efficient retraining method comprising:
(a) retraining, by a mobile device, a pretrained generative neural network model with respect to some data of a new user dataset;
(b) comparing, by the mobile device, the pretrained generative neural network model and a generative neural network model retrained for each layer with each other in terms of a relative change rate of weights;
(c) selecting, by the mobile device, specific layers having high relative change rate of weights, among layers of the pretrained generative neural network model, as layers to be retrained; and
(d) performing, by the mobile device, weight update for only the layers selected in step (c).
Claim 4 sheds a bit of light on what may be part of the combined DNN-CNN in that it does forward propagation learning, a technique Akida uses (SNN), and subsequently does back propagation (DNN)
4 . The energy-efficient retraining method according to claim 3, wherein, in step (d), the mobile device maintains original weights without weight update for unselected layers, after selecting the k continuous layers, does not perform even back propagation for unselected layers before a first one of the selected layers, performs forward propagation in only a first epoch of retraining, and reuses a result of the forward propagation of the first epoch in repeated retraining epochs thereafter.
This one is about DNN learning:
US2023072432A1 APPARATUS AND METHOD FOR ACCELERATING DEEP NEURAL NETWORK LEARNING FOR DEEP REINFORCEMENT LEARNING 20210831
a deep neural network (DNN) learning accelerating apparatus for deep reinforcement learning, the apparatus including: a DNN operation core configured to perform DNN learning for the deep reinforcement learning; and a weight training unit configured to train a weight parameter to accelerate the DNN learning and transmit it to the DNN operation core, the weight training unit including: a neural network weight memory storing the weight parameter; a neural network pruning unit configured to store a sparse weight pattern generated as a result of performing the weight pruning based on the weight parameter; and a weight prefetcher configured to select/align only pieces of weight data of which values are not zero (0) from the neural network weight memory using the sparse weight pattern and transmit the pieces of weight data of which the values are not zero to the DNN operation core.
Interestingly, KAIST have also been working on MRAM, which could be used in an analog NN:
US2023410864A1 MRAM CELL WITH PAIR OF MAGNETIC TUNNEL JUNCTIONS HAVING OPPOSITE STATES AND MEMORY DEVICE USING THE SAME 20220620
An MRAM cell includes a switch unit configured to determine opening and closing thereof by a word line voltage and to activate a current path between a bit line and a bit line bar in an opened state thereof, first and second MTJs having opposite states, respectively, and connected in series between the bit line and the bit line bar, to constitute a storage node, and a sensing line configured to be activated in a reading mode of the MRAM cell, thereby creating data reading information based on a voltage between the first and second MTJs, wherein the first and second MTJs have different ones of a low resistance state and a high resistance state, respectively, in accordance with a voltage drop direction between the bit line and the bit line bar, thereby storing data of 0 or 1.
All this is no doubt funded by the Korean government who recently announced they were pulling out all the stops to catch up on AI, so perhaps the KAIST hubris is intended to impress their paymasters.
ChatGPT2 is orders of magnitude smaller than ChatGPT3, and nothing like GPT4 and subsequent versions.
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