BRN Discussion Ongoing

[Tothemoon24]

Looks like complimentary tech to AKIDA?
Along the lines of what Prophesee is doing?
Peter might be interested in this, if he doesn't already know..

Hi @DingoBorat

I’ve passed the info on to investor relations.

Big week ahead for the chip , my little brain is thinking

 

[DingoBorat]

@Diogenese when you have time could you provide your opinion on this paper

Dated 9th September 2023
Linked below
Cheers

https://dl.acm.org/doi/full/10.1145/3609101

SoCs equipped with neuromorphic hardware are available, but they rarely consider the integration of non-neuromorphic hardware accelerators. For instance, Akida [6] is an SoC containing an Arm processor that controls the neuromorphic hardware, but does not support the on-chip integration of other hardware accelerators. Similarly, the Loihi SoC [13] consists of a neuromorphic processor and an Intel x86 processor, which merely manages the neuromorphic processor. Loihi is typically deployed as part of a Nahuku expansion board [21, 22], which contains up to 32 interconnected Loihi chips that all interface with the same on-board Arria 10 FPGA. This FPGA is used to interact with the surroundings, notably via sensors and actuators. Additionally, the FPGA is controlled by an off-chip processor (distinct from the aforementioned x86 processor) from which the high-level software application is executed, such as compiling the neuromorphic model and visualizing results.

I skimmed it and these guys look like they know their sheet..
And they are bagging AKIDA, in a sense, lumping us with TrueNorth and Loihi 2..

What they're doing is "Open source" WTF is their game?..

I'd like to know what Diogenese thinks too and Peter, on this one..

 

[Tothemoon24]

I skimmed it and these guys look like they know their sheet..
And they are bagging AKIDA, in a sense, lumping us with TrueNorth and Loihi 2..

View attachment 46025

What they're doing is "Open source" WTF is their game?..

I'd like to know what Diogenese thinks too and Peter, on this one..

I’ve sent it Brainchip , I’ll let you know if I get a reply

 

[BigDonger101]

I will have a closer look later - too bizi now ......... but what you say to Bacon does not sound right to me.
You make it sound so simple when it AIN'T

I don't know what you're saying here, sorry.

 

[Diogenese]

@Diogenese when you have time could you provide your opinion on this paper

Dated 9th September 2023
Linked below
Cheers

https://dl.acm.org/doi/full/10.1145/3609101

SoCs equipped with neuromorphic hardware are available, but they rarely consider the integration of non-neuromorphic hardware accelerators. For instance, Akida [6] is an SoC containing an Arm processor that controls the neuromorphic hardware, but does not support the on-chip integration of other hardware accelerators. Similarly, the Loihi SoC [13] consists of a neuromorphic processor and an Intel x86 processor, which merely manages the neuromorphic processor. Loihi is typically deployed as part of a Nahuku expansion board [21, 22], which contains up to 32 interconnected Loihi chips that all interface with the same on-board Arria 10 FPGA. This FPGA is used to interact with the surroundings, notably via sensors and actuators. Additionally, the FPGA is controlled by an off-chip processor (distinct from the aforementioned x86 processor) from which the high-level software application is executed, such as compiling the neuromorphic model and visualizing results.

Hi TTM,

While I'm not qualified to mark everybody's essays, I would take issue with the underlying principle of this paper that:

'SoCs equipped with neuromorphic hardware are available, but they rarely consider the integration of non-neuromorphic hardware accelerators. For instance, Akida [6] is an SoC containing an Arm processor that controls the neuromorphic hardware, but does not support the on-chip integration of other hardware accelerators.'

This is a reference to Akida 1, SoC, not the Akida IP, but, in any event, the suggested limitations do not apply to either the SoC or the IP.

The whole idea of Akida IP is so that it can be integrated with other IC components, from doorbells to lidar, just as Akida 1 is adapted to work with the whole gamut of processors. As we know, Akida 1 has been demonstrated to work with key word recognition, lidar, DVS, breath analysers, ... . In addition, Akida has been produced in radhard form and in 22 nm FDSoI, and has been proven to be compatible across the range of ARM processors, which presumably includes the M85 with AI hardware Ethos and Helium software (even if it makes them superfluous).

The statement that the ARM processor controls the neuromorphic hardware is not correct. The ARM, or any other processor is used only in setting up the SNN (configuration, loading weights and model libraries), but the processor plays no part in the inference/classification function of Akida 1, and probably very little in the more advanced functions of Akida 2 (TeNNs, ViT, Skip).

Towards this goal, we developed SpikeHard, a runtime-programmable neuromorphic hardware accelerator designed under the premises of high efficiency, scalability, and seamless integration in heterogeneous many-accelerator SoCs. As shown in Figure 1, our design methodology follows innovative restructuring of SNNs, which optimally remaps an SNN model to a desired hardware architecture. This promotes multi-objective design-space exploration (DSE) that helps to meet strict performance and energy-efficiency requirements in a many-accelerator SoC.

Akida is configurable from 2 nodes (8 NPUs), up to 64 nodes, and several Akida's can be ganged together. MetaTF is used in optimizing the configuration of Akida.

Our friends at Renesas are proud of their DRP-AI (not a NN), but it is dynamically reconfigurable, but I'm not familiar with the details.

Having lumped Akida in with True North and Loihi, the paper then goes on to discuss perceived deficiencies in the IBM and Intel products and, by implication, attributing those deficiencies to Akida without any analysis of Akida.

The problem the authors addressed:

This model generation has two main weaknesses. First, the sequential generation at the level of each core imposes a dependency between the computational model and the hardware architecture. Second, after model generation, there is no process that checks for redundancy and efficient resource utilization.

As part of developing SpikeHard, we initially focused on the second weakness by optimizing SNNs that were generated by RANC with a dependency to a hardware architecture. In particular, we analyzed the original placement of neurons and axons, and provided an optimized placement according to the original capacity of each core. As shown in Figure 3, our method dramatically improves inner core utilization from an average of 50%50% for the original model to 85%85%, while also reducing the overall core count by 40%40%. In this way, we eliminate the redundancies at the level of a core and of the full neuromorphic processor, thereby solving the second weakness.

remembering that Akida can run different models, eg, face recognition, gesture recognition, voice recognition, I don't see how the following relates to Akida:

RANC only allows the SNN model to be configured at design time [26]. Specifically, each core stores model parameters, such as how neurons and axons are connected to one another, in immutable local buffers initialized via Verilog initial blocks. Consequently, in the case of an FPGA implementation, loading a new model to RANC requires synthesizing a new bitstream and reconfiguring the FPGA, which is time-consuming and impractical for real-time systems. In the case of an ASIC implementation, the immutable buffers would have to be initialized using an additional mechanism instead of initial blocks. Nevertheless, without programmability, the ASIC design would be unable to accommodate multiple SNN models at runtime.
In contrast, SpikeHard is a flexible hardware accelerator whose configuration can be programmed at runtime to process various SNN models. The neuromorphic processor inside SpikeHard uses the same core architecture as RANC with a few changes to support runtime programmability. To load a new model at runtime, SpikeHard overwrites the aforementioned local buffers with new model parameters. To this end, as illustrated in Figure 1(b), the new model parameters are broadcasted one after the other to all cores while being streamed from main memory. Alongside each parameter is a pointer, which specifies the destination core and buffer address. The destination core then writes the parameter to the specified address. Given a SpikeHard accelerator embedded with a grid of cores and a fixed core capacity, multiple different SNN models can be offloaded onto the accelerator by simply restructuring the models to fit within the core capacity and the grid dimensions (as described in Section 3.4).

So if I'm reading this correctly, they can only run different models sequentially, not simultaneously in parallel.

Because Akida is readily reconfigurable, I'm not sure that this paper is particularly relevant to Akida.

 

[Tothemoon24]

Hi TTM,

While I'm not qualified to mark everybody's essays, I would take issue with the underlying principle of this paper that:

'SoCs equipped with neuromorphic hardware are available, but they rarely consider the integration of non-neuromorphic hardware accelerators. For instance, Akida [6] is an SoC containing an Arm processor that controls the neuromorphic hardware, but does not support the on-chip integration of other hardware accelerators.'

This is a reference to Akida 1, SoC, not the Akida IP, but, in any event, the suggested limitations do not apply to either the SoC or the IP.

The whole idea of Akida IP is so that it can be integrated with other IC components, from doorbells to lidar, just as Akida 1 is adapted to work with the whole gamut of processors. As we know, Akida 1 has been demonstrated to work with key word recognition, lidar, DVS, breath analysers, ... . In addition, Akida has been produced in radhard form and in 22 nm FDSoI, and has been proven to be compatible across the range of ARM processors, which presumably includes the M85 with AI hardware Ethos and Helium software (even if it makes them superfluous).

The statement that the ARM processor controls the neuromorphic hardware is not correct. The ARM, or any other processor is used only in setting up the SNN (configuration, loading weights and model libraries), but the processor plays no part in the inference/classification function of Akida 1, and probably very little in the more advanced functions of Akida 2 (TeNNs, ViT, Skip).

Towards this goal, we developed SpikeHard, a runtime-programmable neuromorphic hardware accelerator designed under the premises of high efficiency, scalability, and seamless integration in heterogeneous many-accelerator SoCs. As shown in Figure 1, our design methodology follows innovative restructuring of SNNs, which optimally remaps an SNN model to a desired hardware architecture. This promotes multi-objective design-space exploration (DSE) that helps to meet strict performance and energy-efficiency requirements in a many-accelerator SoC.


View attachment 46032


Akida is configurable from 2 nodes (8 NPUs), up to 64 nodes, and several Akida's can be ganged together. MetaTF is used in optimizing the configuration of Akida.

Our friends at Renesas are proud of their DRP-AI (not a NN), but it is dynamically reconfigurable, but I'm not familiar with the details.

Having lumped Akida in with True North and Loihi, the paper then goes on to discuss perceived deficiencies in the IBM and Intel products and, by implication, attributing those deficiencies to Akida without any analysis of Akida.

The problem the authors addressed:

This model generation has two main weaknesses. First, the sequential generation at the level of each core imposes a dependency between the computational model and the hardware architecture. Second, after model generation, there is no process that checks for redundancy and efficient resource utilization.

As part of developing SpikeHard, we initially focused on the second weakness by optimizing SNNs that were generated by RANC with a dependency to a hardware architecture. In particular, we analyzed the original placement of neurons and axons, and provided an optimized placement according to the original capacity of each core. As shown in Figure 3, our method dramatically improves inner core utilization from an average of 50%50% for the original model to 85%85%, while also reducing the overall core count by 40%40%. In this way, we eliminate the redundancies at the level of a core and of the full neuromorphic processor, thereby solving the second weakness.

remembering that Akida can run different models, eg, face recognition, gesture recognition, voice recognition, I don't see how the following relates to Akida:

RANC only allows the SNN model to be configured at design time [26]. Specifically, each core stores model parameters, such as how neurons and axons are connected to one another, in immutable local buffers initialized via Verilog initial blocks. Consequently, in the case of an FPGA implementation, loading a new model to RANC requires synthesizing a new bitstream and reconfiguring the FPGA, which is time-consuming and impractical for real-time systems. In the case of an ASIC implementation, the immutable buffers would have to be initialized using an additional mechanism instead of initial blocks. Nevertheless, without programmability, the ASIC design would be unable to accommodate multiple SNN models at runtime.
In contrast, SpikeHard is a flexible hardware accelerator whose configuration can be programmed at runtime to process various SNN models. The neuromorphic processor inside SpikeHard uses the same core architecture as RANC with a few changes to support runtime programmability. To load a new model at runtime, SpikeHard overwrites the aforementioned local buffers with new model parameters. To this end, as illustrated in Figure 1(b), the new model parameters are broadcasted one after the other to all cores while being streamed from main memory. Alongside each parameter is a pointer, which specifies the destination core and buffer address. The destination core then writes the parameter to the specified address. Given a SpikeHard accelerator embedded with a grid of cores and a fixed core capacity, multiple different SNN models can be offloaded onto the accelerator by simply restructuring the models to fit within the core capacity and the grid dimensions (as described in Section 3.4).

So if I'm reading this correctly, they can only run different models sequentially, not simultaneously in parallel.

Because Akida is readily reconfigurable, I'm not sure that this paper is particularly relevant to Akida.

Thank you so much for the reply Dio ,

I’ll sleep easier knowing that there still may come a day when I’ll eat a rib eye again

 

[Diogenese]

Thank you so much for the reply Dio ,

I’ll sleep easier knowing that there still may come a day when I’ll eat a rib eye again

... and have a 389 to boot!

 

[Esq.111]

Morning Chippers,

Article on drone company .

The vidio is worth a watch , nothing directly BRN .



Regards,
Esq.

 

[skutza]

Need to break and hold 20c

 

[Calsco]

New week, let’s hope for some announcements and IP contracts are we still anticipating the release of 2.0 sometime in the future?

 

[Fenris78]

View attachment 46039

Need to break and hold 20c

Need to break and hold $2.00!

 

[skutza]

Need to break and hold $2.00!

LOl, yes, small steps though

 

[DK6161]

New week, let’s hope for some announcements and IP contracts are we still anticipating the release of 2.0 sometime in the future?

Yeah we're just waiting for TD to be back from leave to do the announcement, then the SP should go back $2.0 easy

Not advice.

 

[jtardif999]

In my view based on the events and happenings over the lst 3 years the below scenario occurring would not surprise me one little bit….

ARM slowly building up an unofficial position in BRN through unrelated parties.. They’ve already infiltrated BRN with many ex ARM employees..
Any number of institutions x 5-6 or more could accumulate 4-4.5% over time not signalling any substantial holder notices, gradually buying and selling to each other whilst the price lowers, and at the same time loaning out to short sellers.

Then when there is a controlling interest large enough, let the good news start coming out with a few official contracts and products sticking, pushing the market cap back towards 1billion. ARM comes in and you offers 1.5billion, PVDM and Anil get sweet deals to go on the ARM BOD with relevant interests and holdings, their product Akida gets onto market as they want and the ASX shareholders as usual get screwed over…

Stranger things have happened I’m sure..

What a load of rubbish. Do you think Peter and Anil would sell out for a $1 a share when their life’s work has gone into Akida just for a spot on ARMs board? Ridiculous twat, we should be asking you what your agenda is rather than ARMs. You spread negative sentiment at every opportunity and seem to be motivated by putting doubt in other SH minds.

 

[Schnitzel lover]

What a load of rubbish. Do you think Peter and Anil would sell out for a $1 a share when their life’s work has gone into Akida just for a spot on ARMs board? Ridiculous twat, we should be asking you what your agenda is rather than ARMs. You spread negative sentiment at every opportunity and seem to be motivated by putting doubt in other SH minds.

One would hope that SH's could think for themselves as adults, and have sound risk management with their investments.

I am simply not naive enough to rule my opinion out as a possibility. We all like dot joining here of which I am respectful and support whether positive or negative.

I definitely feel for outraged shareholders that have emotionally been screwed over by big losses.. I will gladly take one to the jewels if PVDM and Co can ride things out with their positions and roles intact..

These are just my thoughts. Looking forward to seeing some tangible process that can allow me to state some positive opinions and facts..

 

[Glen]

Automotive Custom SoC Technologies and Solutions

Socionext’s advanced automotive custom SoC solutions are designed to help OEMs and tier-one automakers achieve differentiating technologies

socionextus.com

 

[skutza]

While the shorts are still there, we haven't seen this for a long time? See what is missing.

 

[AusEire]

What a load of rubbish. Do you think Peter and Anil would sell out for a $1 a share when their life’s work has gone into Akida just for a spot on ARMs board? Ridiculous twat, we should be asking you what your agenda is rather than ARMs. You spread negative sentiment at every opportunity and seem to be motivated by putting doubt in other SH minds.

I absolutely 100% agree with you re Peter and Anil selling for $1 per share. There's absolutely no way they would accept it.

In my opinion it would take an offer well North of $5 per share to even consider it.

 

[Esq.111]

While the shorts are still there, we haven't seen this for a long time? See what is missing.
View attachment 46044

Afternoon Skutza,

BRN pressently No.22 with 6.27% short as of 26th Sep.

Regards,
Esq.

 

[Bravo]

Ambient computing. Processing the world in real time.

A Silicon Valley Supergroup Is Coming Together to Create an A.I. Device (Published 2023)

OpenAI’s Sam Altman, the former Apple designer Jony Ive and SoftBank’s Masayoshi Son are teaming up to develop a device that could replace the smartphone.

www.nytimes.com

Extract 1

Extract 2