BRN Discussion Ongoing
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Yes ... 1.4 bill now and may well be 1.5 bill by close.
White Horse
Regular
8 nodes is obviously a sweet spot for Akida.
Both Akida 1500 and Akida 2S offer 8 nodes.
SiFive suggests that Akida 2S is not for on-sensor applications, but rather for integrating into a CPU, so Akida 2S can do a lot of the heavy lifting:
“Through our collaboration with BrainChip, we are enabling the combination of SiFive’s RISC-V processor IP portfolio and BrainChip’s 2nd generation Akida neuromorophic IP to provide a power-efficient, high capability solution for AI processing on the Edge,” said Phil Dworsky, Global Head of Strategic Alliances at SiFive. “Deeply embedded applications can benefit from the combination of compact SiFive Essential™ processors with BrainChip’s Akida-E, efficient processors; more complex applications including object detection, robotics, and more can take advantage of SiFive X280 Intelligence™ AI Dataflow Processors tightly integrated with BrainChip’s Akida-S or Akida-P neural processors.”
Phil Dworsky, Global Head of Strategic Alliances, SiFive
SiFive has several "Essential" processor cores. SiFive E20 looks like a good match for Akida 2E:
https://www.riscfive.com/2022/12/07...SC-V ISA to provide 64-bit and 32-bit options.
The SiFive X280 Intelligence is more powerful and AI/ML capable:
https://www.sifive.com/cores/intelligence-x280
The SiFive Intelligence™ X280 is a multi-core capable RISC-V processor with vector extensions and SiFive Intelligence Extensions and is optimized for AI/ML compute at the edge.
In addition to ML inferencing, it is ideal for applications requiring high-throughput, single-thread performance while under power constraints (e.g., AR, VR, sensor hubs, IVI systems, IP cameras, digital cameras, gaming devices).
...
SiFive X280 Intelligence data sheet:
https://sifive.cdn.prismic.io/sifive/70445cba-0549-475e-a538-5c09a402efbc_x280-datasheet-22G1.pdf
Here's a coincidence:-
The smallest byte that the X280 Intelligence can accept is 8 bits ...
If only Akida had an 8 bit version it could be tightly integrated with SiFive's X280 Intelligence processor.
Both Akida 1500 and Akida 2S offer 8 nodes.
SiFive suggests that Akida 2S is not for on-sensor applications, but rather for integrating into a CPU, so Akida 2S can do a lot of the heavy lifting:
“Through our collaboration with BrainChip, we are enabling the combination of SiFive’s RISC-V processor IP portfolio and BrainChip’s 2nd generation Akida neuromorophic IP to provide a power-efficient, high capability solution for AI processing on the Edge,” said Phil Dworsky, Global Head of Strategic Alliances at SiFive. “Deeply embedded applications can benefit from the combination of compact SiFive Essential™ processors with BrainChip’s Akida-E, efficient processors; more complex applications including object detection, robotics, and more can take advantage of SiFive X280 Intelligence™ AI Dataflow Processors tightly integrated with BrainChip’s Akida-S or Akida-P neural processors.”
Phil Dworsky, Global Head of Strategic Alliances, SiFive
SiFive has several "Essential" processor cores. SiFive E20 looks like a good match for Akida 2E:
https://www.riscfive.com/2022/12/07...SC-V ISA to provide 64-bit and 32-bit options.
SiFive E20
The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines.The SiFive X280 Intelligence is more powerful and AI/ML capable:
https://www.sifive.com/cores/intelligence-x280
The SiFive Intelligence™ X280 is a multi-core capable RISC-V processor with vector extensions and SiFive Intelligence Extensions and is optimized for AI/ML compute at the edge.
In addition to ML inferencing, it is ideal for applications requiring high-throughput, single-thread performance while under power constraints (e.g., AR, VR, sensor hubs, IVI systems, IP cameras, digital cameras, gaming devices).
...
SiFive X280 Intelligence data sheet:
https://sifive.cdn.prismic.io/sifive/70445cba-0549-475e-a538-5c09a402efbc_x280-datasheet-22G1.pdf
Here's a coincidence:-
The smallest byte that the X280 Intelligence can accept is 8 bits ...
If only Akida had an 8 bit version it could be tightly integrated with SiFive's X280 Intelligence processor.
Fact Finder
Top 20
I was reading a Taiwanese Trade Show advert (see @Taproot post above) where SiFive are THE attraction with multiple speakers and demonstrations. I was using Google translate because it was not in English but one of the SiFive presenters in his blurb was saying that SiFive’s RISC-V is set to takeover from traditional semiconductors. That did seem like sales talk and science fiction all rolled up into one package.
My opinion only DYOR
FF
AKIDA BALLISTA
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Taproot
Regular
RISC-V - SiFive
SiFive was founded by the inventors of RISC-V, who have been developing the RISC-V instruction Set Architecture (ISA) since 2010. Focused on RISC-V solutions, that initial team of RISC-V innovators later founded SiFive.
www.sifive.com
HopalongPetrovski
I'm Spartacus!
That's why all our key staff have great hearing, especially for listening and co-operating when a company other than ours
makes an engineering suggestion that ultimately benefits both parties...that's my definition of "Beneficial AI".
The love affair continues, anyone willing to loan me, say $500,000 to 1Million AUD ? in my opinion this current pattern is heading
for a major shake up beyond April, is AKD1500 being baked for a client/s, I (sense) it is ? wrong, we shall see.
Texta
Fullmoonfever
Top 20
@Diogenese
Thoughts on this latest NASA SBIR paper and the relevant to BRN section highlighted towards end of post.
In your thinking, does our recent discussions around 22nm FDSOI, the X280 NASA use and recent Akida platform upgrade have any applicability to the NASA comments re critical gaps possibly being filled?
TIA
Couldn't attach full paper as extension not compatible and just on moby at the mo.
National Aeronautics and Space Administration
Small Business
Innovation Research (SBIR)
Phase I
Fiscal Year 2023 Solicitation
Scope Title: Neuromorphic Software for Cognition and Learning for Space Missions
Scope Description:
This scope seeks integrated neuromorphic software systems that together achieve a space mission capability. Such capabilities include but are not limited to:
• Cognitive communications for constellations of spacecraft.
• Spacecraft health and maintenance from anomaly detection through diagnosis; prognosis; and fault detection, isolation, and recovery (FDIR).
• Visual odometry, path planning, and navigation for autonomous rovers.
• Science data processing from sensor denoising, through sensor fusion and super resolution, and finally output the generation of science information products such as planetary digital elevation maps.
In this scope, it is expected that a provider will pipeline together a number of neural nets from different sources to achieve a space capability. The first challenge is to achieve the pipelining in a manner that achieves high overall throughput and is energy efficient. The second challenge is to put together a demonstration breadboard integrated hardware/software system that achieves the throughput incorporating neuromorphic or neural net accelerators perhaps in combination with conventional processors such as CPUs, GPUs, and FPGAs. Systems on a chip (SOC), could be another demonstration hardware platform. In either case, the neural cores should do the heavy computational lifting, and the CPUs, GPUs, and FPGAs should play a supportive role. The total power requirements shall be commensurate with the space domain, for example, 10 W maximum for systems expected to operate on CubeSats 24/7 and even less wattage for lunar systems that need to operate on battery power over the 2-week-long lunar night.
The third optional challenge is to evolve the neural net individual applications and pipeline through adaptive learning over the course of a simulated mission.
Radiation tolerance and space environment robustness are not addressed directly through this scope. Rather, a provider is expected to use terrestrial grade processors and only after Phase II target radiation tolerant neuromorphic processors potentially developed under Scopes 1 or 2 or from another source. The goal is to achieve space mission capabilities that require system integration of individual neural nets together with minimal overhead conventional software. The continuous mission-long learning complements the capability of Earth operations to adapt software over the course of a mission.
As background, development of individual neural net software is now state of the practice, and a large number of neural net applications can be downloaded in standard formats such as pseudo-assembly level or programming languages such as TensorflowTM (Google Inc), PyTorchTM (Linux Foundation), NengoTM (Applied Brain Research), LavaTM (Intel Cooporation), and others. Published neural nets for aerospace applications can be found, ranging from telescope fine-pointing control to adaptive flight control to medical support for astronaut health. In addition, there are many published neural nets for analogous terrestrial capabilities, such as autonomous driving. Transfer learning and other state-of-practice techniques enable adaptation of neural nets from terrestrial domains, such as image-processing for the image net challenge, to space domains such as Mars terrain classification for predicting rover traction.
Expected TRL or TRL Range at completion of the Project: 2 to 4
Primary Technology Taxonomy:
• Level 1: TX 10 Autonomous Systems
• Level 2: TX 10.2 Reasoning and Acting
Desired Deliverables of Phase I and Phase II:
• Analysis
• Prototype
• Hardware
• Software
Desired Deliverables Description:
The deliverables for Phase I should include at minimum the concept definition of a space capability that could be achieved through a dataflow pipeline/graph of neural nets and identification of at least a portion of the pipeline that can be achieved with existing neural nets that are either already suited for the space domain or provide an analogous capability from an Earth application. The pipeline should at a minimum be mocked up and characterized by parameterized throughput requirements for the individual neural nets, a description of the dataflow and control flow integration of the system of neural nets, and an assignment and mapping from the individual software components to the hardware elements, and an energy/power/throughput estimate for the entire pipeline. Enhanced deliverables for Phase I would include a partial demonstration of the pipeline on some terrestrial hardware platform. A report that illustrates a conceptual pipeline of neural nets for autonomous rovers can be found in the reference authored by Eric Barszcz.
The deliverables for Phase II should include at minimum a demonstration hardware system, using terrestrial grade processors and sensors, that performs a significant portion of the overall pipeline needed for the chosen space capability, together with filling in at least some of the neural net applications that needed to be customized, adapted, or developed from scratch. It is expected that the hardware system would include one or more terrestrial grade neuromorphic processors that do the primary processing, with support from CPUs, GPUs, and FPGAs. An alternative would be an SOC that incorporates a substantial number of neural cores. The demonstration shall include empirical measurement and validation of throughput and power. Enhanced deliverables for Phase II would be a simulation of continuous in situ mission-long adaptation and learning that exhibits significant evolution.
State of the Art and Critical Gaps:
Neuromorphic and deep neural net software for point applications has become widespread and is state of the art. Integrated solutions that achieve space-relevant mission capabilities with high throughput and energy efficiency is a critical gap. For example, terrestrial neuromorphic processors such as Intel Corporation’s LoihiTM, Brainchip's AkidaTM, and Google Inc's Tensor Processing Unit (TPUTM) require full host processors for integration for their software development kit (SDK) that are power hungry or limit throughput. This by itself is inhibiting the use of neuromorphic processors for low SWaP space missions. The system integration principles for integrated combinations of neuromorphic software is a critical gap that requires R&D, as well as the efficient mapping of integrated software to integrated avionics hardware. Challenges include translating the throughput and energy efficiency of neuromorphic processors from the component level to the system level, which means minimizing the utilization and processing done by supportive CPUs and GPUs.
Relevance / Science Traceability:
• 03-09a (Autonomous self-sensing)
• 04-15 (Collision avoidance maneuver design)
• 04-16 (Consolidated advanced sensors for relative navigation and autonomous robotics)
• 04-23 (Robotic actuators, sensors, and interfaces)
• 04-77 (Low SWaP, “End of arm” proximity range sensors)
• 04-89 (Autonomous Rover GNC for mating)
• 10-04 (Integrated system fault/anomaly detection, diagnosis, prognostics)
• 10-05 (On-Board "thinking" autonomy)
• 10-06 (Creation, scheduling and execution of activities by autonomous systems)
• 10-16 (Fail operational robotic manipulation)
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Rise from the ashes
Regular
Happy to obligeThat's why all our key staff have great hearing, especially for listening and co-operating when a company other than ours
makes an engineering suggestion that ultimately benefits both parties...that's my definition of "Beneficial AI".
The love affair continues, anyone willing to loan me, say $500,000 to 1Million AUD ? in my opinion this current pattern is heading
for a major shake up beyond April, is AKD1500 being baked for a client/s, I (sense) it is ? wrong, we shall see.
Texta
Maybe a little lost in translation.
I have been confident that the SiFive/BrainChip partnership was going places from day 1.
https://brainchip.com/brainchip-sifive-partner-deploy-ai-ml-at-edge/ (20220405)
Intel need RISC-V, and what better way than with Akida 2?
https://www.sifive.com/press/sifive-partners-with-intel-to-spark-innovation-in-high-performance
SAN MATEO, Calif., February 7, 2022 – SiFive, Inc., the founder and leader of RISC-V computing, today announced the company will support Intel Foundry Services (IFS) innovation fund’s goal to build innovative new RISC-V computing platforms optimized for Intel process technology. The $1B Intel fund will support the creation of disruptive technologies to address modern computing challenges, with the Intel-SiFive collaboration aiming to extend the RISC-V ecosystem. Compute blocks in future silicon chips, optimized for specific classes of workloads, require a vibrant market of semiconductor IP that is further enabled by SiFive’s leading RISC-V processor IP optimized and available to customers of IFS. The open nature of the RISC-V instruction set architecture creates freedom to innovate, with specifications and extensions developed by expert contributors from leaders in the semiconductor industry, research institutions, and academia.
SiFive has partnered with IFS to develop a RISC-V development platform, codenamed “Horse Creek,” featuring a multi-core SiFive Performance™ P550 processor, and implemented on the Intel 4 technology platform, on track for availability in 2022. The “Horse Creek” SoC will enable a new generation of RISC-V developer boards, continuing the tradition of SiFive HiFive boards that have helped drive the growth of the RISC-V ecosystem.
"Horse Creek" - that's an interesting name - in Australia there's a creek called "Rocky Creek" which seems to run the whole length of the east coast, but, in fact, it is a tributary of Sandy Creek.
Taproot
Regular
For example, Apple’s A15 has more than a dozen Arm-based CPU cores distributed across the die for various non-user-facing functions. SemiAnalysis can confirm that these cores are actively being converted to RISC-V in future generations of hardware.
Every one of Tenstorrent’s TenSix processor tiles includes X280 CPUs.
SiFive can offer something Arm cannot, flexibility. Customers can modify their cores by adding hardware accelerators directly into the vector register file. This can be used for extending the X280 core to applications such as DSP, image signal processing, and AI. This is where the Google collaboration comes in.
Google already uses 3rd party ASIC design services with Broadcom for the TPU and VCU. The internal teams focus on what is differentiated to their use case. In the case of the TPU, it is the Matrix Multiply Unit and the Inter-Chip Interconnect. Google is taking a sensible approach to their TPUs by outsourcing redundant work. Instead of building everything from scratch, they will now use X280’s VCIX mode.
www.semianalysis.com
PS. The Google VCU link makes for super interesting reading.
Every one of Tenstorrent’s TenSix processor tiles includes X280 CPUs.
SiFive can offer something Arm cannot, flexibility. Customers can modify their cores by adding hardware accelerators directly into the vector register file. This can be used for extending the X280 core to applications such as DSP, image signal processing, and AI. This is where the Google collaboration comes in.
Google already uses 3rd party ASIC design services with Broadcom for the TPU and VCU. The internal teams focus on what is differentiated to their use case. In the case of the TPU, it is the Matrix Multiply Unit and the Inter-Chip Interconnect. Google is taking a sensible approach to their TPUs by outsourcing redundant work. Instead of building everything from scratch, they will now use X280’s VCIX mode.
SiFive Powers Google TPU, NASA, Tenstorrent, Renesas, Microchip, And More
RISC-V Is The Standard For non-user-facing functions.
www.semianalysis.com
PS. The Google VCU link makes for super interesting reading.
Roy Rogers! C'mon,...................pleeeeeeease.
He t'aint no Hopalong Cassidy.
Hopalong's the name.....giddalong liddle dosies, the game.
Watch how Hoppy handles dem dastardly shorters and you betcha he later gets to lullaby bigtime with that lumpy shirted dude.
Gee that was a good shot from those hills a couple of miles away!
Roy Rogers! C'mon,...................pleeeeeeease.
He t'aint no Hopalong Cassidy.
Hopalong's the name.....giddalong liddle dosies, the game.
Watch how Hoppy handles dem dastardly shorters and you betcha he later gets to lullaby bigtime with that lumpy shirted dude.
Why sorry Pardner ( said in Hoppy's slow drawl)
So that's where John Wayne got his slow drawl from! The rider and horse speeding down the hill reminded me of the similar scene in The Man From Snowy River.
HopalongPetrovski
I'm Spartacus!
Sure shooting' t'was.
Good with a gun and good with a rope.
And that white horse.....Dang!
Are you impressed with the capability of Akida 2 Diogenese?
Surprised? Delighted?
As our resident Tech expert would love to have your considered opinion, if you're willing?
Also your views on what would be the killer applications for the E,S, and P versions?
And anything else you'd like to volunteer, please.
VictorG
Member
Not sure what to make of this, when I looked at their partners ecosystem I found Socionext and Renesas as technology partners.
I think/hope Akida is in Hailo-15 through either Renesas or Socionext.
hailo.ai
Leading Edge AI Chipmaker Hailo Introduces Hailo-15: The First AI-Centric Vision Processors for Next-Generation Intelligent Cameras
www.prnewswire.com
I think/hope Akida is in Hailo-15 through either Renesas or Socionext.
AI Partnerships: Hailo's Ecosystem Driving AI Business Solutions
Seize AI partnership opportunities with Hailo and tap into a thriving AI ecosystem for innovative AI business solutions & transformation.
hailo.ai
Leading Edge AI Chipmaker Hailo Introduces Hailo-15: The First AI-Centric Vision Processors for Next-Generation Intelligent Cameras
Leading Edge AI Chipmaker Hailo Introduces Hailo-15: The First AI-Centric Vision Processors for Next-Generation Intelligent Cameras
/PRNewswire/ -- Hailo, the pioneering chipmaker of edge artificial intelligence (AI) processors, today announced its groundbreaking new Hailo-15™ family of...
Rise from the ashes
Regular
"E,S and P versions"Sure shooting' t'was.
Good with a gun and good with a rope.
And that white horse.....Dang!
Are you impressed with the capability of Akida 2 Diogenese?
Surprised? Delighted?
As our resident Tech expert would love to have your considered opinion, if you're willing?
Also your views on what would be the killer applications for the E,S, and P versions?
And anything else you'd like to volunteer, please.
Extrasensory perception: perception or communication outside of normal sensory capability, as in telepathy and clairvoyance
Norse clairvoyant shapeshifter goddess
Fact Finder
Top 20
Renesas & Socionext have both been partnered separately with Hailo for years yet both keep on keeping on with Brainchip and AKIDA.Not sure what to make of this, when I looked at their partners ecosystem I found Socionext and Renesas as technology partners.
I think/hope Akida is in Hailo-15 through either Renesas or Socionext.
AI Partnerships: Hailo's Ecosystem Driving AI Business Solutions
Seize AI partnership opportunities with Hailo and tap into a thriving AI ecosystem for innovative AI business solutions & transformation.
Leading Edge AI Chipmaker Hailo Introduces Hailo-15: The First AI-Centric Vision Processors for Next-Generation Intelligent Cameras
Leading Edge AI Chipmaker Hailo Introduces Hailo-15: The First AI-Centric Vision Processors for Next-Generation Intelligent Cameras
/PRNewswire/ -- Hailo, the pioneering chipmaker of edge artificial intelligence (AI) processors, today announced its groundbreaking new Hailo-15™ family of...
Hailo is an accelerator and uses more power than AKIDA and the last time I looked was 2021 and it was running at multiple watts. In 2020 Socionext, Foxconn and Hailo had a product out cannot remember now exactly what it was but not in any way competing with AKIDA 1000 and now with AKIDA 2000 and it’s performance levels well it’s a look out Hailo AKIDA is coming through.
My opinion only DYOR
FF
AKIDA BALLISTA
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