BRN Discussion Ongoing

[Rach2512]

Thoughts?

GitHub - lightborneintelligence/spikelink: Spike-native transport protocol for neuromorphic systems. Preserves spike timing and magnitude without ADC/DAC conversion. | Jesus Carrasco

We just open-sourced SpikeLink v2 — a spike-native transport protocol purpose-built for neuromorphic chip-to-chip communication. The problem: neuromorphic processors like Intel's Loihi 3 and BrainChip's Akida communicate internally through spikes — asynchronous, event-driven signals where...

www.linkedin.com

 

[Diogenese]

Thoughts?

GitHub - lightborneintelligence/spikelink: Spike-native transport protocol for neuromorphic systems. Preserves spike timing and magnitude without ADC/DAC conversion. | Jesus Carrasco

We just open-sourced SpikeLink v2 — a spike-native transport protocol purpose-built for neuromorphic chip-to-chip communication. The problem: neuromorphic processors like Intel's Loihi 3 and BrainChip's Akida communicate internally through spikes — asynchronous, event-driven signals where...

www.linkedin.com

Hi Rach,

I don't think the possum is in the tree Jesus is barking up.

He's labouring under a misconception that Akida's "spikes" are analog and not normal binary digital bytes. The prototype Akida 1 used a single binary bit to represent a spike, but it was not an analog spike. It was a binary digital bit. The commercial version upped the "spike" to 4 binary digital bits. Akida does not need ADC (analog to digital converter) to talk to associated digital equipment. In fact Akida has a number of external digital interfaces adapted to utilize different digital communication protocols without using ADC

An ADC converts an analog voltage signal to digital format by producing a digital byte whose value is proportional to the size of the spike voltage. Manufacturing variability and temperature instability make this an unreliable process when thousands of ADC operations are involved.

Akida 3/GenAI will move away from an internal packet transport mesh to a solid state switched transport mesh because this gets rid of the packet header overload (to which Jesus has directed his efforts) and the associated bit switching operations.

 

[GStocks123]

First time I’ve read of a partner testing TENNs.

Designing Ultra-Low-Power Vision Pipelines on Neuromorphic Hardware

MulticoreWare, ultra‑low‑power vision pipelines, neuromorphic hardware, edge AI, temporal event‑based neural networks, TENNs, real‑time vision AI, low power inference, event‑driven processing, embedded computer vision, neuromorphic acceleration, Raspberry Pi edge AI, activity detection system...

multicorewareinc.com

 

[7für7]

First time I’ve read of a partner testing TENNs.

Designing Ultra-Low-Power Vision Pipelines on Neuromorphic Hardware

MulticoreWare, ultra‑low‑power vision pipelines, neuromorphic hardware, edge AI, temporal event‑based neural networks, TENNs, real‑time vision AI, low power inference, event‑driven processing, embedded computer vision, neuromorphic acceleration, Raspberry Pi edge AI, activity detection system...

multicorewareinc.com

A bit older, but once again like I mentioned earlier … kinda sh*t. They don’t name the thing for what it is … for whatever “reasons”…
BrainChip or Akida isn’t mentioned anywhere, but the clues are pretty obvious in my opinion: TENNs, event-based processing, ultra-low-power vision, the PCIe/RPi edge setup, and even an ARM context between the lines.

Outsiders just read “neuromorphic hardware”… insiders recognize the fingerprint.

Braini… just my opinion.